1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64TargetMachine.h"
14 #include "AArch64.h"
15 #include "AArch64MacroFusion.h"
16 #include "AArch64Subtarget.h"
17 #include "AArch64TargetObjectFile.h"
18 #include "AArch64TargetTransformInfo.h"
19 #include "MCTargetDesc/AArch64MCTargetDesc.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
24 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
25 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
26 #include "llvm/CodeGen/GlobalISel/Localizer.h"
27 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
28 #include "llvm/CodeGen/MachineScheduler.h"
29 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/CodeGen/TargetPassConfig.h"
31 #include "llvm/IR/Attributes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/MC/MCTargetOptions.h"
34 #include "llvm/Pass.h"
35 #include "llvm/Support/CodeGen.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/TargetRegistry.h"
38 #include "llvm/Target/TargetLoweringObjectFile.h"
39 #include "llvm/Target/TargetOptions.h"
40 #include "llvm/Transforms/Scalar.h"
41 #include <memory>
42 #include <string>
43 
44 using namespace llvm;
45 
46 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
47                                 cl::desc("Enable the CCMP formation pass"),
48                                 cl::init(true), cl::Hidden);
49 
50 static cl::opt<bool>
51     EnableCondBrTuning("aarch64-enable-cond-br-tune",
52                        cl::desc("Enable the conditional branch tuning pass"),
53                        cl::init(true), cl::Hidden);
54 
55 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
56                                cl::desc("Enable the machine combiner pass"),
57                                cl::init(true), cl::Hidden);
58 
59 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
60                                           cl::desc("Suppress STP for AArch64"),
61                                           cl::init(true), cl::Hidden);
62 
63 static cl::opt<bool> EnableAdvSIMDScalar(
64     "aarch64-enable-simd-scalar",
65     cl::desc("Enable use of AdvSIMD scalar integer instructions"),
66     cl::init(false), cl::Hidden);
67 
68 static cl::opt<bool>
69     EnablePromoteConstant("aarch64-enable-promote-const",
70                           cl::desc("Enable the promote constant pass"),
71                           cl::init(true), cl::Hidden);
72 
73 static cl::opt<bool> EnableCollectLOH(
74     "aarch64-enable-collect-loh",
75     cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
76     cl::init(true), cl::Hidden);
77 
78 static cl::opt<bool>
79     EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
80                                   cl::desc("Enable the pass that removes dead"
81                                            " definitons and replaces stores to"
82                                            " them with stores to the zero"
83                                            " register"),
84                                   cl::init(true));
85 
86 static cl::opt<bool> EnableRedundantCopyElimination(
87     "aarch64-enable-copyelim",
88     cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
89     cl::Hidden);
90 
91 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
92                                         cl::desc("Enable the load/store pair"
93                                                  " optimization pass"),
94                                         cl::init(true), cl::Hidden);
95 
96 static cl::opt<bool> EnableAtomicTidy(
97     "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
98     cl::desc("Run SimplifyCFG after expanding atomic operations"
99              " to make use of cmpxchg flow-based information"),
100     cl::init(true));
101 
102 static cl::opt<bool>
103 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
104                         cl::desc("Run early if-conversion"),
105                         cl::init(true));
106 
107 static cl::opt<bool>
108     EnableCondOpt("aarch64-enable-condopt",
109                   cl::desc("Enable the condition optimizer pass"),
110                   cl::init(true), cl::Hidden);
111 
112 static cl::opt<bool>
113 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
114                 cl::desc("Work around Cortex-A53 erratum 835769"),
115                 cl::init(false));
116 
117 static cl::opt<bool>
118     EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
119                  cl::desc("Enable optimizations on complex GEPs"),
120                  cl::init(false));
121 
122 static cl::opt<bool>
123     BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
124                      cl::desc("Relax out of range conditional branches"));
125 
126 // FIXME: Unify control over GlobalMerge.
127 static cl::opt<cl::boolOrDefault>
128     EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
129                       cl::desc("Enable the global merge pass"));
130 
131 static cl::opt<bool>
132     EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
133                            cl::desc("Enable the loop data prefetch pass"),
134                            cl::init(true));
135 
136 static cl::opt<int> EnableGlobalISelAtO(
137     "aarch64-enable-global-isel-at-O", cl::Hidden,
138     cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
139     cl::init(-1));
140 
141 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
142                                          cl::init(true), cl::Hidden);
143 
144 extern "C" void LLVMInitializeAArch64Target() {
145   // Register the target.
146   RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
147   RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
148   RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
149   auto PR = PassRegistry::getPassRegistry();
150   initializeGlobalISel(*PR);
151   initializeAArch64A53Fix835769Pass(*PR);
152   initializeAArch64A57FPLoadBalancingPass(*PR);
153   initializeAArch64AdvSIMDScalarPass(*PR);
154   initializeAArch64CollectLOHPass(*PR);
155   initializeAArch64ConditionalComparesPass(*PR);
156   initializeAArch64ConditionOptimizerPass(*PR);
157   initializeAArch64DeadRegisterDefinitionsPass(*PR);
158   initializeAArch64ExpandPseudoPass(*PR);
159   initializeAArch64LoadStoreOptPass(*PR);
160   initializeAArch64VectorByElementOptPass(*PR);
161   initializeAArch64PromoteConstantPass(*PR);
162   initializeAArch64RedundantCopyEliminationPass(*PR);
163   initializeAArch64StorePairSuppressPass(*PR);
164   initializeFalkorHWPFFixPass(*PR);
165   initializeFalkorMarkStridedAccessesLegacyPass(*PR);
166   initializeLDTLSCleanupPass(*PR);
167 }
168 
169 //===----------------------------------------------------------------------===//
170 // AArch64 Lowering public interface.
171 //===----------------------------------------------------------------------===//
172 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
173   if (TT.isOSBinFormatMachO())
174     return llvm::make_unique<AArch64_MachoTargetObjectFile>();
175   if (TT.isOSBinFormatCOFF())
176     return llvm::make_unique<AArch64_COFFTargetObjectFile>();
177 
178   return llvm::make_unique<AArch64_ELFTargetObjectFile>();
179 }
180 
181 // Helper function to build a DataLayout string
182 static std::string computeDataLayout(const Triple &TT,
183                                      const MCTargetOptions &Options,
184                                      bool LittleEndian) {
185   if (Options.getABIName() == "ilp32")
186     return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128";
187   if (TT.isOSBinFormatMachO())
188     return "e-m:o-i64:64-i128:128-n32:64-S128";
189   if (TT.isOSBinFormatCOFF())
190     return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
191   if (LittleEndian)
192     return "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
193   return "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
194 }
195 
196 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
197                                            Optional<Reloc::Model> RM) {
198   // AArch64 Darwin is always PIC.
199   if (TT.isOSDarwin())
200     return Reloc::PIC_;
201   // On ELF platforms the default static relocation model has a smart enough
202   // linker to cope with referencing external symbols defined in a shared
203   // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
204   if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
205     return Reloc::Static;
206   return *RM;
207 }
208 
209 /// Create an AArch64 architecture model.
210 ///
211 AArch64TargetMachine::AArch64TargetMachine(
212     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
213     const TargetOptions &Options, Optional<Reloc::Model> RM,
214     CodeModel::Model CM, CodeGenOpt::Level OL, bool LittleEndian)
215     : LLVMTargetMachine(T, computeDataLayout(TT, Options.MCOptions,
216                                              LittleEndian),
217                         TT, CPU, FS, Options,
218 			getEffectiveRelocModel(TT, RM), CM, OL),
219       TLOF(createTLOF(getTargetTriple())),
220       isLittle(LittleEndian) {
221   initAsmInfo();
222 }
223 
224 AArch64TargetMachine::~AArch64TargetMachine() = default;
225 
226 const AArch64Subtarget *
227 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
228   Attribute CPUAttr = F.getFnAttribute("target-cpu");
229   Attribute FSAttr = F.getFnAttribute("target-features");
230 
231   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
232                         ? CPUAttr.getValueAsString().str()
233                         : TargetCPU;
234   std::string FS = !FSAttr.hasAttribute(Attribute::None)
235                        ? FSAttr.getValueAsString().str()
236                        : TargetFS;
237 
238   auto &I = SubtargetMap[CPU + FS];
239   if (!I) {
240     // This needs to be done before we create a new subtarget since any
241     // creation will depend on the TM and the code generation flags on the
242     // function that reside in TargetOptions.
243     resetTargetOptions(F);
244     I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
245                                             isLittle);
246   }
247   return I.get();
248 }
249 
250 void AArch64leTargetMachine::anchor() { }
251 
252 AArch64leTargetMachine::AArch64leTargetMachine(
253     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
254     const TargetOptions &Options, Optional<Reloc::Model> RM,
255     CodeModel::Model CM, CodeGenOpt::Level OL)
256     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
257 
258 void AArch64beTargetMachine::anchor() { }
259 
260 AArch64beTargetMachine::AArch64beTargetMachine(
261     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
262     const TargetOptions &Options, Optional<Reloc::Model> RM,
263     CodeModel::Model CM, CodeGenOpt::Level OL)
264     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
265 
266 namespace {
267 
268 /// AArch64 Code Generator Pass Configuration Options.
269 class AArch64PassConfig : public TargetPassConfig {
270 public:
271   AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
272       : TargetPassConfig(TM, PM) {
273     if (TM.getOptLevel() != CodeGenOpt::None)
274       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
275   }
276 
277   AArch64TargetMachine &getAArch64TargetMachine() const {
278     return getTM<AArch64TargetMachine>();
279   }
280 
281   ScheduleDAGInstrs *
282   createMachineScheduler(MachineSchedContext *C) const override {
283     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
284     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
285     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
286     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
287     if (ST.hasFusion())
288       DAG->addMutation(createAArch64MacroFusionDAGMutation());
289     return DAG;
290   }
291 
292   ScheduleDAGInstrs *
293   createPostMachineScheduler(MachineSchedContext *C) const override {
294     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
295     if (ST.hasFusion()) {
296       // Run the Macro Fusion after RA again since literals are expanded from
297       // pseudos then (v. addPreSched2()).
298       ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
299       DAG->addMutation(createAArch64MacroFusionDAGMutation());
300       return DAG;
301     }
302 
303     return nullptr;
304   }
305 
306   void addIRPasses()  override;
307   bool addPreISel() override;
308   bool addInstSelector() override;
309 #ifdef LLVM_BUILD_GLOBAL_ISEL
310   bool addIRTranslator() override;
311   bool addLegalizeMachineIR() override;
312   bool addRegBankSelect() override;
313   void addPreGlobalInstructionSelect() override;
314   bool addGlobalInstructionSelect() override;
315 #endif
316   bool addILPOpts() override;
317   void addPreRegAlloc() override;
318   void addPostRegAlloc() override;
319   void addPreSched2() override;
320   void addPreEmitPass() override;
321 
322   bool isGlobalISelEnabled() const override;
323 };
324 
325 } // end anonymous namespace
326 
327 TargetIRAnalysis AArch64TargetMachine::getTargetIRAnalysis() {
328   return TargetIRAnalysis([this](const Function &F) {
329     return TargetTransformInfo(AArch64TTIImpl(this, F));
330   });
331 }
332 
333 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
334   return new AArch64PassConfig(*this, PM);
335 }
336 
337 void AArch64PassConfig::addIRPasses() {
338   // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
339   // ourselves.
340   addPass(createAtomicExpandPass());
341 
342   // Cmpxchg instructions are often used with a subsequent comparison to
343   // determine whether it succeeded. We can exploit existing control-flow in
344   // ldrex/strex loops to simplify this, but it needs tidying up.
345   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
346     addPass(createCFGSimplificationPass());
347 
348   // Run LoopDataPrefetch
349   //
350   // Run this before LSR to remove the multiplies involved in computing the
351   // pointer values N iterations ahead.
352   if (TM->getOptLevel() != CodeGenOpt::None) {
353     if (EnableLoopDataPrefetch)
354       addPass(createLoopDataPrefetchPass());
355     if (EnableFalkorHWPFFix)
356       addPass(createFalkorMarkStridedAccessesPass());
357   }
358 
359   TargetPassConfig::addIRPasses();
360 
361   // Match interleaved memory accesses to ldN/stN intrinsics.
362   if (TM->getOptLevel() != CodeGenOpt::None)
363     addPass(createInterleavedAccessPass());
364 
365   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
366     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
367     // and lower a GEP with multiple indices to either arithmetic operations or
368     // multiple GEPs with single index.
369     addPass(createSeparateConstOffsetFromGEPPass(TM, true));
370     // Call EarlyCSE pass to find and remove subexpressions in the lowered
371     // result.
372     addPass(createEarlyCSEPass());
373     // Do loop invariant code motion in case part of the lowered result is
374     // invariant.
375     addPass(createLICMPass());
376   }
377 }
378 
379 // Pass Pipeline Configuration
380 bool AArch64PassConfig::addPreISel() {
381   // Run promote constant before global merge, so that the promoted constants
382   // get a chance to be merged
383   if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
384     addPass(createAArch64PromoteConstantPass());
385   // FIXME: On AArch64, this depends on the type.
386   // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
387   // and the offset has to be a multiple of the related size in bytes.
388   if ((TM->getOptLevel() != CodeGenOpt::None &&
389        EnableGlobalMerge == cl::BOU_UNSET) ||
390       EnableGlobalMerge == cl::BOU_TRUE) {
391     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
392                                (EnableGlobalMerge == cl::BOU_UNSET);
393     addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize));
394   }
395 
396   return false;
397 }
398 
399 bool AArch64PassConfig::addInstSelector() {
400   addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
401 
402   // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
403   // references to _TLS_MODULE_BASE_ as possible.
404   if (TM->getTargetTriple().isOSBinFormatELF() &&
405       getOptLevel() != CodeGenOpt::None)
406     addPass(createAArch64CleanupLocalDynamicTLSPass());
407 
408   return false;
409 }
410 
411 #ifdef LLVM_BUILD_GLOBAL_ISEL
412 bool AArch64PassConfig::addIRTranslator() {
413   addPass(new IRTranslator());
414   return false;
415 }
416 
417 bool AArch64PassConfig::addLegalizeMachineIR() {
418   addPass(new Legalizer());
419   return false;
420 }
421 
422 bool AArch64PassConfig::addRegBankSelect() {
423   addPass(new RegBankSelect());
424   return false;
425 }
426 
427 void AArch64PassConfig::addPreGlobalInstructionSelect() {
428   // Workaround the deficiency of the fast register allocator.
429   if (TM->getOptLevel() == CodeGenOpt::None)
430     addPass(new Localizer());
431 }
432 
433 bool AArch64PassConfig::addGlobalInstructionSelect() {
434   addPass(new InstructionSelect());
435   return false;
436 }
437 #endif
438 
439 bool AArch64PassConfig::isGlobalISelEnabled() const {
440   return TM->getOptLevel() <= EnableGlobalISelAtO;
441 }
442 
443 bool AArch64PassConfig::addILPOpts() {
444   if (EnableCondOpt)
445     addPass(createAArch64ConditionOptimizerPass());
446   if (EnableCCMP)
447     addPass(createAArch64ConditionalCompares());
448   if (EnableMCR)
449     addPass(&MachineCombinerID);
450   if (EnableCondBrTuning)
451     addPass(createAArch64CondBrTuning());
452   if (EnableEarlyIfConversion)
453     addPass(&EarlyIfConverterID);
454   if (EnableStPairSuppress)
455     addPass(createAArch64StorePairSuppressPass());
456   addPass(createAArch64VectorByElementOptPass());
457   return true;
458 }
459 
460 void AArch64PassConfig::addPreRegAlloc() {
461   // Change dead register definitions to refer to the zero register.
462   if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
463     addPass(createAArch64DeadRegisterDefinitions());
464 
465   // Use AdvSIMD scalar instructions whenever profitable.
466   if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
467     addPass(createAArch64AdvSIMDScalar());
468     // The AdvSIMD pass may produce copies that can be rewritten to
469     // be register coaleascer friendly.
470     addPass(&PeepholeOptimizerID);
471   }
472 }
473 
474 void AArch64PassConfig::addPostRegAlloc() {
475   // Remove redundant copy instructions.
476   if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
477     addPass(createAArch64RedundantCopyEliminationPass());
478 
479   if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
480     // Improve performance for some FP/SIMD code for A57.
481     addPass(createAArch64A57FPLoadBalancing());
482 }
483 
484 void AArch64PassConfig::addPreSched2() {
485   // Expand some pseudo instructions to allow proper scheduling.
486   addPass(createAArch64ExpandPseudoPass());
487   // Use load/store pair instructions when possible.
488   if (TM->getOptLevel() != CodeGenOpt::None) {
489     if (EnableLoadStoreOpt)
490       addPass(createAArch64LoadStoreOptimizationPass());
491     if (EnableFalkorHWPFFix)
492       addPass(createFalkorHWPFFixPass());
493   }
494 }
495 
496 void AArch64PassConfig::addPreEmitPass() {
497   if (EnableA53Fix835769)
498     addPass(createAArch64A53Fix835769());
499   // Relax conditional branch instructions if they're otherwise out of
500   // range of their destination.
501   if (BranchRelaxation)
502     addPass(&BranchRelaxationPassID);
503 
504   if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
505       TM->getTargetTriple().isOSBinFormatMachO())
506     addPass(createAArch64CollectLOHPass());
507 }
508