1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "AArch64TargetMachine.h"
13 #include "AArch64.h"
14 #include "AArch64MacroFusion.h"
15 #include "AArch64Subtarget.h"
16 #include "AArch64TargetObjectFile.h"
17 #include "AArch64TargetTransformInfo.h"
18 #include "MCTargetDesc/AArch64MCTargetDesc.h"
19 #include "TargetInfo/AArch64TargetInfo.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/CSEConfigBase.h"
24 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
25 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
26 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
27 #include "llvm/CodeGen/GlobalISel/Localizer.h"
28 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
29 #include "llvm/CodeGen/MachineScheduler.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/CodeGen/TargetPassConfig.h"
32 #include "llvm/IR/Attributes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/InitializePasses.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCTargetOptions.h"
37 #include "llvm/Pass.h"
38 #include "llvm/Support/CodeGen.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Target/TargetLoweringObjectFile.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/Transforms/CFGuard.h"
44 #include "llvm/Transforms/Scalar.h"
45 #include <memory>
46 #include <string>
47 
48 using namespace llvm;
49 
50 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
51                                 cl::desc("Enable the CCMP formation pass"),
52                                 cl::init(true), cl::Hidden);
53 
54 static cl::opt<bool>
55     EnableCondBrTuning("aarch64-enable-cond-br-tune",
56                        cl::desc("Enable the conditional branch tuning pass"),
57                        cl::init(true), cl::Hidden);
58 
59 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
60                                cl::desc("Enable the machine combiner pass"),
61                                cl::init(true), cl::Hidden);
62 
63 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
64                                           cl::desc("Suppress STP for AArch64"),
65                                           cl::init(true), cl::Hidden);
66 
67 static cl::opt<bool> EnableAdvSIMDScalar(
68     "aarch64-enable-simd-scalar",
69     cl::desc("Enable use of AdvSIMD scalar integer instructions"),
70     cl::init(false), cl::Hidden);
71 
72 static cl::opt<bool>
73     EnablePromoteConstant("aarch64-enable-promote-const",
74                           cl::desc("Enable the promote constant pass"),
75                           cl::init(true), cl::Hidden);
76 
77 static cl::opt<bool> EnableCollectLOH(
78     "aarch64-enable-collect-loh",
79     cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
80     cl::init(true), cl::Hidden);
81 
82 static cl::opt<bool>
83     EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
84                                   cl::desc("Enable the pass that removes dead"
85                                            " definitons and replaces stores to"
86                                            " them with stores to the zero"
87                                            " register"),
88                                   cl::init(true));
89 
90 static cl::opt<bool> EnableRedundantCopyElimination(
91     "aarch64-enable-copyelim",
92     cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
93     cl::Hidden);
94 
95 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
96                                         cl::desc("Enable the load/store pair"
97                                                  " optimization pass"),
98                                         cl::init(true), cl::Hidden);
99 
100 static cl::opt<bool> EnableAtomicTidy(
101     "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
102     cl::desc("Run SimplifyCFG after expanding atomic operations"
103              " to make use of cmpxchg flow-based information"),
104     cl::init(true));
105 
106 static cl::opt<bool>
107 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
108                         cl::desc("Run early if-conversion"),
109                         cl::init(true));
110 
111 static cl::opt<bool>
112     EnableCondOpt("aarch64-enable-condopt",
113                   cl::desc("Enable the condition optimizer pass"),
114                   cl::init(true), cl::Hidden);
115 
116 static cl::opt<bool>
117 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
118                 cl::desc("Work around Cortex-A53 erratum 835769"),
119                 cl::init(false));
120 
121 static cl::opt<bool>
122     EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
123                  cl::desc("Enable optimizations on complex GEPs"),
124                  cl::init(false));
125 
126 static cl::opt<bool>
127     BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
128                      cl::desc("Relax out of range conditional branches"));
129 
130 static cl::opt<bool> EnableCompressJumpTables(
131     "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
132     cl::desc("Use smallest entry possible for jump tables"));
133 
134 // FIXME: Unify control over GlobalMerge.
135 static cl::opt<cl::boolOrDefault>
136     EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
137                       cl::desc("Enable the global merge pass"));
138 
139 static cl::opt<bool>
140     EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
141                            cl::desc("Enable the loop data prefetch pass"),
142                            cl::init(true));
143 
144 static cl::opt<int> EnableGlobalISelAtO(
145     "aarch64-enable-global-isel-at-O", cl::Hidden,
146     cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
147     cl::init(0));
148 
149 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
150                                          cl::init(true), cl::Hidden);
151 
152 static cl::opt<bool>
153     EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
154                         cl::desc("Enable the AAcrh64 branch target pass"),
155                         cl::init(true));
156 
157 extern "C" void LLVMInitializeAArch64Target() {
158   // Register the target.
159   RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
160   RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
161   RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
162   RegisterTargetMachine<AArch64leTargetMachine> W(getTheARM64_32Target());
163   RegisterTargetMachine<AArch64leTargetMachine> V(getTheAArch64_32Target());
164   auto PR = PassRegistry::getPassRegistry();
165   initializeGlobalISel(*PR);
166   initializeAArch64A53Fix835769Pass(*PR);
167   initializeAArch64A57FPLoadBalancingPass(*PR);
168   initializeAArch64AdvSIMDScalarPass(*PR);
169   initializeAArch64BranchTargetsPass(*PR);
170   initializeAArch64CollectLOHPass(*PR);
171   initializeAArch64CompressJumpTablesPass(*PR);
172   initializeAArch64ConditionalComparesPass(*PR);
173   initializeAArch64ConditionOptimizerPass(*PR);
174   initializeAArch64DeadRegisterDefinitionsPass(*PR);
175   initializeAArch64ExpandPseudoPass(*PR);
176   initializeAArch64LoadStoreOptPass(*PR);
177   initializeAArch64SIMDInstrOptPass(*PR);
178   initializeAArch64PreLegalizerCombinerPass(*PR);
179   initializeAArch64PromoteConstantPass(*PR);
180   initializeAArch64RedundantCopyEliminationPass(*PR);
181   initializeAArch64StorePairSuppressPass(*PR);
182   initializeFalkorHWPFFixPass(*PR);
183   initializeFalkorMarkStridedAccessesLegacyPass(*PR);
184   initializeLDTLSCleanupPass(*PR);
185   initializeAArch64SpeculationHardeningPass(*PR);
186   initializeAArch64StackTaggingPass(*PR);
187   initializeAArch64StackTaggingPreRAPass(*PR);
188 }
189 
190 //===----------------------------------------------------------------------===//
191 // AArch64 Lowering public interface.
192 //===----------------------------------------------------------------------===//
193 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
194   if (TT.isOSBinFormatMachO())
195     return std::make_unique<AArch64_MachoTargetObjectFile>();
196   if (TT.isOSBinFormatCOFF())
197     return std::make_unique<AArch64_COFFTargetObjectFile>();
198 
199   return std::make_unique<AArch64_ELFTargetObjectFile>();
200 }
201 
202 // Helper function to build a DataLayout string
203 static std::string computeDataLayout(const Triple &TT,
204                                      const MCTargetOptions &Options,
205                                      bool LittleEndian) {
206   if (Options.getABIName() == "ilp32")
207     return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128";
208   if (TT.isOSBinFormatMachO()) {
209     if (TT.getArch() == Triple::aarch64_32)
210       return "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128";
211     return "e-m:o-i64:64-i128:128-n32:64-S128";
212   }
213   if (TT.isOSBinFormatCOFF())
214     return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
215   if (LittleEndian)
216     return "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
217   return "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
218 }
219 
220 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
221                                            Optional<Reloc::Model> RM) {
222   // AArch64 Darwin and Windows are always PIC.
223   if (TT.isOSDarwin() || TT.isOSWindows())
224     return Reloc::PIC_;
225   // On ELF platforms the default static relocation model has a smart enough
226   // linker to cope with referencing external symbols defined in a shared
227   // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
228   if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
229     return Reloc::Static;
230   return *RM;
231 }
232 
233 static CodeModel::Model
234 getEffectiveAArch64CodeModel(const Triple &TT, Optional<CodeModel::Model> CM,
235                              bool JIT) {
236   if (CM) {
237     if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
238         *CM != CodeModel::Large) {
239       if (!TT.isOSFuchsia())
240         report_fatal_error(
241             "Only small, tiny and large code models are allowed on AArch64");
242       else if (*CM != CodeModel::Kernel)
243         report_fatal_error("Only small, tiny, kernel, and large code models "
244                            "are allowed on AArch64");
245     } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
246       report_fatal_error("tiny code model is only supported on ELF");
247     return *CM;
248   }
249   // The default MCJIT memory managers make no guarantees about where they can
250   // find an executable page; JITed code needs to be able to refer to globals
251   // no matter how far away they are.
252   if (JIT)
253     return CodeModel::Large;
254   return CodeModel::Small;
255 }
256 
257 /// Create an AArch64 architecture model.
258 ///
259 AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
260                                            StringRef CPU, StringRef FS,
261                                            const TargetOptions &Options,
262                                            Optional<Reloc::Model> RM,
263                                            Optional<CodeModel::Model> CM,
264                                            CodeGenOpt::Level OL, bool JIT,
265                                            bool LittleEndian)
266     : LLVMTargetMachine(T,
267                         computeDataLayout(TT, Options.MCOptions, LittleEndian),
268                         TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM),
269                         getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
270       TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
271   initAsmInfo();
272 
273   if (TT.isOSBinFormatMachO()) {
274     this->Options.TrapUnreachable = true;
275     this->Options.NoTrapAfterNoreturn = true;
276   }
277 
278   if (getMCAsmInfo()->usesWindowsCFI()) {
279     // Unwinding can get confused if the last instruction in an
280     // exception-handling region (function, funclet, try block, etc.)
281     // is a call.
282     //
283     // FIXME: We could elide the trap if the next instruction would be in
284     // the same region anyway.
285     this->Options.TrapUnreachable = true;
286   }
287 
288   // Enable GlobalISel at or below EnableGlobalISelAt0, unless this is
289   // MachO/CodeModel::Large, which GlobalISel does not support.
290   if (getOptLevel() <= EnableGlobalISelAtO &&
291       TT.getArch() != Triple::aarch64_32 &&
292       !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO())) {
293     setGlobalISel(true);
294     setGlobalISelAbort(GlobalISelAbortMode::Disable);
295   }
296 
297   // AArch64 supports the MachineOutliner.
298   setMachineOutliner(true);
299 
300   // AArch64 supports default outlining behaviour.
301   setSupportsDefaultOutlining(true);
302 }
303 
304 AArch64TargetMachine::~AArch64TargetMachine() = default;
305 
306 const AArch64Subtarget *
307 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
308   Attribute CPUAttr = F.getFnAttribute("target-cpu");
309   Attribute FSAttr = F.getFnAttribute("target-features");
310 
311   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
312                         ? CPUAttr.getValueAsString().str()
313                         : TargetCPU;
314   std::string FS = !FSAttr.hasAttribute(Attribute::None)
315                        ? FSAttr.getValueAsString().str()
316                        : TargetFS;
317 
318   auto &I = SubtargetMap[CPU + FS];
319   if (!I) {
320     // This needs to be done before we create a new subtarget since any
321     // creation will depend on the TM and the code generation flags on the
322     // function that reside in TargetOptions.
323     resetTargetOptions(F);
324     I = std::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
325                                             isLittle);
326   }
327   return I.get();
328 }
329 
330 void AArch64leTargetMachine::anchor() { }
331 
332 AArch64leTargetMachine::AArch64leTargetMachine(
333     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
334     const TargetOptions &Options, Optional<Reloc::Model> RM,
335     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
336     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
337 
338 void AArch64beTargetMachine::anchor() { }
339 
340 AArch64beTargetMachine::AArch64beTargetMachine(
341     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
342     const TargetOptions &Options, Optional<Reloc::Model> RM,
343     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
344     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
345 
346 namespace {
347 
348 /// AArch64 Code Generator Pass Configuration Options.
349 class AArch64PassConfig : public TargetPassConfig {
350 public:
351   AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
352       : TargetPassConfig(TM, PM) {
353     if (TM.getOptLevel() != CodeGenOpt::None)
354       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
355   }
356 
357   AArch64TargetMachine &getAArch64TargetMachine() const {
358     return getTM<AArch64TargetMachine>();
359   }
360 
361   ScheduleDAGInstrs *
362   createMachineScheduler(MachineSchedContext *C) const override {
363     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
364     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
365     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
366     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
367     if (ST.hasFusion())
368       DAG->addMutation(createAArch64MacroFusionDAGMutation());
369     return DAG;
370   }
371 
372   ScheduleDAGInstrs *
373   createPostMachineScheduler(MachineSchedContext *C) const override {
374     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
375     if (ST.hasFusion()) {
376       // Run the Macro Fusion after RA again since literals are expanded from
377       // pseudos then (v. addPreSched2()).
378       ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
379       DAG->addMutation(createAArch64MacroFusionDAGMutation());
380       return DAG;
381     }
382 
383     return nullptr;
384   }
385 
386   void addIRPasses()  override;
387   bool addPreISel() override;
388   bool addInstSelector() override;
389   bool addIRTranslator() override;
390   void addPreLegalizeMachineIR() override;
391   bool addLegalizeMachineIR() override;
392   bool addRegBankSelect() override;
393   void addPreGlobalInstructionSelect() override;
394   bool addGlobalInstructionSelect() override;
395   bool addILPOpts() override;
396   void addPreRegAlloc() override;
397   void addPostRegAlloc() override;
398   void addPreSched2() override;
399   void addPreEmitPass() override;
400 
401   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
402 };
403 
404 } // end anonymous namespace
405 
406 TargetTransformInfo
407 AArch64TargetMachine::getTargetTransformInfo(const Function &F) {
408   return TargetTransformInfo(AArch64TTIImpl(this, F));
409 }
410 
411 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
412   return new AArch64PassConfig(*this, PM);
413 }
414 
415 std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
416   return getStandardCSEConfigForOpt(TM->getOptLevel());
417 }
418 
419 void AArch64PassConfig::addIRPasses() {
420   // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
421   // ourselves.
422   addPass(createAtomicExpandPass());
423 
424   // Cmpxchg instructions are often used with a subsequent comparison to
425   // determine whether it succeeded. We can exploit existing control-flow in
426   // ldrex/strex loops to simplify this, but it needs tidying up.
427   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
428     addPass(createCFGSimplificationPass(1, true, true, false, true));
429 
430   // Run LoopDataPrefetch
431   //
432   // Run this before LSR to remove the multiplies involved in computing the
433   // pointer values N iterations ahead.
434   if (TM->getOptLevel() != CodeGenOpt::None) {
435     if (EnableLoopDataPrefetch)
436       addPass(createLoopDataPrefetchPass());
437     if (EnableFalkorHWPFFix)
438       addPass(createFalkorMarkStridedAccessesPass());
439   }
440 
441   TargetPassConfig::addIRPasses();
442 
443   // Match interleaved memory accesses to ldN/stN intrinsics.
444   if (TM->getOptLevel() != CodeGenOpt::None) {
445     addPass(createInterleavedLoadCombinePass());
446     addPass(createInterleavedAccessPass());
447   }
448 
449   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
450     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
451     // and lower a GEP with multiple indices to either arithmetic operations or
452     // multiple GEPs with single index.
453     addPass(createSeparateConstOffsetFromGEPPass(true));
454     // Call EarlyCSE pass to find and remove subexpressions in the lowered
455     // result.
456     addPass(createEarlyCSEPass());
457     // Do loop invariant code motion in case part of the lowered result is
458     // invariant.
459     addPass(createLICMPass());
460   }
461 
462   addPass(createAArch64StackTaggingPass(/* MergeInit = */ TM->getOptLevel() !=
463                                         CodeGenOpt::None));
464 
465   // Add Control Flow Guard checks.
466   if (TM->getTargetTriple().isOSWindows())
467     addPass(createCFGuardCheckPass());
468 }
469 
470 // Pass Pipeline Configuration
471 bool AArch64PassConfig::addPreISel() {
472   // Run promote constant before global merge, so that the promoted constants
473   // get a chance to be merged
474   if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
475     addPass(createAArch64PromoteConstantPass());
476   // FIXME: On AArch64, this depends on the type.
477   // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
478   // and the offset has to be a multiple of the related size in bytes.
479   if ((TM->getOptLevel() != CodeGenOpt::None &&
480        EnableGlobalMerge == cl::BOU_UNSET) ||
481       EnableGlobalMerge == cl::BOU_TRUE) {
482     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
483                                (EnableGlobalMerge == cl::BOU_UNSET);
484 
485     // Merging of extern globals is enabled by default on non-Mach-O as we
486     // expect it to be generally either beneficial or harmless. On Mach-O it
487     // is disabled as we emit the .subsections_via_symbols directive which
488     // means that merging extern globals is not safe.
489     bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
490 
491     // FIXME: extern global merging is only enabled when we optimise for size
492     // because there are some regressions with it also enabled for performance.
493     if (!OnlyOptimizeForSize)
494       MergeExternalByDefault = false;
495 
496     addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize,
497                                   MergeExternalByDefault));
498   }
499 
500   return false;
501 }
502 
503 bool AArch64PassConfig::addInstSelector() {
504   addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
505 
506   // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
507   // references to _TLS_MODULE_BASE_ as possible.
508   if (TM->getTargetTriple().isOSBinFormatELF() &&
509       getOptLevel() != CodeGenOpt::None)
510     addPass(createAArch64CleanupLocalDynamicTLSPass());
511 
512   return false;
513 }
514 
515 bool AArch64PassConfig::addIRTranslator() {
516   addPass(new IRTranslator());
517   return false;
518 }
519 
520 void AArch64PassConfig::addPreLegalizeMachineIR() {
521   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
522   addPass(createAArch64PreLegalizeCombiner(IsOptNone));
523 }
524 
525 bool AArch64PassConfig::addLegalizeMachineIR() {
526   addPass(new Legalizer());
527   return false;
528 }
529 
530 bool AArch64PassConfig::addRegBankSelect() {
531   addPass(new RegBankSelect());
532   return false;
533 }
534 
535 void AArch64PassConfig::addPreGlobalInstructionSelect() {
536   addPass(new Localizer());
537 }
538 
539 bool AArch64PassConfig::addGlobalInstructionSelect() {
540   addPass(new InstructionSelect());
541   return false;
542 }
543 
544 bool AArch64PassConfig::addILPOpts() {
545   if (EnableCondOpt)
546     addPass(createAArch64ConditionOptimizerPass());
547   if (EnableCCMP)
548     addPass(createAArch64ConditionalCompares());
549   if (EnableMCR)
550     addPass(&MachineCombinerID);
551   if (EnableCondBrTuning)
552     addPass(createAArch64CondBrTuning());
553   if (EnableEarlyIfConversion)
554     addPass(&EarlyIfConverterID);
555   if (EnableStPairSuppress)
556     addPass(createAArch64StorePairSuppressPass());
557   addPass(createAArch64SIMDInstrOptPass());
558   if (TM->getOptLevel() != CodeGenOpt::None)
559     addPass(createAArch64StackTaggingPreRAPass());
560   return true;
561 }
562 
563 void AArch64PassConfig::addPreRegAlloc() {
564   // Change dead register definitions to refer to the zero register.
565   if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
566     addPass(createAArch64DeadRegisterDefinitions());
567 
568   // Use AdvSIMD scalar instructions whenever profitable.
569   if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
570     addPass(createAArch64AdvSIMDScalar());
571     // The AdvSIMD pass may produce copies that can be rewritten to
572     // be register coaleascer friendly.
573     addPass(&PeepholeOptimizerID);
574   }
575 }
576 
577 void AArch64PassConfig::addPostRegAlloc() {
578   // Remove redundant copy instructions.
579   if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
580     addPass(createAArch64RedundantCopyEliminationPass());
581 
582   if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
583     // Improve performance for some FP/SIMD code for A57.
584     addPass(createAArch64A57FPLoadBalancing());
585 }
586 
587 void AArch64PassConfig::addPreSched2() {
588   // Expand some pseudo instructions to allow proper scheduling.
589   addPass(createAArch64ExpandPseudoPass());
590   // Use load/store pair instructions when possible.
591   if (TM->getOptLevel() != CodeGenOpt::None) {
592     if (EnableLoadStoreOpt)
593       addPass(createAArch64LoadStoreOptimizationPass());
594   }
595 
596   // The AArch64SpeculationHardeningPass destroys dominator tree and natural
597   // loop info, which is needed for the FalkorHWPFFixPass and also later on.
598   // Therefore, run the AArch64SpeculationHardeningPass before the
599   // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
600   // info.
601   addPass(createAArch64SpeculationHardeningPass());
602 
603   if (TM->getOptLevel() != CodeGenOpt::None) {
604     if (EnableFalkorHWPFFix)
605       addPass(createFalkorHWPFFixPass());
606   }
607 }
608 
609 void AArch64PassConfig::addPreEmitPass() {
610   // Machine Block Placement might have created new opportunities when run
611   // at O3, where the Tail Duplication Threshold is set to 4 instructions.
612   // Run the load/store optimizer once more.
613   if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt)
614     addPass(createAArch64LoadStoreOptimizationPass());
615 
616   if (EnableA53Fix835769)
617     addPass(createAArch64A53Fix835769());
618 
619   if (EnableBranchTargets)
620     addPass(createAArch64BranchTargetsPass());
621 
622   // Relax conditional branch instructions if they're otherwise out of
623   // range of their destination.
624   if (BranchRelaxation)
625     addPass(&BranchRelaxationPassID);
626 
627   // Identify valid longjmp targets for Windows Control Flow Guard.
628   if (TM->getTargetTriple().isOSWindows())
629     addPass(createCFGuardLongjmpPass());
630 
631   if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
632     addPass(createAArch64CompressJumpTablesPass());
633 
634   if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
635       TM->getTargetTriple().isOSBinFormatMachO())
636     addPass(createAArch64CollectLOHPass());
637 }
638