1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "AArch64TargetMachine.h"
13 #include "AArch64.h"
14 #include "AArch64MachineFunctionInfo.h"
15 #include "AArch64MacroFusion.h"
16 #include "AArch64Subtarget.h"
17 #include "AArch64TargetObjectFile.h"
18 #include "AArch64TargetTransformInfo.h"
19 #include "MCTargetDesc/AArch64MCTargetDesc.h"
20 #include "TargetInfo/AArch64TargetInfo.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/Analysis/TargetTransformInfo.h"
24 #include "llvm/CodeGen/CSEConfigBase.h"
25 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
26 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
27 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
28 #include "llvm/CodeGen/GlobalISel/Localizer.h"
29 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
30 #include "llvm/CodeGen/MIRParser/MIParser.h"
31 #include "llvm/CodeGen/MachineScheduler.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/CodeGen/TargetPassConfig.h"
34 #include "llvm/IR/Attributes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/InitializePasses.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCTargetOptions.h"
39 #include "llvm/Pass.h"
40 #include "llvm/Support/CodeGen.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/TargetRegistry.h"
43 #include "llvm/Target/TargetLoweringObjectFile.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Transforms/CFGuard.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include <memory>
48 #include <string>
49 
50 using namespace llvm;
51 
52 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
53                                 cl::desc("Enable the CCMP formation pass"),
54                                 cl::init(true), cl::Hidden);
55 
56 static cl::opt<bool>
57     EnableCondBrTuning("aarch64-enable-cond-br-tune",
58                        cl::desc("Enable the conditional branch tuning pass"),
59                        cl::init(true), cl::Hidden);
60 
61 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
62                                cl::desc("Enable the machine combiner pass"),
63                                cl::init(true), cl::Hidden);
64 
65 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
66                                           cl::desc("Suppress STP for AArch64"),
67                                           cl::init(true), cl::Hidden);
68 
69 static cl::opt<bool> EnableAdvSIMDScalar(
70     "aarch64-enable-simd-scalar",
71     cl::desc("Enable use of AdvSIMD scalar integer instructions"),
72     cl::init(false), cl::Hidden);
73 
74 static cl::opt<bool>
75     EnablePromoteConstant("aarch64-enable-promote-const",
76                           cl::desc("Enable the promote constant pass"),
77                           cl::init(true), cl::Hidden);
78 
79 static cl::opt<bool> EnableCollectLOH(
80     "aarch64-enable-collect-loh",
81     cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
82     cl::init(true), cl::Hidden);
83 
84 static cl::opt<bool>
85     EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
86                                   cl::desc("Enable the pass that removes dead"
87                                            " definitons and replaces stores to"
88                                            " them with stores to the zero"
89                                            " register"),
90                                   cl::init(true));
91 
92 static cl::opt<bool> EnableRedundantCopyElimination(
93     "aarch64-enable-copyelim",
94     cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
95     cl::Hidden);
96 
97 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
98                                         cl::desc("Enable the load/store pair"
99                                                  " optimization pass"),
100                                         cl::init(true), cl::Hidden);
101 
102 static cl::opt<bool> EnableAtomicTidy(
103     "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
104     cl::desc("Run SimplifyCFG after expanding atomic operations"
105              " to make use of cmpxchg flow-based information"),
106     cl::init(true));
107 
108 static cl::opt<bool>
109 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
110                         cl::desc("Run early if-conversion"),
111                         cl::init(true));
112 
113 static cl::opt<bool>
114     EnableCondOpt("aarch64-enable-condopt",
115                   cl::desc("Enable the condition optimizer pass"),
116                   cl::init(true), cl::Hidden);
117 
118 static cl::opt<bool>
119 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
120                 cl::desc("Work around Cortex-A53 erratum 835769"),
121                 cl::init(false));
122 
123 static cl::opt<bool>
124     EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
125                  cl::desc("Enable optimizations on complex GEPs"),
126                  cl::init(false));
127 
128 static cl::opt<bool>
129     BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
130                      cl::desc("Relax out of range conditional branches"));
131 
132 static cl::opt<bool> EnableCompressJumpTables(
133     "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
134     cl::desc("Use smallest entry possible for jump tables"));
135 
136 // FIXME: Unify control over GlobalMerge.
137 static cl::opt<cl::boolOrDefault>
138     EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
139                       cl::desc("Enable the global merge pass"));
140 
141 static cl::opt<bool>
142     EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
143                            cl::desc("Enable the loop data prefetch pass"),
144                            cl::init(true));
145 
146 static cl::opt<int> EnableGlobalISelAtO(
147     "aarch64-enable-global-isel-at-O", cl::Hidden,
148     cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
149     cl::init(0));
150 
151 static cl::opt<bool>
152     EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden,
153                            cl::desc("Enable SVE intrinsic opts"),
154                            cl::init(true));
155 
156 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
157                                          cl::init(true), cl::Hidden);
158 
159 static cl::opt<bool>
160     EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
161                         cl::desc("Enable the AAcrh64 branch target pass"),
162                         cl::init(true));
163 
164 extern cl::opt<bool> EnableHomogeneousPrologEpilog;
165 
166 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() {
167   // Register the target.
168   RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
169   RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
170   RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
171   RegisterTargetMachine<AArch64leTargetMachine> W(getTheARM64_32Target());
172   RegisterTargetMachine<AArch64leTargetMachine> V(getTheAArch64_32Target());
173   auto PR = PassRegistry::getPassRegistry();
174   initializeGlobalISel(*PR);
175   initializeAArch64A53Fix835769Pass(*PR);
176   initializeAArch64A57FPLoadBalancingPass(*PR);
177   initializeAArch64AdvSIMDScalarPass(*PR);
178   initializeAArch64BranchTargetsPass(*PR);
179   initializeAArch64CollectLOHPass(*PR);
180   initializeAArch64CompressJumpTablesPass(*PR);
181   initializeAArch64ConditionalComparesPass(*PR);
182   initializeAArch64ConditionOptimizerPass(*PR);
183   initializeAArch64DeadRegisterDefinitionsPass(*PR);
184   initializeAArch64ExpandPseudoPass(*PR);
185   initializeAArch64LoadStoreOptPass(*PR);
186   initializeAArch64SIMDInstrOptPass(*PR);
187   initializeAArch64PreLegalizerCombinerPass(*PR);
188   initializeAArch64PostLegalizerCombinerPass(*PR);
189   initializeAArch64PostLegalizerLoweringPass(*PR);
190   initializeAArch64PostSelectOptimizePass(*PR);
191   initializeAArch64PromoteConstantPass(*PR);
192   initializeAArch64RedundantCopyEliminationPass(*PR);
193   initializeAArch64StorePairSuppressPass(*PR);
194   initializeFalkorHWPFFixPass(*PR);
195   initializeFalkorMarkStridedAccessesLegacyPass(*PR);
196   initializeLDTLSCleanupPass(*PR);
197   initializeSVEIntrinsicOptsPass(*PR);
198   initializeAArch64SpeculationHardeningPass(*PR);
199   initializeAArch64SLSHardeningPass(*PR);
200   initializeAArch64StackTaggingPass(*PR);
201   initializeAArch64StackTaggingPreRAPass(*PR);
202   initializeAArch64LowerHomogeneousPrologEpilogPass(*PR);
203 }
204 
205 //===----------------------------------------------------------------------===//
206 // AArch64 Lowering public interface.
207 //===----------------------------------------------------------------------===//
208 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
209   if (TT.isOSBinFormatMachO())
210     return std::make_unique<AArch64_MachoTargetObjectFile>();
211   if (TT.isOSBinFormatCOFF())
212     return std::make_unique<AArch64_COFFTargetObjectFile>();
213 
214   return std::make_unique<AArch64_ELFTargetObjectFile>();
215 }
216 
217 // Helper function to build a DataLayout string
218 static std::string computeDataLayout(const Triple &TT,
219                                      const MCTargetOptions &Options,
220                                      bool LittleEndian) {
221   if (TT.isOSBinFormatMachO()) {
222     if (TT.getArch() == Triple::aarch64_32)
223       return "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128";
224     return "e-m:o-i64:64-i128:128-n32:64-S128";
225   }
226   if (TT.isOSBinFormatCOFF())
227     return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
228   std::string Endian = LittleEndian ? "e" : "E";
229   std::string Ptr32 = TT.getEnvironment() == Triple::GNUILP32 ? "-p:32:32" : "";
230   return Endian + "-m:e" + Ptr32 +
231          "-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
232 }
233 
234 static StringRef computeDefaultCPU(const Triple &TT, StringRef CPU) {
235   if (CPU.empty() && TT.isArm64e())
236     return "apple-a12";
237   return CPU;
238 }
239 
240 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
241                                            Optional<Reloc::Model> RM) {
242   // AArch64 Darwin and Windows are always PIC.
243   if (TT.isOSDarwin() || TT.isOSWindows())
244     return Reloc::PIC_;
245   // On ELF platforms the default static relocation model has a smart enough
246   // linker to cope with referencing external symbols defined in a shared
247   // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
248   if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
249     return Reloc::Static;
250   return *RM;
251 }
252 
253 static CodeModel::Model
254 getEffectiveAArch64CodeModel(const Triple &TT, Optional<CodeModel::Model> CM,
255                              bool JIT) {
256   if (CM) {
257     if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
258         *CM != CodeModel::Large) {
259       report_fatal_error(
260           "Only small, tiny and large code models are allowed on AArch64");
261     } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
262       report_fatal_error("tiny code model is only supported on ELF");
263     return *CM;
264   }
265   // The default MCJIT memory managers make no guarantees about where they can
266   // find an executable page; JITed code needs to be able to refer to globals
267   // no matter how far away they are.
268   // We should set the CodeModel::Small for Windows ARM64 in JIT mode,
269   // since with large code model LLVM generating 4 MOV instructions, and
270   // Windows doesn't support relocating these long branch (4 MOVs).
271   if (JIT && !TT.isOSWindows())
272     return CodeModel::Large;
273   return CodeModel::Small;
274 }
275 
276 /// Create an AArch64 architecture model.
277 ///
278 AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
279                                            StringRef CPU, StringRef FS,
280                                            const TargetOptions &Options,
281                                            Optional<Reloc::Model> RM,
282                                            Optional<CodeModel::Model> CM,
283                                            CodeGenOpt::Level OL, bool JIT,
284                                            bool LittleEndian)
285     : LLVMTargetMachine(T,
286                         computeDataLayout(TT, Options.MCOptions, LittleEndian),
287                         TT, computeDefaultCPU(TT, CPU), FS, Options,
288                         getEffectiveRelocModel(TT, RM),
289                         getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
290       TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
291   initAsmInfo();
292 
293   if (TT.isOSBinFormatMachO()) {
294     this->Options.TrapUnreachable = true;
295     this->Options.NoTrapAfterNoreturn = true;
296   }
297 
298   if (getMCAsmInfo()->usesWindowsCFI()) {
299     // Unwinding can get confused if the last instruction in an
300     // exception-handling region (function, funclet, try block, etc.)
301     // is a call.
302     //
303     // FIXME: We could elide the trap if the next instruction would be in
304     // the same region anyway.
305     this->Options.TrapUnreachable = true;
306   }
307 
308   if (this->Options.TLSSize == 0) // default
309     this->Options.TLSSize = 24;
310   if ((getCodeModel() == CodeModel::Small ||
311        getCodeModel() == CodeModel::Kernel) &&
312       this->Options.TLSSize > 32)
313     // for the small (and kernel) code model, the maximum TLS size is 4GiB
314     this->Options.TLSSize = 32;
315   else if (getCodeModel() == CodeModel::Tiny && this->Options.TLSSize > 24)
316     // for the tiny code model, the maximum TLS size is 1MiB (< 16MiB)
317     this->Options.TLSSize = 24;
318 
319   // Enable GlobalISel at or below EnableGlobalISelAt0, unless this is
320   // MachO/CodeModel::Large, which GlobalISel does not support.
321   if (getOptLevel() <= EnableGlobalISelAtO &&
322       TT.getArch() != Triple::aarch64_32 &&
323       TT.getEnvironment() != Triple::GNUILP32 &&
324       !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO())) {
325     setGlobalISel(true);
326     setGlobalISelAbort(GlobalISelAbortMode::Disable);
327   }
328 
329   // AArch64 supports the MachineOutliner.
330   setMachineOutliner(true);
331 
332   // AArch64 supports default outlining behaviour.
333   setSupportsDefaultOutlining(true);
334 
335   // AArch64 supports the debug entry values.
336   setSupportsDebugEntryValues(true);
337 }
338 
339 AArch64TargetMachine::~AArch64TargetMachine() = default;
340 
341 const AArch64Subtarget *
342 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
343   Attribute CPUAttr = F.getFnAttribute("target-cpu");
344   Attribute FSAttr = F.getFnAttribute("target-features");
345 
346   std::string CPU =
347       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
348   std::string FS =
349       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
350 
351   auto &I = SubtargetMap[CPU + FS];
352   if (!I) {
353     // This needs to be done before we create a new subtarget since any
354     // creation will depend on the TM and the code generation flags on the
355     // function that reside in TargetOptions.
356     resetTargetOptions(F);
357     I = std::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
358                                             isLittle);
359   }
360   return I.get();
361 }
362 
363 void AArch64leTargetMachine::anchor() { }
364 
365 AArch64leTargetMachine::AArch64leTargetMachine(
366     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
367     const TargetOptions &Options, Optional<Reloc::Model> RM,
368     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
369     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
370 
371 void AArch64beTargetMachine::anchor() { }
372 
373 AArch64beTargetMachine::AArch64beTargetMachine(
374     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
375     const TargetOptions &Options, Optional<Reloc::Model> RM,
376     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
377     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
378 
379 namespace {
380 
381 /// AArch64 Code Generator Pass Configuration Options.
382 class AArch64PassConfig : public TargetPassConfig {
383 public:
384   AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
385       : TargetPassConfig(TM, PM) {
386     if (TM.getOptLevel() != CodeGenOpt::None)
387       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
388   }
389 
390   AArch64TargetMachine &getAArch64TargetMachine() const {
391     return getTM<AArch64TargetMachine>();
392   }
393 
394   ScheduleDAGInstrs *
395   createMachineScheduler(MachineSchedContext *C) const override {
396     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
397     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
398     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
399     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
400     if (ST.hasFusion())
401       DAG->addMutation(createAArch64MacroFusionDAGMutation());
402     return DAG;
403   }
404 
405   ScheduleDAGInstrs *
406   createPostMachineScheduler(MachineSchedContext *C) const override {
407     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
408     if (ST.hasFusion()) {
409       // Run the Macro Fusion after RA again since literals are expanded from
410       // pseudos then (v. addPreSched2()).
411       ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
412       DAG->addMutation(createAArch64MacroFusionDAGMutation());
413       return DAG;
414     }
415 
416     return nullptr;
417   }
418 
419   void addIRPasses()  override;
420   bool addPreISel() override;
421   bool addInstSelector() override;
422   bool addIRTranslator() override;
423   void addPreLegalizeMachineIR() override;
424   bool addLegalizeMachineIR() override;
425   void addPreRegBankSelect() override;
426   bool addRegBankSelect() override;
427   void addPreGlobalInstructionSelect() override;
428   bool addGlobalInstructionSelect() override;
429   bool addILPOpts() override;
430   void addPreRegAlloc() override;
431   void addPostRegAlloc() override;
432   void addPreSched2() override;
433   void addPreEmitPass() override;
434   void addPreEmitPass2() override;
435 
436   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
437 };
438 
439 } // end anonymous namespace
440 
441 TargetTransformInfo
442 AArch64TargetMachine::getTargetTransformInfo(const Function &F) {
443   return TargetTransformInfo(AArch64TTIImpl(this, F));
444 }
445 
446 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
447   return new AArch64PassConfig(*this, PM);
448 }
449 
450 std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
451   return getStandardCSEConfigForOpt(TM->getOptLevel());
452 }
453 
454 void AArch64PassConfig::addIRPasses() {
455   // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
456   // ourselves.
457   addPass(createAtomicExpandPass());
458 
459   // Expand any SVE vector library calls that we can't code generate directly.
460   if (EnableSVEIntrinsicOpts && TM->getOptLevel() == CodeGenOpt::Aggressive)
461     addPass(createSVEIntrinsicOptsPass());
462 
463   // Cmpxchg instructions are often used with a subsequent comparison to
464   // determine whether it succeeded. We can exploit existing control-flow in
465   // ldrex/strex loops to simplify this, but it needs tidying up.
466   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
467     addPass(createCFGSimplificationPass(SimplifyCFGOptions()
468                                             .forwardSwitchCondToPhi(true)
469                                             .convertSwitchToLookupTable(true)
470                                             .needCanonicalLoops(false)
471                                             .hoistCommonInsts(true)
472                                             .sinkCommonInsts(true)));
473 
474   // Run LoopDataPrefetch
475   //
476   // Run this before LSR to remove the multiplies involved in computing the
477   // pointer values N iterations ahead.
478   if (TM->getOptLevel() != CodeGenOpt::None) {
479     if (EnableLoopDataPrefetch)
480       addPass(createLoopDataPrefetchPass());
481     if (EnableFalkorHWPFFix)
482       addPass(createFalkorMarkStridedAccessesPass());
483   }
484 
485   TargetPassConfig::addIRPasses();
486 
487   addPass(createAArch64StackTaggingPass(
488       /*IsOptNone=*/TM->getOptLevel() == CodeGenOpt::None));
489 
490   // Match interleaved memory accesses to ldN/stN intrinsics.
491   if (TM->getOptLevel() != CodeGenOpt::None) {
492     addPass(createInterleavedLoadCombinePass());
493     addPass(createInterleavedAccessPass());
494   }
495 
496   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
497     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
498     // and lower a GEP with multiple indices to either arithmetic operations or
499     // multiple GEPs with single index.
500     addPass(createSeparateConstOffsetFromGEPPass(true));
501     // Call EarlyCSE pass to find and remove subexpressions in the lowered
502     // result.
503     addPass(createEarlyCSEPass());
504     // Do loop invariant code motion in case part of the lowered result is
505     // invariant.
506     addPass(createLICMPass());
507   }
508 
509   // Add Control Flow Guard checks.
510   if (TM->getTargetTriple().isOSWindows())
511     addPass(createCFGuardCheckPass());
512 }
513 
514 // Pass Pipeline Configuration
515 bool AArch64PassConfig::addPreISel() {
516   // Run promote constant before global merge, so that the promoted constants
517   // get a chance to be merged
518   if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
519     addPass(createAArch64PromoteConstantPass());
520   // FIXME: On AArch64, this depends on the type.
521   // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
522   // and the offset has to be a multiple of the related size in bytes.
523   if ((TM->getOptLevel() != CodeGenOpt::None &&
524        EnableGlobalMerge == cl::BOU_UNSET) ||
525       EnableGlobalMerge == cl::BOU_TRUE) {
526     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
527                                (EnableGlobalMerge == cl::BOU_UNSET);
528 
529     // Merging of extern globals is enabled by default on non-Mach-O as we
530     // expect it to be generally either beneficial or harmless. On Mach-O it
531     // is disabled as we emit the .subsections_via_symbols directive which
532     // means that merging extern globals is not safe.
533     bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
534 
535     // FIXME: extern global merging is only enabled when we optimise for size
536     // because there are some regressions with it also enabled for performance.
537     if (!OnlyOptimizeForSize)
538       MergeExternalByDefault = false;
539 
540     addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize,
541                                   MergeExternalByDefault));
542   }
543 
544   return false;
545 }
546 
547 bool AArch64PassConfig::addInstSelector() {
548   addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
549 
550   // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
551   // references to _TLS_MODULE_BASE_ as possible.
552   if (TM->getTargetTriple().isOSBinFormatELF() &&
553       getOptLevel() != CodeGenOpt::None)
554     addPass(createAArch64CleanupLocalDynamicTLSPass());
555 
556   return false;
557 }
558 
559 bool AArch64PassConfig::addIRTranslator() {
560   addPass(new IRTranslator(getOptLevel()));
561   return false;
562 }
563 
564 void AArch64PassConfig::addPreLegalizeMachineIR() {
565   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
566   addPass(createAArch64PreLegalizerCombiner(IsOptNone));
567 }
568 
569 bool AArch64PassConfig::addLegalizeMachineIR() {
570   addPass(new Legalizer());
571   return false;
572 }
573 
574 void AArch64PassConfig::addPreRegBankSelect() {
575   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
576   if (!IsOptNone)
577     addPass(createAArch64PostLegalizerCombiner(IsOptNone));
578   addPass(createAArch64PostLegalizerLowering());
579 }
580 
581 bool AArch64PassConfig::addRegBankSelect() {
582   addPass(new RegBankSelect());
583   return false;
584 }
585 
586 void AArch64PassConfig::addPreGlobalInstructionSelect() {
587   addPass(new Localizer());
588 }
589 
590 bool AArch64PassConfig::addGlobalInstructionSelect() {
591   addPass(new InstructionSelect(getOptLevel()));
592   if (getOptLevel() != CodeGenOpt::None)
593     addPass(createAArch64PostSelectOptimize());
594   return false;
595 }
596 
597 bool AArch64PassConfig::addILPOpts() {
598   if (EnableCondOpt)
599     addPass(createAArch64ConditionOptimizerPass());
600   if (EnableCCMP)
601     addPass(createAArch64ConditionalCompares());
602   if (EnableMCR)
603     addPass(&MachineCombinerID);
604   if (EnableCondBrTuning)
605     addPass(createAArch64CondBrTuning());
606   if (EnableEarlyIfConversion)
607     addPass(&EarlyIfConverterID);
608   if (EnableStPairSuppress)
609     addPass(createAArch64StorePairSuppressPass());
610   addPass(createAArch64SIMDInstrOptPass());
611   if (TM->getOptLevel() != CodeGenOpt::None)
612     addPass(createAArch64StackTaggingPreRAPass());
613   return true;
614 }
615 
616 void AArch64PassConfig::addPreRegAlloc() {
617   // Change dead register definitions to refer to the zero register.
618   if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
619     addPass(createAArch64DeadRegisterDefinitions());
620 
621   // Use AdvSIMD scalar instructions whenever profitable.
622   if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
623     addPass(createAArch64AdvSIMDScalar());
624     // The AdvSIMD pass may produce copies that can be rewritten to
625     // be register coalescer friendly.
626     addPass(&PeepholeOptimizerID);
627   }
628 }
629 
630 void AArch64PassConfig::addPostRegAlloc() {
631   // Remove redundant copy instructions.
632   if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
633     addPass(createAArch64RedundantCopyEliminationPass());
634 
635   if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
636     // Improve performance for some FP/SIMD code for A57.
637     addPass(createAArch64A57FPLoadBalancing());
638 }
639 
640 void AArch64PassConfig::addPreSched2() {
641   // Lower homogeneous frame instructions
642   if (EnableHomogeneousPrologEpilog)
643     addPass(createAArch64LowerHomogeneousPrologEpilogPass());
644   // Expand some pseudo instructions to allow proper scheduling.
645   addPass(createAArch64ExpandPseudoPass());
646   // Use load/store pair instructions when possible.
647   if (TM->getOptLevel() != CodeGenOpt::None) {
648     if (EnableLoadStoreOpt)
649       addPass(createAArch64LoadStoreOptimizationPass());
650   }
651 
652   // The AArch64SpeculationHardeningPass destroys dominator tree and natural
653   // loop info, which is needed for the FalkorHWPFFixPass and also later on.
654   // Therefore, run the AArch64SpeculationHardeningPass before the
655   // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
656   // info.
657   addPass(createAArch64SpeculationHardeningPass());
658 
659   addPass(createAArch64IndirectThunks());
660   addPass(createAArch64SLSHardeningPass());
661 
662   if (TM->getOptLevel() != CodeGenOpt::None) {
663     if (EnableFalkorHWPFFix)
664       addPass(createFalkorHWPFFixPass());
665   }
666 }
667 
668 void AArch64PassConfig::addPreEmitPass() {
669   // Machine Block Placement might have created new opportunities when run
670   // at O3, where the Tail Duplication Threshold is set to 4 instructions.
671   // Run the load/store optimizer once more.
672   if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt)
673     addPass(createAArch64LoadStoreOptimizationPass());
674 
675   if (EnableA53Fix835769)
676     addPass(createAArch64A53Fix835769());
677 
678   if (EnableBranchTargets)
679     addPass(createAArch64BranchTargetsPass());
680 
681   // Relax conditional branch instructions if they're otherwise out of
682   // range of their destination.
683   if (BranchRelaxation)
684     addPass(&BranchRelaxationPassID);
685 
686   if (TM->getTargetTriple().isOSWindows()) {
687     // Identify valid longjmp targets for Windows Control Flow Guard.
688     addPass(createCFGuardLongjmpPass());
689     // Identify valid eh continuation targets for Windows EHCont Guard.
690     addPass(createEHContGuardCatchretPass());
691   }
692 
693   if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
694     addPass(createAArch64CompressJumpTablesPass());
695 
696   if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
697       TM->getTargetTriple().isOSBinFormatMachO())
698     addPass(createAArch64CollectLOHPass());
699 }
700 
701 void AArch64PassConfig::addPreEmitPass2() {
702   // SVE bundles move prefixes with destructive operations. BLR_RVMARKER pseudo
703   // instructions are lowered to bundles as well.
704   addPass(createUnpackMachineBundles(nullptr));
705 }
706 
707 yaml::MachineFunctionInfo *
708 AArch64TargetMachine::createDefaultFuncInfoYAML() const {
709   return new yaml::AArch64FunctionInfo();
710 }
711 
712 yaml::MachineFunctionInfo *
713 AArch64TargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
714   const auto *MFI = MF.getInfo<AArch64FunctionInfo>();
715   return new yaml::AArch64FunctionInfo(*MFI);
716 }
717 
718 bool AArch64TargetMachine::parseMachineFunctionInfo(
719     const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS,
720     SMDiagnostic &Error, SMRange &SourceRange) const {
721   const auto &YamlMFI =
722       reinterpret_cast<const yaml::AArch64FunctionInfo &>(MFI);
723   MachineFunction &MF = PFS.MF;
724   MF.getInfo<AArch64FunctionInfo>()->initializeBaseYamlFields(YamlMFI);
725   return false;
726 }
727