1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "AArch64TargetMachine.h"
13 #include "AArch64.h"
14 #include "AArch64MacroFusion.h"
15 #include "AArch64Subtarget.h"
16 #include "AArch64TargetObjectFile.h"
17 #include "AArch64TargetTransformInfo.h"
18 #include "MCTargetDesc/AArch64MCTargetDesc.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/Triple.h"
21 #include "llvm/Analysis/TargetTransformInfo.h"
22 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
23 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
24 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
25 #include "llvm/CodeGen/GlobalISel/Localizer.h"
26 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
27 #include "llvm/CodeGen/MachineScheduler.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/CodeGen/TargetPassConfig.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/MC/MCTargetOptions.h"
34 #include "llvm/Pass.h"
35 #include "llvm/Support/CodeGen.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/TargetRegistry.h"
38 #include "llvm/Target/TargetLoweringObjectFile.h"
39 #include "llvm/Target/TargetOptions.h"
40 #include "llvm/Transforms/Scalar.h"
41 #include <memory>
42 #include <string>
43 
44 using namespace llvm;
45 
46 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
47                                 cl::desc("Enable the CCMP formation pass"),
48                                 cl::init(true), cl::Hidden);
49 
50 static cl::opt<bool>
51     EnableCondBrTuning("aarch64-enable-cond-br-tune",
52                        cl::desc("Enable the conditional branch tuning pass"),
53                        cl::init(true), cl::Hidden);
54 
55 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
56                                cl::desc("Enable the machine combiner pass"),
57                                cl::init(true), cl::Hidden);
58 
59 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
60                                           cl::desc("Suppress STP for AArch64"),
61                                           cl::init(true), cl::Hidden);
62 
63 static cl::opt<bool> EnableAdvSIMDScalar(
64     "aarch64-enable-simd-scalar",
65     cl::desc("Enable use of AdvSIMD scalar integer instructions"),
66     cl::init(false), cl::Hidden);
67 
68 static cl::opt<bool>
69     EnablePromoteConstant("aarch64-enable-promote-const",
70                           cl::desc("Enable the promote constant pass"),
71                           cl::init(true), cl::Hidden);
72 
73 static cl::opt<bool> EnableCollectLOH(
74     "aarch64-enable-collect-loh",
75     cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
76     cl::init(true), cl::Hidden);
77 
78 static cl::opt<bool>
79     EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
80                                   cl::desc("Enable the pass that removes dead"
81                                            " definitons and replaces stores to"
82                                            " them with stores to the zero"
83                                            " register"),
84                                   cl::init(true));
85 
86 static cl::opt<bool> EnableRedundantCopyElimination(
87     "aarch64-enable-copyelim",
88     cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
89     cl::Hidden);
90 
91 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
92                                         cl::desc("Enable the load/store pair"
93                                                  " optimization pass"),
94                                         cl::init(true), cl::Hidden);
95 
96 static cl::opt<bool> EnableAtomicTidy(
97     "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
98     cl::desc("Run SimplifyCFG after expanding atomic operations"
99              " to make use of cmpxchg flow-based information"),
100     cl::init(true));
101 
102 static cl::opt<bool>
103 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
104                         cl::desc("Run early if-conversion"),
105                         cl::init(true));
106 
107 static cl::opt<bool>
108     EnableCondOpt("aarch64-enable-condopt",
109                   cl::desc("Enable the condition optimizer pass"),
110                   cl::init(true), cl::Hidden);
111 
112 static cl::opt<bool>
113 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
114                 cl::desc("Work around Cortex-A53 erratum 835769"),
115                 cl::init(false));
116 
117 static cl::opt<bool>
118     EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
119                  cl::desc("Enable optimizations on complex GEPs"),
120                  cl::init(false));
121 
122 static cl::opt<bool>
123     BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
124                      cl::desc("Relax out of range conditional branches"));
125 
126 static cl::opt<bool> EnableCompressJumpTables(
127     "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
128     cl::desc("Use smallest entry possible for jump tables"));
129 
130 // FIXME: Unify control over GlobalMerge.
131 static cl::opt<cl::boolOrDefault>
132     EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
133                       cl::desc("Enable the global merge pass"));
134 
135 static cl::opt<bool>
136     EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
137                            cl::desc("Enable the loop data prefetch pass"),
138                            cl::init(true));
139 
140 static cl::opt<int> EnableGlobalISelAtO(
141     "aarch64-enable-global-isel-at-O", cl::Hidden,
142     cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
143     cl::init(0));
144 
145 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
146                                          cl::init(true), cl::Hidden);
147 
148 static cl::opt<bool>
149     EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
150                         cl::desc("Enable the AAcrh64 branch target pass"),
151                         cl::init(true));
152 
153 extern "C" void LLVMInitializeAArch64Target() {
154   // Register the target.
155   RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
156   RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
157   RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
158   auto PR = PassRegistry::getPassRegistry();
159   initializeGlobalISel(*PR);
160   initializeAArch64A53Fix835769Pass(*PR);
161   initializeAArch64A57FPLoadBalancingPass(*PR);
162   initializeAArch64AdvSIMDScalarPass(*PR);
163   initializeAArch64BranchTargetsPass(*PR);
164   initializeAArch64CollectLOHPass(*PR);
165   initializeAArch64CompressJumpTablesPass(*PR);
166   initializeAArch64ConditionalComparesPass(*PR);
167   initializeAArch64ConditionOptimizerPass(*PR);
168   initializeAArch64DeadRegisterDefinitionsPass(*PR);
169   initializeAArch64ExpandPseudoPass(*PR);
170   initializeAArch64LoadStoreOptPass(*PR);
171   initializeAArch64SIMDInstrOptPass(*PR);
172   initializeAArch64PreLegalizerCombinerPass(*PR);
173   initializeAArch64PromoteConstantPass(*PR);
174   initializeAArch64RedundantCopyEliminationPass(*PR);
175   initializeAArch64StorePairSuppressPass(*PR);
176   initializeFalkorHWPFFixPass(*PR);
177   initializeFalkorMarkStridedAccessesLegacyPass(*PR);
178   initializeLDTLSCleanupPass(*PR);
179   initializeAArch64SpeculationHardeningPass(*PR);
180 }
181 
182 //===----------------------------------------------------------------------===//
183 // AArch64 Lowering public interface.
184 //===----------------------------------------------------------------------===//
185 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
186   if (TT.isOSBinFormatMachO())
187     return llvm::make_unique<AArch64_MachoTargetObjectFile>();
188   if (TT.isOSBinFormatCOFF())
189     return llvm::make_unique<AArch64_COFFTargetObjectFile>();
190 
191   return llvm::make_unique<AArch64_ELFTargetObjectFile>();
192 }
193 
194 // Helper function to build a DataLayout string
195 static std::string computeDataLayout(const Triple &TT,
196                                      const MCTargetOptions &Options,
197                                      bool LittleEndian) {
198   if (Options.getABIName() == "ilp32")
199     return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128";
200   if (TT.isOSBinFormatMachO())
201     return "e-m:o-i64:64-i128:128-n32:64-S128";
202   if (TT.isOSBinFormatCOFF())
203     return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
204   if (LittleEndian)
205     return "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
206   return "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
207 }
208 
209 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
210                                            Optional<Reloc::Model> RM) {
211   // AArch64 Darwin and Windows are always PIC.
212   if (TT.isOSDarwin() || TT.isOSWindows())
213     return Reloc::PIC_;
214   // On ELF platforms the default static relocation model has a smart enough
215   // linker to cope with referencing external symbols defined in a shared
216   // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
217   if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
218     return Reloc::Static;
219   return *RM;
220 }
221 
222 static CodeModel::Model
223 getEffectiveAArch64CodeModel(const Triple &TT, Optional<CodeModel::Model> CM,
224                              bool JIT) {
225   if (CM) {
226     if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
227         *CM != CodeModel::Large) {
228       if (!TT.isOSFuchsia())
229         report_fatal_error(
230             "Only small, tiny and large code models are allowed on AArch64");
231       else if (*CM != CodeModel::Kernel)
232         report_fatal_error("Only small, tiny, kernel, and large code models "
233                            "are allowed on AArch64");
234     } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
235       report_fatal_error("tiny code model is only supported on ELF");
236     return *CM;
237   }
238   // The default MCJIT memory managers make no guarantees about where they can
239   // find an executable page; JITed code needs to be able to refer to globals
240   // no matter how far away they are.
241   if (JIT)
242     return CodeModel::Large;
243   return CodeModel::Small;
244 }
245 
246 /// Create an AArch64 architecture model.
247 ///
248 AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
249                                            StringRef CPU, StringRef FS,
250                                            const TargetOptions &Options,
251                                            Optional<Reloc::Model> RM,
252                                            Optional<CodeModel::Model> CM,
253                                            CodeGenOpt::Level OL, bool JIT,
254                                            bool LittleEndian)
255     : LLVMTargetMachine(T,
256                         computeDataLayout(TT, Options.MCOptions, LittleEndian),
257                         TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM),
258                         getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
259       TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
260   initAsmInfo();
261 
262   if (TT.isOSBinFormatMachO()) {
263     this->Options.TrapUnreachable = true;
264     this->Options.NoTrapAfterNoreturn = true;
265   }
266 
267   if (getMCAsmInfo()->usesWindowsCFI()) {
268     // Unwinding can get confused if the last instruction in an
269     // exception-handling region (function, funclet, try block, etc.)
270     // is a call.
271     //
272     // FIXME: We could elide the trap if the next instruction would be in
273     // the same region anyway.
274     this->Options.TrapUnreachable = true;
275   }
276 
277   // Enable GlobalISel at or below EnableGlobalISelAt0.
278   if (getOptLevel() <= EnableGlobalISelAtO) {
279     setGlobalISel(true);
280     setGlobalISelAbort(GlobalISelAbortMode::Disable);
281   }
282 
283   // AArch64 supports the MachineOutliner.
284   setMachineOutliner(true);
285 
286   // AArch64 supports default outlining behaviour.
287   setSupportsDefaultOutlining(true);
288 }
289 
290 AArch64TargetMachine::~AArch64TargetMachine() = default;
291 
292 const AArch64Subtarget *
293 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
294   Attribute CPUAttr = F.getFnAttribute("target-cpu");
295   Attribute FSAttr = F.getFnAttribute("target-features");
296 
297   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
298                         ? CPUAttr.getValueAsString().str()
299                         : TargetCPU;
300   std::string FS = !FSAttr.hasAttribute(Attribute::None)
301                        ? FSAttr.getValueAsString().str()
302                        : TargetFS;
303 
304   auto &I = SubtargetMap[CPU + FS];
305   if (!I) {
306     // This needs to be done before we create a new subtarget since any
307     // creation will depend on the TM and the code generation flags on the
308     // function that reside in TargetOptions.
309     resetTargetOptions(F);
310     I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
311                                             isLittle);
312   }
313   return I.get();
314 }
315 
316 void AArch64leTargetMachine::anchor() { }
317 
318 AArch64leTargetMachine::AArch64leTargetMachine(
319     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
320     const TargetOptions &Options, Optional<Reloc::Model> RM,
321     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
322     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
323 
324 void AArch64beTargetMachine::anchor() { }
325 
326 AArch64beTargetMachine::AArch64beTargetMachine(
327     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
328     const TargetOptions &Options, Optional<Reloc::Model> RM,
329     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
330     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
331 
332 namespace {
333 
334 /// AArch64 Code Generator Pass Configuration Options.
335 class AArch64PassConfig : public TargetPassConfig {
336 public:
337   AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
338       : TargetPassConfig(TM, PM) {
339     if (TM.getOptLevel() != CodeGenOpt::None)
340       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
341   }
342 
343   AArch64TargetMachine &getAArch64TargetMachine() const {
344     return getTM<AArch64TargetMachine>();
345   }
346 
347   ScheduleDAGInstrs *
348   createMachineScheduler(MachineSchedContext *C) const override {
349     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
350     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
351     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
352     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
353     if (ST.hasFusion())
354       DAG->addMutation(createAArch64MacroFusionDAGMutation());
355     return DAG;
356   }
357 
358   ScheduleDAGInstrs *
359   createPostMachineScheduler(MachineSchedContext *C) const override {
360     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
361     if (ST.hasFusion()) {
362       // Run the Macro Fusion after RA again since literals are expanded from
363       // pseudos then (v. addPreSched2()).
364       ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
365       DAG->addMutation(createAArch64MacroFusionDAGMutation());
366       return DAG;
367     }
368 
369     return nullptr;
370   }
371 
372   void addIRPasses()  override;
373   bool addPreISel() override;
374   bool addInstSelector() override;
375   bool addIRTranslator() override;
376   void addPreLegalizeMachineIR() override;
377   bool addLegalizeMachineIR() override;
378   bool addRegBankSelect() override;
379   void addPreGlobalInstructionSelect() override;
380   bool addGlobalInstructionSelect() override;
381   bool addILPOpts() override;
382   void addPreRegAlloc() override;
383   void addPostRegAlloc() override;
384   void addPreSched2() override;
385   void addPreEmitPass() override;
386 };
387 
388 } // end anonymous namespace
389 
390 TargetTransformInfo
391 AArch64TargetMachine::getTargetTransformInfo(const Function &F) {
392   return TargetTransformInfo(AArch64TTIImpl(this, F));
393 }
394 
395 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
396   return new AArch64PassConfig(*this, PM);
397 }
398 
399 void AArch64PassConfig::addIRPasses() {
400   // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
401   // ourselves.
402   addPass(createAtomicExpandPass());
403 
404   // Cmpxchg instructions are often used with a subsequent comparison to
405   // determine whether it succeeded. We can exploit existing control-flow in
406   // ldrex/strex loops to simplify this, but it needs tidying up.
407   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
408     addPass(createCFGSimplificationPass(1, true, true, false, true));
409 
410   // Run LoopDataPrefetch
411   //
412   // Run this before LSR to remove the multiplies involved in computing the
413   // pointer values N iterations ahead.
414   if (TM->getOptLevel() != CodeGenOpt::None) {
415     if (EnableLoopDataPrefetch)
416       addPass(createLoopDataPrefetchPass());
417     if (EnableFalkorHWPFFix)
418       addPass(createFalkorMarkStridedAccessesPass());
419   }
420 
421   TargetPassConfig::addIRPasses();
422 
423   // Match interleaved memory accesses to ldN/stN intrinsics.
424   if (TM->getOptLevel() != CodeGenOpt::None) {
425     addPass(createInterleavedLoadCombinePass());
426     addPass(createInterleavedAccessPass());
427   }
428 
429   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
430     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
431     // and lower a GEP with multiple indices to either arithmetic operations or
432     // multiple GEPs with single index.
433     addPass(createSeparateConstOffsetFromGEPPass(true));
434     // Call EarlyCSE pass to find and remove subexpressions in the lowered
435     // result.
436     addPass(createEarlyCSEPass());
437     // Do loop invariant code motion in case part of the lowered result is
438     // invariant.
439     addPass(createLICMPass());
440   }
441 }
442 
443 // Pass Pipeline Configuration
444 bool AArch64PassConfig::addPreISel() {
445   // Run promote constant before global merge, so that the promoted constants
446   // get a chance to be merged
447   if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
448     addPass(createAArch64PromoteConstantPass());
449   // FIXME: On AArch64, this depends on the type.
450   // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
451   // and the offset has to be a multiple of the related size in bytes.
452   if ((TM->getOptLevel() != CodeGenOpt::None &&
453        EnableGlobalMerge == cl::BOU_UNSET) ||
454       EnableGlobalMerge == cl::BOU_TRUE) {
455     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
456                                (EnableGlobalMerge == cl::BOU_UNSET);
457     addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize));
458   }
459 
460   return false;
461 }
462 
463 bool AArch64PassConfig::addInstSelector() {
464   addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
465 
466   // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
467   // references to _TLS_MODULE_BASE_ as possible.
468   if (TM->getTargetTriple().isOSBinFormatELF() &&
469       getOptLevel() != CodeGenOpt::None)
470     addPass(createAArch64CleanupLocalDynamicTLSPass());
471 
472   return false;
473 }
474 
475 bool AArch64PassConfig::addIRTranslator() {
476   addPass(new IRTranslator());
477   return false;
478 }
479 
480 void AArch64PassConfig::addPreLegalizeMachineIR() {
481   addPass(createAArch64PreLegalizeCombiner());
482 }
483 
484 bool AArch64PassConfig::addLegalizeMachineIR() {
485   addPass(new Legalizer());
486   return false;
487 }
488 
489 bool AArch64PassConfig::addRegBankSelect() {
490   addPass(new RegBankSelect());
491   return false;
492 }
493 
494 void AArch64PassConfig::addPreGlobalInstructionSelect() {
495   // Workaround the deficiency of the fast register allocator.
496   if (TM->getOptLevel() == CodeGenOpt::None)
497     addPass(new Localizer());
498 }
499 
500 bool AArch64PassConfig::addGlobalInstructionSelect() {
501   addPass(new InstructionSelect());
502   return false;
503 }
504 
505 bool AArch64PassConfig::addILPOpts() {
506   if (EnableCondOpt)
507     addPass(createAArch64ConditionOptimizerPass());
508   if (EnableCCMP)
509     addPass(createAArch64ConditionalCompares());
510   if (EnableMCR)
511     addPass(&MachineCombinerID);
512   if (EnableCondBrTuning)
513     addPass(createAArch64CondBrTuning());
514   if (EnableEarlyIfConversion)
515     addPass(&EarlyIfConverterID);
516   if (EnableStPairSuppress)
517     addPass(createAArch64StorePairSuppressPass());
518   addPass(createAArch64SIMDInstrOptPass());
519   return true;
520 }
521 
522 void AArch64PassConfig::addPreRegAlloc() {
523   // Change dead register definitions to refer to the zero register.
524   if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
525     addPass(createAArch64DeadRegisterDefinitions());
526 
527   // Use AdvSIMD scalar instructions whenever profitable.
528   if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
529     addPass(createAArch64AdvSIMDScalar());
530     // The AdvSIMD pass may produce copies that can be rewritten to
531     // be register coaleascer friendly.
532     addPass(&PeepholeOptimizerID);
533   }
534 }
535 
536 void AArch64PassConfig::addPostRegAlloc() {
537   // Remove redundant copy instructions.
538   if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
539     addPass(createAArch64RedundantCopyEliminationPass());
540 
541   if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
542     // Improve performance for some FP/SIMD code for A57.
543     addPass(createAArch64A57FPLoadBalancing());
544 }
545 
546 void AArch64PassConfig::addPreSched2() {
547   // Expand some pseudo instructions to allow proper scheduling.
548   addPass(createAArch64ExpandPseudoPass());
549   // Use load/store pair instructions when possible.
550   if (TM->getOptLevel() != CodeGenOpt::None) {
551     if (EnableLoadStoreOpt)
552       addPass(createAArch64LoadStoreOptimizationPass());
553   }
554 
555   // The AArch64SpeculationHardeningPass destroys dominator tree and natural
556   // loop info, which is needed for the FalkorHWPFFixPass and also later on.
557   // Therefore, run the AArch64SpeculationHardeningPass before the
558   // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
559   // info.
560   addPass(createAArch64SpeculationHardeningPass());
561 
562   if (TM->getOptLevel() != CodeGenOpt::None) {
563     if (EnableFalkorHWPFFix)
564       addPass(createFalkorHWPFFixPass());
565   }
566 }
567 
568 void AArch64PassConfig::addPreEmitPass() {
569   // Machine Block Placement might have created new opportunities when run
570   // at O3, where the Tail Duplication Threshold is set to 4 instructions.
571   // Run the load/store optimizer once more.
572   if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt)
573     addPass(createAArch64LoadStoreOptimizationPass());
574 
575   if (EnableA53Fix835769)
576     addPass(createAArch64A53Fix835769());
577   // Relax conditional branch instructions if they're otherwise out of
578   // range of their destination.
579   if (BranchRelaxation)
580     addPass(&BranchRelaxationPassID);
581 
582   if (EnableBranchTargets)
583     addPass(createAArch64BranchTargetsPass());
584 
585   if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
586     addPass(createAArch64CompressJumpTablesPass());
587 
588   if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
589       TM->getTargetTriple().isOSBinFormatMachO())
590     addPass(createAArch64CollectLOHPass());
591 }
592