1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64.h"
14 #include "AArch64TargetMachine.h"
15 #include "AArch64TargetObjectFile.h"
16 #include "AArch64TargetTransformInfo.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/RegAllocRegistry.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/TargetRegistry.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/Transforms/Scalar.h"
25 using namespace llvm;
26 
27 static cl::opt<bool>
28 EnableCCMP("aarch64-ccmp", cl::desc("Enable the CCMP formation pass"),
29            cl::init(true), cl::Hidden);
30 
31 static cl::opt<bool> EnableMCR("aarch64-mcr",
32                                cl::desc("Enable the machine combiner pass"),
33                                cl::init(true), cl::Hidden);
34 
35 static cl::opt<bool>
36 EnableStPairSuppress("aarch64-stp-suppress", cl::desc("Suppress STP for AArch64"),
37                      cl::init(true), cl::Hidden);
38 
39 static cl::opt<bool>
40 EnableAdvSIMDScalar("aarch64-simd-scalar", cl::desc("Enable use of AdvSIMD scalar"
41                     " integer instructions"), cl::init(false), cl::Hidden);
42 
43 static cl::opt<bool>
44 EnablePromoteConstant("aarch64-promote-const", cl::desc("Enable the promote "
45                       "constant pass"), cl::init(true), cl::Hidden);
46 
47 static cl::opt<bool>
48 EnableCollectLOH("aarch64-collect-loh", cl::desc("Enable the pass that emits the"
49                  " linker optimization hints (LOH)"), cl::init(true),
50                  cl::Hidden);
51 
52 static cl::opt<bool>
53 EnableDeadRegisterElimination("aarch64-dead-def-elimination", cl::Hidden,
54                               cl::desc("Enable the pass that removes dead"
55                                        " definitons and replaces stores to"
56                                        " them with stores to the zero"
57                                        " register"),
58                               cl::init(true));
59 
60 static cl::opt<bool>
61 EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"
62                    " optimization pass"), cl::init(true), cl::Hidden);
63 
64 static cl::opt<bool>
65 EnableAtomicTidy("aarch64-atomic-cfg-tidy", cl::Hidden,
66                  cl::desc("Run SimplifyCFG after expanding atomic operations"
67                           " to make use of cmpxchg flow-based information"),
68                  cl::init(true));
69 
70 static cl::opt<bool>
71 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
72                         cl::desc("Run early if-conversion"),
73                         cl::init(true));
74 
75 static cl::opt<bool>
76 EnableCondOpt("aarch64-condopt",
77               cl::desc("Enable the condition optimizer pass"),
78               cl::init(true), cl::Hidden);
79 
80 static cl::opt<bool>
81 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
82                 cl::desc("Work around Cortex-A53 erratum 835769"),
83                 cl::init(false));
84 
85 static cl::opt<bool>
86 EnableGEPOpt("aarch64-gep-opt", cl::Hidden,
87              cl::desc("Enable optimizations on complex GEPs"),
88              cl::init(true));
89 
90 extern "C" void LLVMInitializeAArch64Target() {
91   // Register the target.
92   RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
93   RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
94   RegisterTargetMachine<AArch64leTargetMachine> Z(TheARM64Target);
95 }
96 
97 //===----------------------------------------------------------------------===//
98 // AArch64 Lowering public interface.
99 //===----------------------------------------------------------------------===//
100 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
101   if (TT.isOSBinFormatMachO())
102     return make_unique<AArch64_MachoTargetObjectFile>();
103 
104   return make_unique<AArch64_ELFTargetObjectFile>();
105 }
106 
107 // Helper function to build a DataLayout string
108 static std::string computeDataLayout(StringRef TT, bool LittleEndian) {
109   Triple Triple(TT);
110   if (Triple.isOSBinFormatMachO())
111     return "e-m:o-i64:64-i128:128-n32:64-S128";
112   if (LittleEndian)
113     return "e-m:e-i64:64-i128:128-n32:64-S128";
114   return "E-m:e-i64:64-i128:128-n32:64-S128";
115 }
116 
117 /// TargetMachine ctor - Create an AArch64 architecture model.
118 ///
119 AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
120                                            StringRef CPU, StringRef FS,
121                                            const TargetOptions &Options,
122                                            Reloc::Model RM, CodeModel::Model CM,
123                                            CodeGenOpt::Level OL,
124                                            bool LittleEndian)
125     // This nested ternary is horrible, but DL needs to be properly
126     // initialized before TLInfo is constructed.
127     : LLVMTargetMachine(T, computeDataLayout(TT, LittleEndian), TT, CPU, FS,
128                         Options, RM, CM, OL),
129       TLOF(createTLOF(Triple(getTargetTriple()))),
130       isLittle(LittleEndian) {
131   initAsmInfo();
132 }
133 
134 AArch64TargetMachine::~AArch64TargetMachine() {}
135 
136 const AArch64Subtarget *
137 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
138   Attribute CPUAttr = F.getFnAttribute("target-cpu");
139   Attribute FSAttr = F.getFnAttribute("target-features");
140 
141   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
142                         ? CPUAttr.getValueAsString().str()
143                         : TargetCPU;
144   std::string FS = !FSAttr.hasAttribute(Attribute::None)
145                        ? FSAttr.getValueAsString().str()
146                        : TargetFS;
147 
148   auto &I = SubtargetMap[CPU + FS];
149   if (!I) {
150     // This needs to be done before we create a new subtarget since any
151     // creation will depend on the TM and the code generation flags on the
152     // function that reside in TargetOptions.
153     resetTargetOptions(F);
154     I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this, isLittle);
155   }
156   return I.get();
157 }
158 
159 void AArch64leTargetMachine::anchor() { }
160 
161 AArch64leTargetMachine::
162 AArch64leTargetMachine(const Target &T, StringRef TT,
163                        StringRef CPU, StringRef FS, const TargetOptions &Options,
164                        Reloc::Model RM, CodeModel::Model CM,
165                        CodeGenOpt::Level OL)
166   : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
167 
168 void AArch64beTargetMachine::anchor() { }
169 
170 AArch64beTargetMachine::
171 AArch64beTargetMachine(const Target &T, StringRef TT,
172                        StringRef CPU, StringRef FS, const TargetOptions &Options,
173                        Reloc::Model RM, CodeModel::Model CM,
174                        CodeGenOpt::Level OL)
175   : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
176 
177 namespace {
178 /// AArch64 Code Generator Pass Configuration Options.
179 class AArch64PassConfig : public TargetPassConfig {
180 public:
181   AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
182       : TargetPassConfig(TM, PM) {
183     if (TM->getOptLevel() != CodeGenOpt::None)
184       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
185   }
186 
187   AArch64TargetMachine &getAArch64TargetMachine() const {
188     return getTM<AArch64TargetMachine>();
189   }
190 
191   void addIRPasses()  override;
192   bool addPreISel() override;
193   bool addInstSelector() override;
194   bool addILPOpts() override;
195   void addPreRegAlloc() override;
196   void addPostRegAlloc() override;
197   void addPreSched2() override;
198   void addPreEmitPass() override;
199 };
200 } // namespace
201 
202 TargetIRAnalysis AArch64TargetMachine::getTargetIRAnalysis() {
203   return TargetIRAnalysis([this](Function &F) {
204     return TargetTransformInfo(AArch64TTIImpl(this, F));
205   });
206 }
207 
208 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
209   return new AArch64PassConfig(this, PM);
210 }
211 
212 void AArch64PassConfig::addIRPasses() {
213   // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
214   // ourselves.
215   addPass(createAtomicExpandPass(TM));
216 
217   // Cmpxchg instructions are often used with a subsequent comparison to
218   // determine whether it succeeded. We can exploit existing control-flow in
219   // ldrex/strex loops to simplify this, but it needs tidying up.
220   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
221     addPass(createCFGSimplificationPass());
222 
223   TargetPassConfig::addIRPasses();
224 
225   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
226     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
227     // and lower a GEP with multiple indices to either arithmetic operations or
228     // multiple GEPs with single index.
229     addPass(createSeparateConstOffsetFromGEPPass(TM, true));
230     // Call EarlyCSE pass to find and remove subexpressions in the lowered
231     // result.
232     addPass(createEarlyCSEPass());
233     // Do loop invariant code motion in case part of the lowered result is
234     // invariant.
235     addPass(createLICMPass());
236   }
237 }
238 
239 // Pass Pipeline Configuration
240 bool AArch64PassConfig::addPreISel() {
241   // Run promote constant before global merge, so that the promoted constants
242   // get a chance to be merged
243   if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
244     addPass(createAArch64PromoteConstantPass());
245   // FIXME: On AArch64, this depends on the type.
246   // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
247   // and the offset has to be a multiple of the related size in bytes.
248   if (TM->getOptLevel() != CodeGenOpt::None)
249     addPass(createGlobalMergePass(TM, 4095));
250   if (TM->getOptLevel() != CodeGenOpt::None)
251     addPass(createAArch64AddressTypePromotionPass());
252 
253   return false;
254 }
255 
256 bool AArch64PassConfig::addInstSelector() {
257   addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
258 
259   // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
260   // references to _TLS_MODULE_BASE_ as possible.
261   if (Triple(TM->getTargetTriple()).isOSBinFormatELF() &&
262       getOptLevel() != CodeGenOpt::None)
263     addPass(createAArch64CleanupLocalDynamicTLSPass());
264 
265   return false;
266 }
267 
268 bool AArch64PassConfig::addILPOpts() {
269   if (EnableCondOpt)
270     addPass(createAArch64ConditionOptimizerPass());
271   if (EnableCCMP)
272     addPass(createAArch64ConditionalCompares());
273   if (EnableMCR)
274     addPass(&MachineCombinerID);
275   if (EnableEarlyIfConversion)
276     addPass(&EarlyIfConverterID);
277   if (EnableStPairSuppress)
278     addPass(createAArch64StorePairSuppressPass());
279   return true;
280 }
281 
282 void AArch64PassConfig::addPreRegAlloc() {
283   // Use AdvSIMD scalar instructions whenever profitable.
284   if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
285     addPass(createAArch64AdvSIMDScalar());
286     // The AdvSIMD pass may produce copies that can be rewritten to
287     // be register coaleascer friendly.
288     addPass(&PeepholeOptimizerID);
289   }
290 }
291 
292 void AArch64PassConfig::addPostRegAlloc() {
293   // Change dead register definitions to refer to the zero register.
294   if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
295     addPass(createAArch64DeadRegisterDefinitions());
296   if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
297     // Improve performance for some FP/SIMD code for A57.
298     addPass(createAArch64A57FPLoadBalancing());
299 }
300 
301 void AArch64PassConfig::addPreSched2() {
302   // Expand some pseudo instructions to allow proper scheduling.
303   addPass(createAArch64ExpandPseudoPass());
304   // Use load/store pair instructions when possible.
305   if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
306     addPass(createAArch64LoadStoreOptimizationPass());
307 }
308 
309 void AArch64PassConfig::addPreEmitPass() {
310   if (EnableA53Fix835769)
311     addPass(createAArch64A53Fix835769());
312   // Relax conditional branch instructions if they're otherwise out of
313   // range of their destination.
314   addPass(createAArch64BranchRelaxation());
315   if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
316       Triple(TM->getTargetTriple()).isOSBinFormatMachO())
317     addPass(createAArch64CollectLOHPass());
318 }
319