1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the AArch64 specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AArch64Subtarget.h"
15 #include "AArch64InstrInfo.h"
16 #include "AArch64PBQPRegAlloc.h"
17 #include "llvm/CodeGen/Analysis.h"
18 #include "llvm/CodeGen/MachineScheduler.h"
19 #include "llvm/IR/GlobalValue.h"
20 #include "llvm/Support/TargetRegistry.h"
21 
22 using namespace llvm;
23 
24 #define DEBUG_TYPE "aarch64-subtarget"
25 
26 #define GET_SUBTARGETINFO_CTOR
27 #define GET_SUBTARGETINFO_TARGET_DESC
28 #include "AArch64GenSubtargetInfo.inc"
29 
30 static cl::opt<bool>
31 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
32                      "converter pass"), cl::init(true), cl::Hidden);
33 
34 // If OS supports TBI, use this flag to enable it.
35 static cl::opt<bool>
36 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
37                          "an address is ignored"), cl::init(false), cl::Hidden);
38 
39 AArch64Subtarget &
40 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS) {
41   // Determine default and user-specified characteristics
42 
43   if (CPUString.empty())
44     CPUString = "generic";
45 
46   ParseSubtargetFeatures(CPUString, FS);
47   initializeProperties();
48 
49   return *this;
50 }
51 
52 void AArch64Subtarget::initializeProperties() {
53   // Initialize CPU specific properties. We should add a tablegen feature for
54   // this in the future so we can specify it together with the subtarget
55   // features.
56   switch (ARMProcFamily) {
57   case Cyclone:
58     CacheLineSize = 64;
59     PrefetchDistance = 280;
60     MinPrefetchStride = 2048;
61     MaxPrefetchIterationsAhead = 3;
62     break;
63   case CortexA57:
64     MaxInterleaveFactor = 4;
65     break;
66   case ExynosM1:
67     PrefFunctionAlignment = 4;
68     PrefLoopAlignment = 3;
69     break;
70   case Kryo:
71     MaxInterleaveFactor = 4;
72     VectorInsertExtractBaseCost = 2;
73     CacheLineSize = 128;
74     PrefetchDistance = 740;
75     MinPrefetchStride = 1024;
76     MaxPrefetchIterationsAhead = 11;
77     break;
78   case Vulcan: break;
79   case CortexA35: break;
80   case CortexA53: break;
81   case CortexA72: break;
82   case CortexA73: break;
83   case Others: break;
84   }
85 }
86 
87 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
88                                    const std::string &FS,
89                                    const TargetMachine &TM, bool LittleEndian)
90     : AArch64GenSubtargetInfo(TT, CPU, FS), ReserveX18(TT.isOSDarwin()),
91       IsLittle(LittleEndian), CPUString(CPU), TargetTriple(TT), FrameLowering(),
92       InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(),
93       TLInfo(TM, *this), GISel() {}
94 
95 const CallLowering *AArch64Subtarget::getCallLowering() const {
96   assert(GISel && "Access to GlobalISel APIs not set");
97   return GISel->getCallLowering();
98 }
99 
100 const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
101   assert(GISel && "Access to GlobalISel APIs not set");
102   return GISel->getRegBankInfo();
103 }
104 
105 /// Find the target operand flags that describe how a global value should be
106 /// referenced for the current subtarget.
107 unsigned char
108 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
109                                           const TargetMachine &TM) const {
110   // MachO large model always goes via a GOT, simply to get a single 8-byte
111   // absolute relocation on all global addresses.
112   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
113     return AArch64II::MO_GOT;
114 
115   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
116     return AArch64II::MO_GOT;
117 
118   // The small code mode's direct accesses use ADRP, which cannot necessarily
119   // produce the value 0 (if the code is above 4GB).
120   if (TM.getCodeModel() == CodeModel::Small && GV->hasExternalWeakLinkage())
121     return AArch64II::MO_GOT;
122 
123   return AArch64II::MO_NO_FLAG;
124 }
125 
126 /// This function returns the name of a function which has an interface
127 /// like the non-standard bzero function, if such a function exists on
128 /// the current subtarget and it is considered prefereable over
129 /// memset with zero passed as the second argument. Otherwise it
130 /// returns null.
131 const char *AArch64Subtarget::getBZeroEntry() const {
132   // Prefer bzero on Darwin only.
133   if(isTargetDarwin())
134     return "bzero";
135 
136   return nullptr;
137 }
138 
139 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
140                                          MachineInstr *begin, MachineInstr *end,
141                                          unsigned NumRegionInstrs) const {
142   // LNT run (at least on Cyclone) showed reasonably significant gains for
143   // bi-directional scheduling. 253.perlbmk.
144   Policy.OnlyTopDown = false;
145   Policy.OnlyBottomUp = false;
146   // Enabling or Disabling the latency heuristic is a close call: It seems to
147   // help nearly no benchmark on out-of-order architectures, on the other hand
148   // it regresses register pressure on a few benchmarking.
149   Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
150 }
151 
152 bool AArch64Subtarget::enableEarlyIfConversion() const {
153   return EnableEarlyIfConvert;
154 }
155 
156 bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
157   if (!UseAddressTopByteIgnored)
158     return false;
159 
160   if (TargetTriple.isiOS()) {
161     unsigned Major, Minor, Micro;
162     TargetTriple.getiOSVersion(Major, Minor, Micro);
163     return Major >= 8;
164   }
165 
166   return false;
167 }
168 
169 std::unique_ptr<PBQPRAConstraint>
170 AArch64Subtarget::getCustomPBQPConstraints() const {
171   return balanceFPOps() ? llvm::make_unique<A57ChainingConstraint>() : nullptr;
172 }
173