History log of /llvm-project-15.0.7/llvm/lib/Target/AArch64/AArch64Subtarget.cpp (Results 1 – 25 of 177)
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Revision tags: llvmorg-20.1.0, llvmorg-20.1.0-rc3, llvmorg-20.1.0-rc2, llvmorg-20.1.0-rc1, llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4
# 75f9e83a 03-May-2022 Peter Waller <[email protected]>

[AArch64] Add -aarch64-insert-extract-base-cost

The new flag -aarch64-insert-extract-base-cost can be used to
set the value of AArch64Subtarget::getVectorInsertExtractBaseCost(),
for the purposes of

[AArch64] Add -aarch64-insert-extract-base-cost

The new flag -aarch64-insert-extract-base-cost can be used to
set the value of AArch64Subtarget::getVectorInsertExtractBaseCost(),
for the purposes of experimentation.

Differential Revision: https://reviews.llvm.org/D124835

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# 64816e68 03-May-2022 Philipp Tomsich <[email protected]>

[AArch64] Support for Ampere1 core

Add support for the Ampere Computing Ampere1 core.
Ampere1 implements the AArch64 state and is compatible with ARMv8.6-A.

Differential Revision: https://reviews.l

[AArch64] Support for Ampere1 core

Add support for the Ampere Computing Ampere1 core.
Ampere1 implements the AArch64 state and is compatible with ARMv8.6-A.

Differential Revision: https://reviews.llvm.org/D117112

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Revision tags: llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1
# 7d676714 22-Mar-2022 Nicholas Guy <[email protected]>

[AArch64] Set MaxBytesForLoopAlignment for more targets

Differential Revision: https://reviews.llvm.org/D122566


# 989f1c72 15-Mar-2022 serge-sans-paille <[email protected]>

Cleanup codegen includes

This is a (fixed) recommit of https://reviews.llvm.org/D121169

after: 1061034926
before: 1063332844

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-in

Cleanup codegen includes

This is a (fixed) recommit of https://reviews.llvm.org/D121169

after: 1061034926
before: 1063332844

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D121681

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Revision tags: llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3
# a278250b 10-Mar-2022 Nico Weber <[email protected]>

Revert "Cleanup codegen includes"

This reverts commit 7f230feeeac8a67b335f52bd2e900a05c6098f20.
Breaks CodeGenCUDA/link-device-bitcode.cu in check-clang,
and many LLVM tests, see comments on https:/

Revert "Cleanup codegen includes"

This reverts commit 7f230feeeac8a67b335f52bd2e900a05c6098f20.
Breaks CodeGenCUDA/link-device-bitcode.cu in check-clang,
and many LLVM tests, see comments on https://reviews.llvm.org/D121169

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# 7f230fee 07-Mar-2022 serge-sans-paille <[email protected]>

Cleanup codegen includes

after: 1061034926
before: 1063332844

Differential Revision: https://reviews.llvm.org/D121169


Revision tags: llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1, llvmorg-15-init
# 3a1cb362 24-Jan-2022 Egor Zhdan <[email protected]>

Add DriverKit support

This patch is the first in a series of patches to upstream the support for Apple's DriverKit. Once complete, it will allow targeting DriverKit platform with Clang similarly to

Add DriverKit support

This patch is the first in a series of patches to upstream the support for Apple's DriverKit. Once complete, it will allow targeting DriverKit platform with Clang similarly to AppleClang.

This code was originally authored by JF Bastien.

Differential Revision: https://reviews.llvm.org/D118046

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# 6b1e844b 31-Jan-2022 Ties Stuij <[email protected]>

[ARM] Add Cortex-X1C Support for Clang and LLVM

This patch upstreams support for the Arm-v8 Cortex-X1C processor for AArch64 and
ARM.

For more information, see:
- https://community.arm.com/arm-comm

[ARM] Add Cortex-X1C Support for Clang and LLVM

This patch upstreams support for the Arm-v8 Cortex-X1C processor for AArch64 and
ARM.

For more information, see:
- https://community.arm.com/arm-community-blogs/b/announcements/posts/arm-cortex-x1c
- https://developer.arm.com/documentation/101968/0002/Functional-description/Technical-overview/Components

The following people contributed to this patch:
- Simon Tatham
- Ties Stuij

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D117202

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# 13252160 21-Jan-2022 David Sherwood <[email protected]>

[NFC] Move useSVEForFixedLengthVectors into AArch64Subtarget.h

Given how small the function is and how often it gets used it
makes more sense to live in the header file.

Differential Revision: http

[NFC] Move useSVEForFixedLengthVectors into AArch64Subtarget.h

Given how small the function is and how often it gets used it
makes more sense to live in the header file.

Differential Revision: https://reviews.llvm.org/D117883

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Revision tags: llvmorg-13.0.1, llvmorg-13.0.1-rc3
# 75e164f6 20-Jan-2022 serge-sans-paille <[email protected]>

[llvm] Cleanup header dependencies in ADT and Support

The cleanup was manual, but assisted by "include-what-you-use". It consists in

1. Removing unused forward declaration. No impact expected.
2. R

[llvm] Cleanup header dependencies in ADT and Support

The cleanup was manual, but assisted by "include-what-you-use". It consists in

1. Removing unused forward declaration. No impact expected.
2. Removing unused headers in .cpp files. No impact expected.
3. Removing unused headers in .h files. This removes implicit dependencies and
is generally considered a good thing, but this may break downstream builds.
I've updated llvm, clang, lld, lldb and mlir deps, and included a list of the
modification in the second part of the commit.
4. Replacing header inclusion by forward declaration. This has the same impact
as 3.

Notable changes:

- llvm/Support/TargetParser.h no longer includes llvm/Support/AArch64TargetParser.h nor llvm/Support/ARMTargetParser.h
- llvm/Support/TypeSize.h no longer includes llvm/Support/WithColor.h
- llvm/Support/YAMLTraits.h no longer includes llvm/Support/Regex.h
- llvm/ADT/SmallVector.h no longer includes llvm/Support/MemAlloc.h nor llvm/Support/ErrorHandling.h

You may need to add some of these headers in your compilation units, if needs be.

As an hint to the impact of the cleanup, running

clang++ -E -Iinclude -I../llvm/include ../llvm/lib/Support/*.cpp -std=c++14 -fno-rtti -fno-exceptions | wc -l

before: 8000919 lines
after: 7917500 lines

Reduced dependencies also helps incremental rebuilds and is more ccache
friendly, something not shown by the above metric :-)

Discourse thread on the topic: https://llvm.discourse.group/t/include-what-you-use-include-cleanup/5831

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Revision tags: llvmorg-13.0.1-rc2
# f3a344d2 07-Jan-2022 Kazu Hirata <[email protected]>

[Target] Remove redundant member initialization (NFC)

Identified with readability-redundant-member-init.


# 13992498 07-Dec-2021 Nicholas Guy <[email protected]>

[AArch64][CodeGen] Emit alignment "Max Skip" operand for AArch64 loops

Differential Revision: https://reviews.llvm.org/D114879


# e5947760 03-Jan-2022 Kazu Hirata <[email protected]>

Revert "[llvm] Remove redundant member initialization (NFC)"

This reverts commit fd4808887ee47f3ec8a030e9211169ef4fb094c3.

This patch causes gcc to issue a lot of warnings like:

warning: base cl

Revert "[llvm] Remove redundant member initialization (NFC)"

This reverts commit fd4808887ee47f3ec8a030e9211169ef4fb094c3.

This patch causes gcc to issue a lot of warnings like:

warning: base class ‘class llvm::MCParsedAsmOperand’ should be
explicitly initialized in the copy constructor [-Wextra]

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# fd480888 02-Jan-2022 Kazu Hirata <[email protected]>

[llvm] Remove redundant member initialization (NFC)

Identified with readability-redundant-member-init.


# 219672b8 06-Dec-2021 James Farrell <[email protected]>

Revert "Revert "Use VersionTuple for parsing versions in Triple, fixing issues that caused the original change to be reverted. This makes it possible to distinguish between "16" and "16.0" after pars

Revert "Revert "Use VersionTuple for parsing versions in Triple, fixing issues that caused the original change to be reverted. This makes it possible to distinguish between "16" and "16.0" after parsing, which previously was not possible.""

This reverts commit 63a6348cad6caccf285c1661bc60d8ba5a40c972.

Differential Revision: https://reviews.llvm.org/D115254

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# 63a6348c 06-Dec-2021 James Farrell <[email protected]>

Revert "Use VersionTuple for parsing versions in Triple, fixing issues that caused the original change to be reverted. This makes it possible to distinguish between "16" and "16.0" after parsing, whi

Revert "Use VersionTuple for parsing versions in Triple, fixing issues that caused the original change to be reverted. This makes it possible to distinguish between "16" and "16.0" after parsing, which previously was not possible."

This reverts commit 50324670342d9391f62671685f4d6b4880a4ea9a.

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# 50324670 01-Dec-2021 James Farrell <[email protected]>

Use VersionTuple for parsing versions in Triple, fixing issues that caused the original change to be reverted. This makes it possible to distinguish between "16" and "16.0" after parsing, which previ

Use VersionTuple for parsing versions in Triple, fixing issues that caused the original change to be reverted. This makes it possible to distinguish between "16" and "16.0" after parsing, which previously was not possible.

This reverts commit 40d5eeac6cd89a2360c3ba997cbaa816abca828c.

Differential Revision: https://reviews.llvm.org/D114885

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# 40d5eeac 30-Nov-2021 Nikita Popov <[email protected]>

Revert "Use VersionTuple for parsing versions in Triple. This makes it possible to distinguish between "16" and "16.0" after parsing, which previously was not possible."

This reverts commit 1e828646

Revert "Use VersionTuple for parsing versions in Triple. This makes it possible to distinguish between "16" and "16.0" after parsing, which previously was not possible."

This reverts commit 1e8286467036d8ef1a972de723f805a4981b2692.

llvm/test/Transforms/LoopStrengthReduce/X86/2009-11-10-LSRCrash.ll fails
with assertion failure:

llc: /home/nikic/llvm-project/llvm/include/llvm/ADT/Optional.h:196: T& llvm::optional_detail::OptionalStorage<T, true>::getValue() & [with T = unsigned int]: Assertion `hasVal' failed.
...
#8 0x00005633843af5cb llvm::MCStreamer::emitVersionForTarget(llvm::Triple const&, llvm::VersionTuple const&)
#9 0x0000563383b47f14 llvm::AsmPrinter::doInitialization(llvm::Module&)

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Revision tags: llvmorg-13.0.1-rc1
# 1e828646 16-Nov-2021 James Farrell <[email protected]>

Use VersionTuple for parsing versions in Triple. This makes it possible to distinguish between "16" and "16.0" after parsing, which previously was not possible.

See also https://github.com/android/n

Use VersionTuple for parsing versions in Triple. This makes it possible to distinguish between "16" and "16.0" after parsing, which previously was not possible.

See also https://github.com/android/ndk/issues/1455.

Differential Revision: https://reviews.llvm.org/D114163

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# 8e47b83e 14-Oct-2021 Mubashar Ahmad <[email protected]>

[AArch64][ARM] Enablement of Cortex-A710 Support

Phabricator review: https://reviews.llvm.org/D113256


# 0b83a18a 01-Nov-2021 Mubashar Ahmad <[email protected]>

[AArch64] Enablement of Cortex-X2

Enables support for Cortex-X2 cores.

Differential Revision: https://reviews.llvm.org/D112459


# 2186b011 22-Oct-2021 Caroline Concatto <[email protected]>

[Driver][AArch64]Add driver support for neoverse-512tvb target

The support for neoverse-512tvb mirrors the same option available in GCC[1].
There is no functional effect for this option yet.
This p

[Driver][AArch64]Add driver support for neoverse-512tvb target

The support for neoverse-512tvb mirrors the same option available in GCC[1].
There is no functional effect for this option yet.
This patch ensures the driver accepts "-mcpu=neoverse-512tvb", and enough
plumbing is in place to allow the new option to be used in the future.

[1]https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html

Differential Revision: https://reviews.llvm.org/D112406

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Revision tags: llvmorg-13.0.0, llvmorg-13.0.0-rc4
# 9448cdc9 22-Sep-2021 David Sherwood <[email protected]>

[SVE][Analysis] Tune the cost model according to the tune-cpu attribute

This patch introduces a new function:

AArch64Subtarget::getVScaleForTuning

that returns a value for vscale that can be use

[SVE][Analysis] Tune the cost model according to the tune-cpu attribute

This patch introduces a new function:

AArch64Subtarget::getVScaleForTuning

that returns a value for vscale that can be used for tuning the cost
model when using scalable vectors. The VScaleForTuning option in
AArch64Subtarget is initialised according to the following rules:

1. If the user has specified the CPU to tune for we use that, else
2. If the target CPU was specified we use that, else
3. The tuning is set to "generic".

For CPUs of type "generic" I have assumed that vscale=2.

New tests added here:

Analysis/CostModel/AArch64/sve-gather.ll
Analysis/CostModel/AArch64/sve-scatter.ll
Transforms/LoopVectorize/AArch64/sve-strict-fadd-cost.ll

Differential Revision: https://reviews.llvm.org/D110259

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# 607fb1bb 22-Sep-2021 David Sherwood <[email protected]>

[AArch64] Always add -tune-cpu argument to -cc1 driver

This patch ensures that we always tune for a given CPU on AArch64
targets when the user specifies the "-mtune=xyz" flag. In the
AArch64Subtarge

[AArch64] Always add -tune-cpu argument to -cc1 driver

This patch ensures that we always tune for a given CPU on AArch64
targets when the user specifies the "-mtune=xyz" flag. In the
AArch64Subtarget if the tune flag is unset we use the CPU value
instead.

I've updated the release notes here:

llvm/docs/ReleaseNotes.rst

and added tests here:

clang/test/Driver/aarch64-mtune.c

Differential Revision: https://reviews.llvm.org/D110258

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# 97809c82 15-Oct-2021 Mubashar Ahmad <[email protected]>

[AArch64]Enabling Cortex-A510 Support

This patch enables support for Cortex-A510 CPUs.

Reviewed By: MarkMurrayARM, dmgreen

Differential Revision: https://reviews.llvm.org/D109825


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