1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the AArch64 specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64Subtarget.h"
14 
15 #include "AArch64.h"
16 #include "AArch64CallLowering.h"
17 #include "AArch64InstrInfo.h"
18 #include "AArch64LegalizerInfo.h"
19 #include "AArch64PBQPRegAlloc.h"
20 #include "AArch64RegisterBankInfo.h"
21 #include "AArch64TargetMachine.h"
22 #include "MCTargetDesc/AArch64AddressingModes.h"
23 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
24 #include "llvm/CodeGen/MachineScheduler.h"
25 #include "llvm/IR/GlobalValue.h"
26 #include "llvm/Support/TargetParser.h"
27 
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "aarch64-subtarget"
31 
32 #define GET_SUBTARGETINFO_CTOR
33 #define GET_SUBTARGETINFO_TARGET_DESC
34 #include "AArch64GenSubtargetInfo.inc"
35 
36 static cl::opt<bool>
37 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
38                      "converter pass"), cl::init(true), cl::Hidden);
39 
40 // If OS supports TBI, use this flag to enable it.
41 static cl::opt<bool>
42 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
43                          "an address is ignored"), cl::init(false), cl::Hidden);
44 
45 static cl::opt<bool>
46     UseNonLazyBind("aarch64-enable-nonlazybind",
47                    cl::desc("Call nonlazybind functions via direct GOT load"),
48                    cl::init(false), cl::Hidden);
49 
50 AArch64Subtarget &
51 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS,
52                                                   StringRef CPUString) {
53   // Determine default and user-specified characteristics
54 
55   if (CPUString.empty())
56     CPUString = "generic";
57 
58   ParseSubtargetFeatures(CPUString, FS);
59   initializeProperties();
60 
61   return *this;
62 }
63 
64 void AArch64Subtarget::initializeProperties() {
65   // Initialize CPU specific properties. We should add a tablegen feature for
66   // this in the future so we can specify it together with the subtarget
67   // features.
68   switch (ARMProcFamily) {
69   case Others:
70     break;
71   case CortexA35:
72     break;
73   case CortexA53:
74     PrefFunctionAlignment = 3;
75     break;
76   case CortexA55:
77     break;
78   case CortexA57:
79     MaxInterleaveFactor = 4;
80     PrefFunctionAlignment = 4;
81     break;
82   case CortexA65:
83     break;
84   case CortexA72:
85   case CortexA73:
86   case CortexA75:
87   case CortexA76:
88     PrefFunctionAlignment = 4;
89     break;
90   case Cyclone:
91     CacheLineSize = 64;
92     PrefetchDistance = 280;
93     MinPrefetchStride = 2048;
94     MaxPrefetchIterationsAhead = 3;
95     break;
96   case ExynosM1:
97     MaxInterleaveFactor = 4;
98     MaxJumpTableSize = 8;
99     PrefFunctionAlignment = 4;
100     PrefLoopAlignment = 3;
101     break;
102   case ExynosM3:
103     MaxInterleaveFactor = 4;
104     MaxJumpTableSize = 20;
105     PrefFunctionAlignment = 5;
106     PrefLoopAlignment = 4;
107     break;
108   case Falkor:
109     MaxInterleaveFactor = 4;
110     // FIXME: remove this to enable 64-bit SLP if performance looks good.
111     MinVectorRegisterBitWidth = 128;
112     CacheLineSize = 128;
113     PrefetchDistance = 820;
114     MinPrefetchStride = 2048;
115     MaxPrefetchIterationsAhead = 8;
116     break;
117   case Kryo:
118     MaxInterleaveFactor = 4;
119     VectorInsertExtractBaseCost = 2;
120     CacheLineSize = 128;
121     PrefetchDistance = 740;
122     MinPrefetchStride = 1024;
123     MaxPrefetchIterationsAhead = 11;
124     // FIXME: remove this to enable 64-bit SLP if performance looks good.
125     MinVectorRegisterBitWidth = 128;
126     break;
127   case NeoverseE1:
128   case NeoverseN1:
129     break;
130   case Saphira:
131     MaxInterleaveFactor = 4;
132     // FIXME: remove this to enable 64-bit SLP if performance looks good.
133     MinVectorRegisterBitWidth = 128;
134     break;
135   case ThunderX2T99:
136     CacheLineSize = 64;
137     PrefFunctionAlignment = 3;
138     PrefLoopAlignment = 2;
139     MaxInterleaveFactor = 4;
140     PrefetchDistance = 128;
141     MinPrefetchStride = 1024;
142     MaxPrefetchIterationsAhead = 4;
143     // FIXME: remove this to enable 64-bit SLP if performance looks good.
144     MinVectorRegisterBitWidth = 128;
145     break;
146   case ThunderX:
147   case ThunderXT88:
148   case ThunderXT81:
149   case ThunderXT83:
150     CacheLineSize = 128;
151     PrefFunctionAlignment = 3;
152     PrefLoopAlignment = 2;
153     // FIXME: remove this to enable 64-bit SLP if performance looks good.
154     MinVectorRegisterBitWidth = 128;
155     break;
156   case TSV110:
157     CacheLineSize = 64;
158     PrefFunctionAlignment = 4;
159     PrefLoopAlignment = 2;
160     break;
161   }
162 }
163 
164 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
165                                    const std::string &FS,
166                                    const TargetMachine &TM, bool LittleEndian)
167     : AArch64GenSubtargetInfo(TT, CPU, FS),
168       ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
169       CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
170       IsLittle(LittleEndian),
171       TargetTriple(TT), FrameLowering(),
172       InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(),
173       TLInfo(TM, *this) {
174   if (AArch64::isX18ReservedByDefault(TT))
175     ReserveXRegister.set(18);
176 
177   CallLoweringInfo.reset(new AArch64CallLowering(*getTargetLowering()));
178   Legalizer.reset(new AArch64LegalizerInfo(*this));
179 
180   auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
181 
182   // FIXME: At this point, we can't rely on Subtarget having RBI.
183   // It's awkward to mix passing RBI and the Subtarget; should we pass
184   // TII/TRI as well?
185   InstSelector.reset(createAArch64InstructionSelector(
186       *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
187 
188   RegBankInfo.reset(RBI);
189 }
190 
191 const CallLowering *AArch64Subtarget::getCallLowering() const {
192   return CallLoweringInfo.get();
193 }
194 
195 const InstructionSelector *AArch64Subtarget::getInstructionSelector() const {
196   return InstSelector.get();
197 }
198 
199 const LegalizerInfo *AArch64Subtarget::getLegalizerInfo() const {
200   return Legalizer.get();
201 }
202 
203 const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
204   return RegBankInfo.get();
205 }
206 
207 /// Find the target operand flags that describe how a global value should be
208 /// referenced for the current subtarget.
209 unsigned
210 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
211                                           const TargetMachine &TM) const {
212   // MachO large model always goes via a GOT, simply to get a single 8-byte
213   // absolute relocation on all global addresses.
214   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
215     return AArch64II::MO_GOT;
216 
217   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) {
218     if (GV->hasDLLImportStorageClass())
219       return AArch64II::MO_GOT | AArch64II::MO_DLLIMPORT;
220     if (getTargetTriple().isOSWindows())
221       return AArch64II::MO_GOT | AArch64II::MO_COFFSTUB;
222     return AArch64II::MO_GOT;
223   }
224 
225   // The small code model's direct accesses use ADRP, which cannot
226   // necessarily produce the value 0 (if the code is above 4GB).
227   // Same for the tiny code model, where we have a pc relative LDR.
228   if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&
229       GV->hasExternalWeakLinkage())
230     return AArch64II::MO_GOT;
231 
232   // References to tagged globals are marked with MO_NC | MO_TAGGED to indicate
233   // that their nominal addresses are tagged and outside of the code model. In
234   // AArch64ExpandPseudo::expandMI we emit an additional instruction to set the
235   // tag if necessary based on MO_TAGGED.
236   if (AllowTaggedGlobals && !isa<FunctionType>(GV->getValueType()))
237     return AArch64II::MO_NC | AArch64II::MO_TAGGED;
238 
239   return AArch64II::MO_NO_FLAG;
240 }
241 
242 unsigned AArch64Subtarget::classifyGlobalFunctionReference(
243     const GlobalValue *GV, const TargetMachine &TM) const {
244   // MachO large model always goes via a GOT, because we don't have the
245   // relocations available to do anything else..
246   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
247       !GV->hasInternalLinkage())
248     return AArch64II::MO_GOT;
249 
250   // NonLazyBind goes via GOT unless we know it's available locally.
251   auto *F = dyn_cast<Function>(GV);
252   if (UseNonLazyBind && F && F->hasFnAttribute(Attribute::NonLazyBind) &&
253       !TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
254     return AArch64II::MO_GOT;
255 
256   return AArch64II::MO_NO_FLAG;
257 }
258 
259 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
260                                            unsigned NumRegionInstrs) const {
261   // LNT run (at least on Cyclone) showed reasonably significant gains for
262   // bi-directional scheduling. 253.perlbmk.
263   Policy.OnlyTopDown = false;
264   Policy.OnlyBottomUp = false;
265   // Enabling or Disabling the latency heuristic is a close call: It seems to
266   // help nearly no benchmark on out-of-order architectures, on the other hand
267   // it regresses register pressure on a few benchmarking.
268   Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
269 }
270 
271 bool AArch64Subtarget::enableEarlyIfConversion() const {
272   return EnableEarlyIfConvert;
273 }
274 
275 bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
276   if (!UseAddressTopByteIgnored)
277     return false;
278 
279   if (TargetTriple.isiOS()) {
280     unsigned Major, Minor, Micro;
281     TargetTriple.getiOSVersion(Major, Minor, Micro);
282     return Major >= 8;
283   }
284 
285   return false;
286 }
287 
288 std::unique_ptr<PBQPRAConstraint>
289 AArch64Subtarget::getCustomPBQPConstraints() const {
290   return balanceFPOps() ? llvm::make_unique<A57ChainingConstraint>() : nullptr;
291 }
292 
293 void AArch64Subtarget::mirFileLoaded(MachineFunction &MF) const {
294   // We usually compute max call frame size after ISel. Do the computation now
295   // if the .mir file didn't specify it. Note that this will probably give you
296   // bogus values after PEI has eliminated the callframe setup/destroy pseudo
297   // instructions, specify explicitly if you need it to be correct.
298   MachineFrameInfo &MFI = MF.getFrameInfo();
299   if (!MFI.isMaxCallFrameSizeComputed())
300     MFI.computeMaxCallFrameSize(MF);
301 }
302