1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the AArch64 specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AArch64Subtarget.h"
15 #include "AArch64InstrInfo.h"
16 #include "AArch64PBQPRegAlloc.h"
17 #include "llvm/CodeGen/Analysis.h"
18 #include "llvm/CodeGen/MachineScheduler.h"
19 #include "llvm/IR/GlobalValue.h"
20 #include "llvm/Support/TargetRegistry.h"
21 
22 using namespace llvm;
23 
24 #define DEBUG_TYPE "aarch64-subtarget"
25 
26 #define GET_SUBTARGETINFO_CTOR
27 #define GET_SUBTARGETINFO_TARGET_DESC
28 #include "AArch64GenSubtargetInfo.inc"
29 
30 static cl::opt<bool>
31 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
32                      "converter pass"), cl::init(true), cl::Hidden);
33 
34 // If OS supports TBI, use this flag to enable it.
35 static cl::opt<bool>
36 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
37                          "an address is ignored"), cl::init(false), cl::Hidden);
38 
39 AArch64Subtarget &
40 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS) {
41   // Determine default and user-specified characteristics
42 
43   if (CPUString.empty())
44     CPUString = "generic";
45 
46   ParseSubtargetFeatures(CPUString, FS);
47   return *this;
48 }
49 
50 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
51                                    const std::string &FS,
52                                    const TargetMachine &TM, bool LittleEndian)
53     : AArch64GenSubtargetInfo(TT, CPU, FS), ReserveX18(TT.isOSDarwin()),
54       IsLittle(LittleEndian), CPUString(CPU), TargetTriple(TT), FrameLowering(),
55       InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(),
56       TLInfo(TM, *this), GISel() {}
57 
58 const CallLowering *AArch64Subtarget::getCallLowering() const {
59   assert(GISel && "Access to GlobalISel APIs not set");
60   return GISel->getCallLowering();
61 }
62 
63 const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
64   assert(GISel && "Access to GlobalISel APIs not set");
65   return GISel->getRegBankInfo();
66 }
67 
68 /// Find the target operand flags that describe how a global value should be
69 /// referenced for the current subtarget.
70 unsigned char
71 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
72                                           const TargetMachine &TM) const {
73   // MachO large model always goes via a GOT, simply to get a single 8-byte
74   // absolute relocation on all global addresses.
75   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
76     return AArch64II::MO_GOT;
77 
78   Reloc::Model RM = TM.getRelocationModel();
79   if (!shouldAssumeDSOLocal(RM, TargetTriple, *GV->getParent(), GV))
80     return AArch64II::MO_GOT;
81 
82   // The small code mode's direct accesses use ADRP, which cannot necessarily
83   // produce the value 0 (if the code is above 4GB).
84   if (TM.getCodeModel() == CodeModel::Small && GV->hasExternalWeakLinkage())
85     return AArch64II::MO_GOT;
86 
87   return AArch64II::MO_NO_FLAG;
88 }
89 
90 /// This function returns the name of a function which has an interface
91 /// like the non-standard bzero function, if such a function exists on
92 /// the current subtarget and it is considered prefereable over
93 /// memset with zero passed as the second argument. Otherwise it
94 /// returns null.
95 const char *AArch64Subtarget::getBZeroEntry() const {
96   // Prefer bzero on Darwin only.
97   if(isTargetDarwin())
98     return "bzero";
99 
100   return nullptr;
101 }
102 
103 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
104                                          MachineInstr *begin, MachineInstr *end,
105                                          unsigned NumRegionInstrs) const {
106   // LNT run (at least on Cyclone) showed reasonably significant gains for
107   // bi-directional scheduling. 253.perlbmk.
108   Policy.OnlyTopDown = false;
109   Policy.OnlyBottomUp = false;
110   // Enabling or Disabling the latency heuristic is a close call: It seems to
111   // help nearly no benchmark on out-of-order architectures, on the other hand
112   // it regresses register pressure on a few benchmarking.
113   if (isCyclone())
114     Policy.DisableLatencyHeuristic = true;
115 }
116 
117 bool AArch64Subtarget::enableEarlyIfConversion() const {
118   return EnableEarlyIfConvert;
119 }
120 
121 bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
122   if (!UseAddressTopByteIgnored)
123     return false;
124 
125   if (TargetTriple.isiOS()) {
126     unsigned Major, Minor, Micro;
127     TargetTriple.getiOSVersion(Major, Minor, Micro);
128     return Major >= 8;
129   }
130 
131   return false;
132 }
133 
134 std::unique_ptr<PBQPRAConstraint>
135 AArch64Subtarget::getCustomPBQPConstraints() const {
136   if (!isCortexA57())
137     return nullptr;
138 
139   return llvm::make_unique<A57ChainingConstraint>();
140 }
141