1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the AArch64 specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64Subtarget.h"
14 
15 #include "AArch64.h"
16 #include "AArch64InstrInfo.h"
17 #include "AArch64PBQPRegAlloc.h"
18 #include "AArch64TargetMachine.h"
19 #include "GISel/AArch64CallLowering.h"
20 #include "GISel/AArch64LegalizerInfo.h"
21 #include "GISel/AArch64RegisterBankInfo.h"
22 #include "MCTargetDesc/AArch64AddressingModes.h"
23 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
24 #include "llvm/CodeGen/MachineScheduler.h"
25 #include "llvm/IR/GlobalValue.h"
26 #include "llvm/Support/AArch64TargetParser.h"
27 #include "llvm/Support/TargetParser.h"
28 
29 using namespace llvm;
30 
31 #define DEBUG_TYPE "aarch64-subtarget"
32 
33 #define GET_SUBTARGETINFO_CTOR
34 #define GET_SUBTARGETINFO_TARGET_DESC
35 #include "AArch64GenSubtargetInfo.inc"
36 
37 static cl::opt<bool>
38 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
39                      "converter pass"), cl::init(true), cl::Hidden);
40 
41 // If OS supports TBI, use this flag to enable it.
42 static cl::opt<bool>
43 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
44                          "an address is ignored"), cl::init(false), cl::Hidden);
45 
46 static cl::opt<bool>
47     UseNonLazyBind("aarch64-enable-nonlazybind",
48                    cl::desc("Call nonlazybind functions via direct GOT load"),
49                    cl::init(false), cl::Hidden);
50 
51 static cl::opt<bool> UseAA("aarch64-use-aa", cl::init(true),
52                            cl::desc("Enable the use of AA during codegen."));
53 
54 AArch64Subtarget &AArch64Subtarget::initializeSubtargetDependencies(
55     StringRef FS, StringRef CPUString, StringRef TuneCPUString) {
56   // Determine default and user-specified characteristics
57 
58   if (CPUString.empty())
59     CPUString = "generic";
60 
61   if (TuneCPUString.empty())
62     TuneCPUString = CPUString;
63 
64   ParseSubtargetFeatures(CPUString, TuneCPUString, FS);
65   initializeProperties();
66 
67   return *this;
68 }
69 
70 void AArch64Subtarget::initializeProperties() {
71   // Initialize CPU specific properties. We should add a tablegen feature for
72   // this in the future so we can specify it together with the subtarget
73   // features.
74   switch (ARMProcFamily) {
75   case Others:
76     break;
77   case Carmel:
78     CacheLineSize = 64;
79     break;
80   case CortexA35:
81     break;
82   case CortexA53:
83   case CortexA55:
84     PrefFunctionLogAlignment = 4;
85     break;
86   case CortexA57:
87     MaxInterleaveFactor = 4;
88     PrefFunctionLogAlignment = 4;
89     break;
90   case CortexA65:
91     PrefFunctionLogAlignment = 3;
92     break;
93   case CortexA72:
94   case CortexA73:
95   case CortexA75:
96   case CortexA76:
97   case CortexA77:
98   case CortexA78:
99   case CortexA78C:
100   case CortexR82:
101   case CortexX1:
102     PrefFunctionLogAlignment = 4;
103     break;
104   case CortexA510:
105   case CortexA710:
106   case CortexX2:
107     PrefFunctionLogAlignment = 4;
108     VScaleForTuning = 1;
109     break;
110   case A64FX:
111     CacheLineSize = 256;
112     PrefFunctionLogAlignment = 3;
113     PrefLoopLogAlignment = 2;
114     MaxInterleaveFactor = 4;
115     PrefetchDistance = 128;
116     MinPrefetchStride = 1024;
117     MaxPrefetchIterationsAhead = 4;
118     VScaleForTuning = 4;
119     break;
120   case AppleA7:
121   case AppleA10:
122   case AppleA11:
123   case AppleA12:
124   case AppleA13:
125   case AppleA14:
126     CacheLineSize = 64;
127     PrefetchDistance = 280;
128     MinPrefetchStride = 2048;
129     MaxPrefetchIterationsAhead = 3;
130     break;
131   case ExynosM3:
132     MaxInterleaveFactor = 4;
133     MaxJumpTableSize = 20;
134     PrefFunctionLogAlignment = 5;
135     PrefLoopLogAlignment = 4;
136     break;
137   case Falkor:
138     MaxInterleaveFactor = 4;
139     // FIXME: remove this to enable 64-bit SLP if performance looks good.
140     MinVectorRegisterBitWidth = 128;
141     CacheLineSize = 128;
142     PrefetchDistance = 820;
143     MinPrefetchStride = 2048;
144     MaxPrefetchIterationsAhead = 8;
145     break;
146   case Kryo:
147     MaxInterleaveFactor = 4;
148     VectorInsertExtractBaseCost = 2;
149     CacheLineSize = 128;
150     PrefetchDistance = 740;
151     MinPrefetchStride = 1024;
152     MaxPrefetchIterationsAhead = 11;
153     // FIXME: remove this to enable 64-bit SLP if performance looks good.
154     MinVectorRegisterBitWidth = 128;
155     break;
156   case NeoverseE1:
157     PrefFunctionLogAlignment = 3;
158     break;
159   case NeoverseN1:
160     PrefFunctionLogAlignment = 4;
161     PrefLoopLogAlignment = 5;
162     MaxBytesForLoopAlignment = 16;
163     break;
164   case NeoverseN2:
165     PrefFunctionLogAlignment = 4;
166     PrefLoopLogAlignment = 5;
167     MaxBytesForLoopAlignment = 16;
168     VScaleForTuning = 1;
169     break;
170   case NeoverseV1:
171     PrefFunctionLogAlignment = 4;
172     PrefLoopLogAlignment = 5;
173     MaxBytesForLoopAlignment = 16;
174     VScaleForTuning = 2;
175     break;
176   case Neoverse512TVB:
177     PrefFunctionLogAlignment = 4;
178     VScaleForTuning = 1;
179     MaxInterleaveFactor = 4;
180     break;
181   case Saphira:
182     MaxInterleaveFactor = 4;
183     // FIXME: remove this to enable 64-bit SLP if performance looks good.
184     MinVectorRegisterBitWidth = 128;
185     break;
186   case ThunderX2T99:
187     CacheLineSize = 64;
188     PrefFunctionLogAlignment = 3;
189     PrefLoopLogAlignment = 2;
190     MaxInterleaveFactor = 4;
191     PrefetchDistance = 128;
192     MinPrefetchStride = 1024;
193     MaxPrefetchIterationsAhead = 4;
194     // FIXME: remove this to enable 64-bit SLP if performance looks good.
195     MinVectorRegisterBitWidth = 128;
196     break;
197   case ThunderX:
198   case ThunderXT88:
199   case ThunderXT81:
200   case ThunderXT83:
201     CacheLineSize = 128;
202     PrefFunctionLogAlignment = 3;
203     PrefLoopLogAlignment = 2;
204     // FIXME: remove this to enable 64-bit SLP if performance looks good.
205     MinVectorRegisterBitWidth = 128;
206     break;
207   case TSV110:
208     CacheLineSize = 64;
209     PrefFunctionLogAlignment = 4;
210     PrefLoopLogAlignment = 2;
211     break;
212   case ThunderX3T110:
213     CacheLineSize = 64;
214     PrefFunctionLogAlignment = 4;
215     PrefLoopLogAlignment = 2;
216     MaxInterleaveFactor = 4;
217     PrefetchDistance = 128;
218     MinPrefetchStride = 1024;
219     MaxPrefetchIterationsAhead = 4;
220     // FIXME: remove this to enable 64-bit SLP if performance looks good.
221     MinVectorRegisterBitWidth = 128;
222     break;
223   }
224 }
225 
226 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
227                                    const std::string &TuneCPU,
228                                    const std::string &FS,
229                                    const TargetMachine &TM, bool LittleEndian,
230                                    unsigned MinSVEVectorSizeInBitsOverride,
231                                    unsigned MaxSVEVectorSizeInBitsOverride)
232     : AArch64GenSubtargetInfo(TT, CPU, TuneCPU, FS),
233       ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
234       CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
235       IsLittle(LittleEndian),
236       MinSVEVectorSizeInBits(MinSVEVectorSizeInBitsOverride),
237       MaxSVEVectorSizeInBits(MaxSVEVectorSizeInBitsOverride), TargetTriple(TT),
238       InstrInfo(initializeSubtargetDependencies(FS, CPU, TuneCPU)),
239       TLInfo(TM, *this) {
240   if (AArch64::isX18ReservedByDefault(TT))
241     ReserveXRegister.set(18);
242 
243   CallLoweringInfo.reset(new AArch64CallLowering(*getTargetLowering()));
244   InlineAsmLoweringInfo.reset(new InlineAsmLowering(getTargetLowering()));
245   Legalizer.reset(new AArch64LegalizerInfo(*this));
246 
247   auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
248 
249   // FIXME: At this point, we can't rely on Subtarget having RBI.
250   // It's awkward to mix passing RBI and the Subtarget; should we pass
251   // TII/TRI as well?
252   InstSelector.reset(createAArch64InstructionSelector(
253       *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
254 
255   RegBankInfo.reset(RBI);
256 }
257 
258 const CallLowering *AArch64Subtarget::getCallLowering() const {
259   return CallLoweringInfo.get();
260 }
261 
262 const InlineAsmLowering *AArch64Subtarget::getInlineAsmLowering() const {
263   return InlineAsmLoweringInfo.get();
264 }
265 
266 InstructionSelector *AArch64Subtarget::getInstructionSelector() const {
267   return InstSelector.get();
268 }
269 
270 const LegalizerInfo *AArch64Subtarget::getLegalizerInfo() const {
271   return Legalizer.get();
272 }
273 
274 const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
275   return RegBankInfo.get();
276 }
277 
278 /// Find the target operand flags that describe how a global value should be
279 /// referenced for the current subtarget.
280 unsigned
281 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
282                                           const TargetMachine &TM) const {
283   // MachO large model always goes via a GOT, simply to get a single 8-byte
284   // absolute relocation on all global addresses.
285   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
286     return AArch64II::MO_GOT;
287 
288   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) {
289     if (GV->hasDLLImportStorageClass())
290       return AArch64II::MO_GOT | AArch64II::MO_DLLIMPORT;
291     if (getTargetTriple().isOSWindows())
292       return AArch64II::MO_GOT | AArch64II::MO_COFFSTUB;
293     return AArch64II::MO_GOT;
294   }
295 
296   // The small code model's direct accesses use ADRP, which cannot
297   // necessarily produce the value 0 (if the code is above 4GB).
298   // Same for the tiny code model, where we have a pc relative LDR.
299   if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&
300       GV->hasExternalWeakLinkage())
301     return AArch64II::MO_GOT;
302 
303   // References to tagged globals are marked with MO_NC | MO_TAGGED to indicate
304   // that their nominal addresses are tagged and outside of the code model. In
305   // AArch64ExpandPseudo::expandMI we emit an additional instruction to set the
306   // tag if necessary based on MO_TAGGED.
307   if (AllowTaggedGlobals && !isa<FunctionType>(GV->getValueType()))
308     return AArch64II::MO_NC | AArch64II::MO_TAGGED;
309 
310   return AArch64II::MO_NO_FLAG;
311 }
312 
313 unsigned AArch64Subtarget::classifyGlobalFunctionReference(
314     const GlobalValue *GV, const TargetMachine &TM) const {
315   // MachO large model always goes via a GOT, because we don't have the
316   // relocations available to do anything else..
317   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
318       !GV->hasInternalLinkage())
319     return AArch64II::MO_GOT;
320 
321   // NonLazyBind goes via GOT unless we know it's available locally.
322   auto *F = dyn_cast<Function>(GV);
323   if (UseNonLazyBind && F && F->hasFnAttribute(Attribute::NonLazyBind) &&
324       !TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
325     return AArch64II::MO_GOT;
326 
327   // Use ClassifyGlobalReference for setting MO_DLLIMPORT/MO_COFFSTUB.
328   if (getTargetTriple().isOSWindows())
329     return ClassifyGlobalReference(GV, TM);
330 
331   return AArch64II::MO_NO_FLAG;
332 }
333 
334 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
335                                            unsigned NumRegionInstrs) const {
336   // LNT run (at least on Cyclone) showed reasonably significant gains for
337   // bi-directional scheduling. 253.perlbmk.
338   Policy.OnlyTopDown = false;
339   Policy.OnlyBottomUp = false;
340   // Enabling or Disabling the latency heuristic is a close call: It seems to
341   // help nearly no benchmark on out-of-order architectures, on the other hand
342   // it regresses register pressure on a few benchmarking.
343   Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
344 }
345 
346 bool AArch64Subtarget::enableEarlyIfConversion() const {
347   return EnableEarlyIfConvert;
348 }
349 
350 bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
351   if (!UseAddressTopByteIgnored)
352     return false;
353 
354   if (TargetTriple.isiOS()) {
355     return TargetTriple.getiOSVersion() >= VersionTuple(8);
356   }
357 
358   return false;
359 }
360 
361 std::unique_ptr<PBQPRAConstraint>
362 AArch64Subtarget::getCustomPBQPConstraints() const {
363   return balanceFPOps() ? std::make_unique<A57ChainingConstraint>() : nullptr;
364 }
365 
366 void AArch64Subtarget::mirFileLoaded(MachineFunction &MF) const {
367   // We usually compute max call frame size after ISel. Do the computation now
368   // if the .mir file didn't specify it. Note that this will probably give you
369   // bogus values after PEI has eliminated the callframe setup/destroy pseudo
370   // instructions, specify explicitly if you need it to be correct.
371   MachineFrameInfo &MFI = MF.getFrameInfo();
372   if (!MFI.isMaxCallFrameSizeComputed())
373     MFI.computeMaxCallFrameSize(MF);
374 }
375 
376 bool AArch64Subtarget::useSVEForFixedLengthVectors() const {
377   // Prefer NEON unless larger SVE registers are available.
378   return hasSVE() && getMinSVEVectorSizeInBits() >= 256;
379 }
380 
381 bool AArch64Subtarget::useAA() const { return UseAA; }
382