1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the AArch64 specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64Subtarget.h"
14 
15 #include "AArch64.h"
16 #include "AArch64InstrInfo.h"
17 #include "AArch64PBQPRegAlloc.h"
18 #include "AArch64TargetMachine.h"
19 #include "GISel/AArch64CallLowering.h"
20 #include "GISel/AArch64LegalizerInfo.h"
21 #include "GISel/AArch64RegisterBankInfo.h"
22 #include "MCTargetDesc/AArch64AddressingModes.h"
23 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
24 #include "llvm/CodeGen/MachineScheduler.h"
25 #include "llvm/IR/GlobalValue.h"
26 #include "llvm/Support/TargetParser.h"
27 
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "aarch64-subtarget"
31 
32 #define GET_SUBTARGETINFO_CTOR
33 #define GET_SUBTARGETINFO_TARGET_DESC
34 #include "AArch64GenSubtargetInfo.inc"
35 
36 static cl::opt<bool>
37 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
38                      "converter pass"), cl::init(true), cl::Hidden);
39 
40 // If OS supports TBI, use this flag to enable it.
41 static cl::opt<bool>
42 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
43                          "an address is ignored"), cl::init(false), cl::Hidden);
44 
45 static cl::opt<bool>
46     UseNonLazyBind("aarch64-enable-nonlazybind",
47                    cl::desc("Call nonlazybind functions via direct GOT load"),
48                    cl::init(false), cl::Hidden);
49 
50 static cl::opt<unsigned> SVEVectorBitsMax(
51     "aarch64-sve-vector-bits-max",
52     cl::desc("Assume SVE vector registers are at most this big, "
53              "with zero meaning no maximum size is assumed."),
54     cl::init(0), cl::Hidden);
55 
56 static cl::opt<unsigned> SVEVectorBitsMin(
57     "aarch64-sve-vector-bits-min",
58     cl::desc("Assume SVE vector registers are at least this big, "
59              "with zero meaning no minimum size is assumed."),
60     cl::init(0), cl::Hidden);
61 
62 AArch64Subtarget &
63 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS,
64                                                   StringRef CPUString) {
65   // Determine default and user-specified characteristics
66 
67   if (CPUString.empty())
68     CPUString = "generic";
69 
70   ParseSubtargetFeatures(CPUString, /*TuneCPU*/ CPUString, FS);
71   initializeProperties();
72 
73   return *this;
74 }
75 
76 void AArch64Subtarget::initializeProperties() {
77   // Initialize CPU specific properties. We should add a tablegen feature for
78   // this in the future so we can specify it together with the subtarget
79   // features.
80   switch (ARMProcFamily) {
81   case Others:
82     break;
83   case Carmel:
84     CacheLineSize = 64;
85     break;
86   case CortexA35:
87     break;
88   case CortexA53:
89     PrefFunctionLogAlignment = 3;
90     break;
91   case CortexA55:
92     break;
93   case CortexA57:
94     MaxInterleaveFactor = 4;
95     PrefFunctionLogAlignment = 4;
96     break;
97   case CortexA65:
98     PrefFunctionLogAlignment = 3;
99     break;
100   case CortexA72:
101   case CortexA73:
102   case CortexA75:
103   case CortexA76:
104   case CortexA77:
105   case CortexA78:
106   case CortexR82:
107   case CortexX1:
108     PrefFunctionLogAlignment = 4;
109     break;
110   case A64FX:
111     CacheLineSize = 256;
112     PrefFunctionLogAlignment = 5;
113     PrefLoopLogAlignment = 5;
114     break;
115   case AppleA7:
116   case AppleA10:
117   case AppleA11:
118   case AppleA12:
119   case AppleA13:
120     CacheLineSize = 64;
121     PrefetchDistance = 280;
122     MinPrefetchStride = 2048;
123     MaxPrefetchIterationsAhead = 3;
124     break;
125   case ExynosM3:
126     MaxInterleaveFactor = 4;
127     MaxJumpTableSize = 20;
128     PrefFunctionLogAlignment = 5;
129     PrefLoopLogAlignment = 4;
130     break;
131   case Falkor:
132     MaxInterleaveFactor = 4;
133     // FIXME: remove this to enable 64-bit SLP if performance looks good.
134     MinVectorRegisterBitWidth = 128;
135     CacheLineSize = 128;
136     PrefetchDistance = 820;
137     MinPrefetchStride = 2048;
138     MaxPrefetchIterationsAhead = 8;
139     break;
140   case Kryo:
141     MaxInterleaveFactor = 4;
142     VectorInsertExtractBaseCost = 2;
143     CacheLineSize = 128;
144     PrefetchDistance = 740;
145     MinPrefetchStride = 1024;
146     MaxPrefetchIterationsAhead = 11;
147     // FIXME: remove this to enable 64-bit SLP if performance looks good.
148     MinVectorRegisterBitWidth = 128;
149     break;
150   case NeoverseE1:
151     PrefFunctionLogAlignment = 3;
152     break;
153   case NeoverseN1:
154     PrefFunctionLogAlignment = 4;
155     break;
156   case Saphira:
157     MaxInterleaveFactor = 4;
158     // FIXME: remove this to enable 64-bit SLP if performance looks good.
159     MinVectorRegisterBitWidth = 128;
160     break;
161   case ThunderX2T99:
162     CacheLineSize = 64;
163     PrefFunctionLogAlignment = 3;
164     PrefLoopLogAlignment = 2;
165     MaxInterleaveFactor = 4;
166     PrefetchDistance = 128;
167     MinPrefetchStride = 1024;
168     MaxPrefetchIterationsAhead = 4;
169     // FIXME: remove this to enable 64-bit SLP if performance looks good.
170     MinVectorRegisterBitWidth = 128;
171     break;
172   case ThunderX:
173   case ThunderXT88:
174   case ThunderXT81:
175   case ThunderXT83:
176     CacheLineSize = 128;
177     PrefFunctionLogAlignment = 3;
178     PrefLoopLogAlignment = 2;
179     // FIXME: remove this to enable 64-bit SLP if performance looks good.
180     MinVectorRegisterBitWidth = 128;
181     break;
182   case TSV110:
183     CacheLineSize = 64;
184     PrefFunctionLogAlignment = 4;
185     PrefLoopLogAlignment = 2;
186     break;
187   case ThunderX3T110:
188     CacheLineSize = 64;
189     PrefFunctionLogAlignment = 4;
190     PrefLoopLogAlignment = 2;
191     MaxInterleaveFactor = 4;
192     PrefetchDistance = 128;
193     MinPrefetchStride = 1024;
194     MaxPrefetchIterationsAhead = 4;
195     // FIXME: remove this to enable 64-bit SLP if performance looks good.
196     MinVectorRegisterBitWidth = 128;
197     break;
198   }
199 }
200 
201 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
202                                    const std::string &FS,
203                                    const TargetMachine &TM, bool LittleEndian)
204     : AArch64GenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
205       ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
206       CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
207       IsLittle(LittleEndian),
208       TargetTriple(TT), FrameLowering(),
209       InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(),
210       TLInfo(TM, *this) {
211   if (AArch64::isX18ReservedByDefault(TT))
212     ReserveXRegister.set(18);
213 
214   CallLoweringInfo.reset(new AArch64CallLowering(*getTargetLowering()));
215   InlineAsmLoweringInfo.reset(new InlineAsmLowering(getTargetLowering()));
216   Legalizer.reset(new AArch64LegalizerInfo(*this));
217 
218   auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
219 
220   // FIXME: At this point, we can't rely on Subtarget having RBI.
221   // It's awkward to mix passing RBI and the Subtarget; should we pass
222   // TII/TRI as well?
223   InstSelector.reset(createAArch64InstructionSelector(
224       *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
225 
226   RegBankInfo.reset(RBI);
227 }
228 
229 const CallLowering *AArch64Subtarget::getCallLowering() const {
230   return CallLoweringInfo.get();
231 }
232 
233 const InlineAsmLowering *AArch64Subtarget::getInlineAsmLowering() const {
234   return InlineAsmLoweringInfo.get();
235 }
236 
237 InstructionSelector *AArch64Subtarget::getInstructionSelector() const {
238   return InstSelector.get();
239 }
240 
241 const LegalizerInfo *AArch64Subtarget::getLegalizerInfo() const {
242   return Legalizer.get();
243 }
244 
245 const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
246   return RegBankInfo.get();
247 }
248 
249 /// Find the target operand flags that describe how a global value should be
250 /// referenced for the current subtarget.
251 unsigned
252 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
253                                           const TargetMachine &TM) const {
254   // MachO large model always goes via a GOT, simply to get a single 8-byte
255   // absolute relocation on all global addresses.
256   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
257     return AArch64II::MO_GOT;
258 
259   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) {
260     if (GV->hasDLLImportStorageClass())
261       return AArch64II::MO_GOT | AArch64II::MO_DLLIMPORT;
262     if (getTargetTriple().isOSWindows())
263       return AArch64II::MO_GOT | AArch64II::MO_COFFSTUB;
264     return AArch64II::MO_GOT;
265   }
266 
267   // The small code model's direct accesses use ADRP, which cannot
268   // necessarily produce the value 0 (if the code is above 4GB).
269   // Same for the tiny code model, where we have a pc relative LDR.
270   if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&
271       GV->hasExternalWeakLinkage())
272     return AArch64II::MO_GOT;
273 
274   // References to tagged globals are marked with MO_NC | MO_TAGGED to indicate
275   // that their nominal addresses are tagged and outside of the code model. In
276   // AArch64ExpandPseudo::expandMI we emit an additional instruction to set the
277   // tag if necessary based on MO_TAGGED.
278   if (AllowTaggedGlobals && !isa<FunctionType>(GV->getValueType()))
279     return AArch64II::MO_NC | AArch64II::MO_TAGGED;
280 
281   return AArch64II::MO_NO_FLAG;
282 }
283 
284 unsigned AArch64Subtarget::classifyGlobalFunctionReference(
285     const GlobalValue *GV, const TargetMachine &TM) const {
286   // MachO large model always goes via a GOT, because we don't have the
287   // relocations available to do anything else..
288   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
289       !GV->hasInternalLinkage())
290     return AArch64II::MO_GOT;
291 
292   // NonLazyBind goes via GOT unless we know it's available locally.
293   auto *F = dyn_cast<Function>(GV);
294   if (UseNonLazyBind && F && F->hasFnAttribute(Attribute::NonLazyBind) &&
295       !TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
296     return AArch64II::MO_GOT;
297 
298   // Use ClassifyGlobalReference for setting MO_DLLIMPORT/MO_COFFSTUB.
299   if (getTargetTriple().isOSWindows())
300     return ClassifyGlobalReference(GV, TM);
301 
302   return AArch64II::MO_NO_FLAG;
303 }
304 
305 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
306                                            unsigned NumRegionInstrs) const {
307   // LNT run (at least on Cyclone) showed reasonably significant gains for
308   // bi-directional scheduling. 253.perlbmk.
309   Policy.OnlyTopDown = false;
310   Policy.OnlyBottomUp = false;
311   // Enabling or Disabling the latency heuristic is a close call: It seems to
312   // help nearly no benchmark on out-of-order architectures, on the other hand
313   // it regresses register pressure on a few benchmarking.
314   Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
315 }
316 
317 bool AArch64Subtarget::enableEarlyIfConversion() const {
318   return EnableEarlyIfConvert;
319 }
320 
321 bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
322   if (!UseAddressTopByteIgnored)
323     return false;
324 
325   if (TargetTriple.isiOS()) {
326     unsigned Major, Minor, Micro;
327     TargetTriple.getiOSVersion(Major, Minor, Micro);
328     return Major >= 8;
329   }
330 
331   return false;
332 }
333 
334 std::unique_ptr<PBQPRAConstraint>
335 AArch64Subtarget::getCustomPBQPConstraints() const {
336   return balanceFPOps() ? std::make_unique<A57ChainingConstraint>() : nullptr;
337 }
338 
339 void AArch64Subtarget::mirFileLoaded(MachineFunction &MF) const {
340   // We usually compute max call frame size after ISel. Do the computation now
341   // if the .mir file didn't specify it. Note that this will probably give you
342   // bogus values after PEI has eliminated the callframe setup/destroy pseudo
343   // instructions, specify explicitly if you need it to be correct.
344   MachineFrameInfo &MFI = MF.getFrameInfo();
345   if (!MFI.isMaxCallFrameSizeComputed())
346     MFI.computeMaxCallFrameSize(MF);
347 }
348 
349 unsigned AArch64Subtarget::getMaxSVEVectorSizeInBits() const {
350   assert(HasSVE && "Tried to get SVE vector length without SVE support!");
351   assert(SVEVectorBitsMax % 128 == 0 &&
352          "SVE requires vector length in multiples of 128!");
353   assert((SVEVectorBitsMax >= SVEVectorBitsMin || SVEVectorBitsMax == 0) &&
354          "Minimum SVE vector size should not be larger than its maximum!");
355   if (SVEVectorBitsMax == 0)
356     return 0;
357   return (std::max(SVEVectorBitsMin, SVEVectorBitsMax) / 128) * 128;
358 }
359 
360 unsigned AArch64Subtarget::getMinSVEVectorSizeInBits() const {
361   assert(HasSVE && "Tried to get SVE vector length without SVE support!");
362   assert(SVEVectorBitsMin % 128 == 0 &&
363          "SVE requires vector length in multiples of 128!");
364   assert((SVEVectorBitsMax >= SVEVectorBitsMin || SVEVectorBitsMax == 0) &&
365          "Minimum SVE vector size should not be larger than its maximum!");
366   if (SVEVectorBitsMax == 0)
367     return (SVEVectorBitsMin / 128) * 128;
368   return (std::min(SVEVectorBitsMin, SVEVectorBitsMax) / 128) * 128;
369 }
370