1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the AArch64 specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64Subtarget.h"
14 
15 #include "AArch64.h"
16 #include "AArch64InstrInfo.h"
17 #include "AArch64PBQPRegAlloc.h"
18 #include "AArch64TargetMachine.h"
19 #include "GISel/AArch64CallLowering.h"
20 #include "GISel/AArch64LegalizerInfo.h"
21 #include "GISel/AArch64RegisterBankInfo.h"
22 #include "MCTargetDesc/AArch64AddressingModes.h"
23 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
24 #include "llvm/CodeGen/MachineScheduler.h"
25 #include "llvm/IR/GlobalValue.h"
26 #include "llvm/Support/TargetParser.h"
27 
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "aarch64-subtarget"
31 
32 #define GET_SUBTARGETINFO_CTOR
33 #define GET_SUBTARGETINFO_TARGET_DESC
34 #include "AArch64GenSubtargetInfo.inc"
35 
36 static cl::opt<bool>
37 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
38                      "converter pass"), cl::init(true), cl::Hidden);
39 
40 // If OS supports TBI, use this flag to enable it.
41 static cl::opt<bool>
42 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
43                          "an address is ignored"), cl::init(false), cl::Hidden);
44 
45 static cl::opt<bool>
46     UseNonLazyBind("aarch64-enable-nonlazybind",
47                    cl::desc("Call nonlazybind functions via direct GOT load"),
48                    cl::init(false), cl::Hidden);
49 
50 static cl::opt<unsigned> SVEVectorBitsMax(
51     "aarch64-sve-vector-bits-max",
52     cl::desc("Assume SVE vector registers are at most this big, "
53              "with zero meaning no maximum size is assumed."),
54     cl::init(0), cl::Hidden);
55 
56 static cl::opt<unsigned> SVEVectorBitsMin(
57     "aarch64-sve-vector-bits-min",
58     cl::desc("Assume SVE vector registers are at least this big, "
59              "with zero meaning no minimum size is assumed."),
60     cl::init(0), cl::Hidden);
61 
62 AArch64Subtarget &
63 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS,
64                                                   StringRef CPUString) {
65   // Determine default and user-specified characteristics
66 
67   if (CPUString.empty())
68     CPUString = "generic";
69 
70   ParseSubtargetFeatures(CPUString, FS);
71   initializeProperties();
72 
73   return *this;
74 }
75 
76 void AArch64Subtarget::initializeProperties() {
77   // Initialize CPU specific properties. We should add a tablegen feature for
78   // this in the future so we can specify it together with the subtarget
79   // features.
80   switch (ARMProcFamily) {
81   case Others:
82     break;
83   case Carmel:
84     CacheLineSize = 64;
85     break;
86   case CortexA35:
87     break;
88   case CortexA53:
89     PrefFunctionLogAlignment = 3;
90     break;
91   case CortexA55:
92     break;
93   case CortexA57:
94     MaxInterleaveFactor = 4;
95     PrefFunctionLogAlignment = 4;
96     break;
97   case CortexA65:
98     PrefFunctionLogAlignment = 3;
99     break;
100   case CortexA72:
101   case CortexA73:
102   case CortexA75:
103   case CortexA76:
104     PrefFunctionLogAlignment = 4;
105     break;
106   case A64FX:
107     CacheLineSize = 256;
108     PrefFunctionLogAlignment = 5;
109     PrefLoopLogAlignment = 5;
110     break;
111   case AppleA7:
112   case AppleA10:
113   case AppleA11:
114   case AppleA12:
115   case AppleA13:
116     CacheLineSize = 64;
117     PrefetchDistance = 280;
118     MinPrefetchStride = 2048;
119     MaxPrefetchIterationsAhead = 3;
120     break;
121   case ExynosM3:
122     MaxInterleaveFactor = 4;
123     MaxJumpTableSize = 20;
124     PrefFunctionLogAlignment = 5;
125     PrefLoopLogAlignment = 4;
126     break;
127   case Falkor:
128     MaxInterleaveFactor = 4;
129     // FIXME: remove this to enable 64-bit SLP if performance looks good.
130     MinVectorRegisterBitWidth = 128;
131     CacheLineSize = 128;
132     PrefetchDistance = 820;
133     MinPrefetchStride = 2048;
134     MaxPrefetchIterationsAhead = 8;
135     break;
136   case Kryo:
137     MaxInterleaveFactor = 4;
138     VectorInsertExtractBaseCost = 2;
139     CacheLineSize = 128;
140     PrefetchDistance = 740;
141     MinPrefetchStride = 1024;
142     MaxPrefetchIterationsAhead = 11;
143     // FIXME: remove this to enable 64-bit SLP if performance looks good.
144     MinVectorRegisterBitWidth = 128;
145     break;
146   case NeoverseE1:
147     PrefFunctionLogAlignment = 3;
148     break;
149   case NeoverseN1:
150     PrefFunctionLogAlignment = 4;
151     break;
152   case Saphira:
153     MaxInterleaveFactor = 4;
154     // FIXME: remove this to enable 64-bit SLP if performance looks good.
155     MinVectorRegisterBitWidth = 128;
156     break;
157   case ThunderX2T99:
158     CacheLineSize = 64;
159     PrefFunctionLogAlignment = 3;
160     PrefLoopLogAlignment = 2;
161     MaxInterleaveFactor = 4;
162     PrefetchDistance = 128;
163     MinPrefetchStride = 1024;
164     MaxPrefetchIterationsAhead = 4;
165     // FIXME: remove this to enable 64-bit SLP if performance looks good.
166     MinVectorRegisterBitWidth = 128;
167     break;
168   case ThunderX:
169   case ThunderXT88:
170   case ThunderXT81:
171   case ThunderXT83:
172     CacheLineSize = 128;
173     PrefFunctionLogAlignment = 3;
174     PrefLoopLogAlignment = 2;
175     // FIXME: remove this to enable 64-bit SLP if performance looks good.
176     MinVectorRegisterBitWidth = 128;
177     break;
178   case TSV110:
179     CacheLineSize = 64;
180     PrefFunctionLogAlignment = 4;
181     PrefLoopLogAlignment = 2;
182     break;
183   case ThunderX3T110:
184     CacheLineSize = 64;
185     PrefFunctionLogAlignment = 4;
186     PrefLoopLogAlignment = 2;
187     MaxInterleaveFactor = 4;
188     PrefetchDistance = 128;
189     MinPrefetchStride = 1024;
190     MaxPrefetchIterationsAhead = 4;
191     // FIXME: remove this to enable 64-bit SLP if performance looks good.
192     MinVectorRegisterBitWidth = 128;
193     break;
194   }
195 }
196 
197 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
198                                    const std::string &FS,
199                                    const TargetMachine &TM, bool LittleEndian)
200     : AArch64GenSubtargetInfo(TT, CPU, FS),
201       ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
202       CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
203       IsLittle(LittleEndian),
204       TargetTriple(TT), FrameLowering(),
205       InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(),
206       TLInfo(TM, *this) {
207   if (AArch64::isX18ReservedByDefault(TT))
208     ReserveXRegister.set(18);
209 
210   CallLoweringInfo.reset(new AArch64CallLowering(*getTargetLowering()));
211   InlineAsmLoweringInfo.reset(new InlineAsmLowering(getTargetLowering()));
212   Legalizer.reset(new AArch64LegalizerInfo(*this));
213 
214   auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
215 
216   // FIXME: At this point, we can't rely on Subtarget having RBI.
217   // It's awkward to mix passing RBI and the Subtarget; should we pass
218   // TII/TRI as well?
219   InstSelector.reset(createAArch64InstructionSelector(
220       *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
221 
222   RegBankInfo.reset(RBI);
223 }
224 
225 const CallLowering *AArch64Subtarget::getCallLowering() const {
226   return CallLoweringInfo.get();
227 }
228 
229 const InlineAsmLowering *AArch64Subtarget::getInlineAsmLowering() const {
230   return InlineAsmLoweringInfo.get();
231 }
232 
233 InstructionSelector *AArch64Subtarget::getInstructionSelector() const {
234   return InstSelector.get();
235 }
236 
237 const LegalizerInfo *AArch64Subtarget::getLegalizerInfo() const {
238   return Legalizer.get();
239 }
240 
241 const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
242   return RegBankInfo.get();
243 }
244 
245 /// Find the target operand flags that describe how a global value should be
246 /// referenced for the current subtarget.
247 unsigned
248 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
249                                           const TargetMachine &TM) const {
250   // MachO large model always goes via a GOT, simply to get a single 8-byte
251   // absolute relocation on all global addresses.
252   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
253     return AArch64II::MO_GOT;
254 
255   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) {
256     if (GV->hasDLLImportStorageClass())
257       return AArch64II::MO_GOT | AArch64II::MO_DLLIMPORT;
258     if (getTargetTriple().isOSWindows())
259       return AArch64II::MO_GOT | AArch64II::MO_COFFSTUB;
260     return AArch64II::MO_GOT;
261   }
262 
263   // The small code model's direct accesses use ADRP, which cannot
264   // necessarily produce the value 0 (if the code is above 4GB).
265   // Same for the tiny code model, where we have a pc relative LDR.
266   if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&
267       GV->hasExternalWeakLinkage())
268     return AArch64II::MO_GOT;
269 
270   // References to tagged globals are marked with MO_NC | MO_TAGGED to indicate
271   // that their nominal addresses are tagged and outside of the code model. In
272   // AArch64ExpandPseudo::expandMI we emit an additional instruction to set the
273   // tag if necessary based on MO_TAGGED.
274   if (AllowTaggedGlobals && !isa<FunctionType>(GV->getValueType()))
275     return AArch64II::MO_NC | AArch64II::MO_TAGGED;
276 
277   return AArch64II::MO_NO_FLAG;
278 }
279 
280 unsigned AArch64Subtarget::classifyGlobalFunctionReference(
281     const GlobalValue *GV, const TargetMachine &TM) const {
282   // MachO large model always goes via a GOT, because we don't have the
283   // relocations available to do anything else..
284   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
285       !GV->hasInternalLinkage())
286     return AArch64II::MO_GOT;
287 
288   // NonLazyBind goes via GOT unless we know it's available locally.
289   auto *F = dyn_cast<Function>(GV);
290   if (UseNonLazyBind && F && F->hasFnAttribute(Attribute::NonLazyBind) &&
291       !TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
292     return AArch64II::MO_GOT;
293 
294   // Use ClassifyGlobalReference for setting MO_DLLIMPORT/MO_COFFSTUB.
295   if (getTargetTriple().isOSWindows())
296     return ClassifyGlobalReference(GV, TM);
297 
298   return AArch64II::MO_NO_FLAG;
299 }
300 
301 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
302                                            unsigned NumRegionInstrs) const {
303   // LNT run (at least on Cyclone) showed reasonably significant gains for
304   // bi-directional scheduling. 253.perlbmk.
305   Policy.OnlyTopDown = false;
306   Policy.OnlyBottomUp = false;
307   // Enabling or Disabling the latency heuristic is a close call: It seems to
308   // help nearly no benchmark on out-of-order architectures, on the other hand
309   // it regresses register pressure on a few benchmarking.
310   Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
311 }
312 
313 bool AArch64Subtarget::enableEarlyIfConversion() const {
314   return EnableEarlyIfConvert;
315 }
316 
317 bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
318   if (!UseAddressTopByteIgnored)
319     return false;
320 
321   if (TargetTriple.isiOS()) {
322     unsigned Major, Minor, Micro;
323     TargetTriple.getiOSVersion(Major, Minor, Micro);
324     return Major >= 8;
325   }
326 
327   return false;
328 }
329 
330 std::unique_ptr<PBQPRAConstraint>
331 AArch64Subtarget::getCustomPBQPConstraints() const {
332   return balanceFPOps() ? std::make_unique<A57ChainingConstraint>() : nullptr;
333 }
334 
335 void AArch64Subtarget::mirFileLoaded(MachineFunction &MF) const {
336   // We usually compute max call frame size after ISel. Do the computation now
337   // if the .mir file didn't specify it. Note that this will probably give you
338   // bogus values after PEI has eliminated the callframe setup/destroy pseudo
339   // instructions, specify explicitly if you need it to be correct.
340   MachineFrameInfo &MFI = MF.getFrameInfo();
341   if (!MFI.isMaxCallFrameSizeComputed())
342     MFI.computeMaxCallFrameSize(MF);
343 }
344 
345 unsigned AArch64Subtarget::getMaxSVEVectorSizeInBits() const {
346   assert(HasSVE && "Tried to get SVE vector length without SVE support!");
347   assert(SVEVectorBitsMax % 128 == 0 &&
348          "SVE requires vector length in multiples of 128!");
349   assert((SVEVectorBitsMax >= SVEVectorBitsMin || SVEVectorBitsMax == 0) &&
350          "Minimum SVE vector size should not be larger than its maximum!");
351   if (SVEVectorBitsMax == 0)
352     return 0;
353   return (std::max(SVEVectorBitsMin, SVEVectorBitsMax) / 128) * 128;
354 }
355 
356 unsigned AArch64Subtarget::getMinSVEVectorSizeInBits() const {
357   assert(HasSVE && "Tried to get SVE vector length without SVE support!");
358   assert(SVEVectorBitsMin % 128 == 0 &&
359          "SVE requires vector length in multiples of 128!");
360   assert((SVEVectorBitsMax >= SVEVectorBitsMin || SVEVectorBitsMax == 0) &&
361          "Minimum SVE vector size should not be larger than its maximum!");
362   if (SVEVectorBitsMax == 0)
363     return (SVEVectorBitsMin / 128) * 128;
364   return (std::min(SVEVectorBitsMin, SVEVectorBitsMax) / 128) * 128;
365 }
366