1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the AArch64 specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64Subtarget.h"
14 
15 #include "AArch64.h"
16 #include "AArch64InstrInfo.h"
17 #include "AArch64PBQPRegAlloc.h"
18 #include "AArch64TargetMachine.h"
19 #include "GISel/AArch64CallLowering.h"
20 #include "GISel/AArch64LegalizerInfo.h"
21 #include "GISel/AArch64RegisterBankInfo.h"
22 #include "MCTargetDesc/AArch64AddressingModes.h"
23 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
24 #include "llvm/CodeGen/MachineScheduler.h"
25 #include "llvm/IR/GlobalValue.h"
26 #include "llvm/Support/TargetParser.h"
27 
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "aarch64-subtarget"
31 
32 #define GET_SUBTARGETINFO_CTOR
33 #define GET_SUBTARGETINFO_TARGET_DESC
34 #include "AArch64GenSubtargetInfo.inc"
35 
36 static cl::opt<bool>
37 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
38                      "converter pass"), cl::init(true), cl::Hidden);
39 
40 // If OS supports TBI, use this flag to enable it.
41 static cl::opt<bool>
42 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
43                          "an address is ignored"), cl::init(false), cl::Hidden);
44 
45 static cl::opt<bool>
46     UseNonLazyBind("aarch64-enable-nonlazybind",
47                    cl::desc("Call nonlazybind functions via direct GOT load"),
48                    cl::init(false), cl::Hidden);
49 
50 static cl::opt<bool> UseAA("aarch64-use-aa", cl::init(true),
51                            cl::desc("Enable the use of AA during codegen."));
52 
53 AArch64Subtarget &
54 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS,
55                                                   StringRef CPUString) {
56   // Determine default and user-specified characteristics
57 
58   if (CPUString.empty())
59     CPUString = "generic";
60 
61   ParseSubtargetFeatures(CPUString, /*TuneCPU*/ CPUString, FS);
62   initializeProperties();
63 
64   return *this;
65 }
66 
67 void AArch64Subtarget::initializeProperties() {
68   // Initialize CPU specific properties. We should add a tablegen feature for
69   // this in the future so we can specify it together with the subtarget
70   // features.
71   switch (ARMProcFamily) {
72   case Others:
73     break;
74   case Carmel:
75     CacheLineSize = 64;
76     break;
77   case CortexA35:
78     break;
79   case CortexA53:
80   case CortexA55:
81   case CortexA510:
82     PrefFunctionLogAlignment = 4;
83     break;
84   case CortexA57:
85     MaxInterleaveFactor = 4;
86     PrefFunctionLogAlignment = 4;
87     break;
88   case CortexA65:
89     PrefFunctionLogAlignment = 3;
90     break;
91   case CortexA72:
92   case CortexA73:
93   case CortexA75:
94   case CortexA76:
95   case CortexA77:
96   case CortexA78:
97   case CortexA78C:
98   case CortexR82:
99   case CortexX1:
100     PrefFunctionLogAlignment = 4;
101     break;
102   case A64FX:
103     CacheLineSize = 256;
104     PrefFunctionLogAlignment = 3;
105     PrefLoopLogAlignment = 2;
106     MaxInterleaveFactor = 4;
107     PrefetchDistance = 128;
108     MinPrefetchStride = 1024;
109     MaxPrefetchIterationsAhead = 4;
110     break;
111   case AppleA7:
112   case AppleA10:
113   case AppleA11:
114   case AppleA12:
115   case AppleA13:
116   case AppleA14:
117     CacheLineSize = 64;
118     PrefetchDistance = 280;
119     MinPrefetchStride = 2048;
120     MaxPrefetchIterationsAhead = 3;
121     break;
122   case ExynosM3:
123     MaxInterleaveFactor = 4;
124     MaxJumpTableSize = 20;
125     PrefFunctionLogAlignment = 5;
126     PrefLoopLogAlignment = 4;
127     break;
128   case Falkor:
129     MaxInterleaveFactor = 4;
130     // FIXME: remove this to enable 64-bit SLP if performance looks good.
131     MinVectorRegisterBitWidth = 128;
132     CacheLineSize = 128;
133     PrefetchDistance = 820;
134     MinPrefetchStride = 2048;
135     MaxPrefetchIterationsAhead = 8;
136     break;
137   case Kryo:
138     MaxInterleaveFactor = 4;
139     VectorInsertExtractBaseCost = 2;
140     CacheLineSize = 128;
141     PrefetchDistance = 740;
142     MinPrefetchStride = 1024;
143     MaxPrefetchIterationsAhead = 11;
144     // FIXME: remove this to enable 64-bit SLP if performance looks good.
145     MinVectorRegisterBitWidth = 128;
146     break;
147   case NeoverseE1:
148     PrefFunctionLogAlignment = 3;
149     break;
150   case NeoverseN1:
151   case NeoverseN2:
152   case NeoverseV1:
153     PrefFunctionLogAlignment = 4;
154     break;
155   case Saphira:
156     MaxInterleaveFactor = 4;
157     // FIXME: remove this to enable 64-bit SLP if performance looks good.
158     MinVectorRegisterBitWidth = 128;
159     break;
160   case ThunderX2T99:
161     CacheLineSize = 64;
162     PrefFunctionLogAlignment = 3;
163     PrefLoopLogAlignment = 2;
164     MaxInterleaveFactor = 4;
165     PrefetchDistance = 128;
166     MinPrefetchStride = 1024;
167     MaxPrefetchIterationsAhead = 4;
168     // FIXME: remove this to enable 64-bit SLP if performance looks good.
169     MinVectorRegisterBitWidth = 128;
170     break;
171   case ThunderX:
172   case ThunderXT88:
173   case ThunderXT81:
174   case ThunderXT83:
175     CacheLineSize = 128;
176     PrefFunctionLogAlignment = 3;
177     PrefLoopLogAlignment = 2;
178     // FIXME: remove this to enable 64-bit SLP if performance looks good.
179     MinVectorRegisterBitWidth = 128;
180     break;
181   case TSV110:
182     CacheLineSize = 64;
183     PrefFunctionLogAlignment = 4;
184     PrefLoopLogAlignment = 2;
185     break;
186   case ThunderX3T110:
187     CacheLineSize = 64;
188     PrefFunctionLogAlignment = 4;
189     PrefLoopLogAlignment = 2;
190     MaxInterleaveFactor = 4;
191     PrefetchDistance = 128;
192     MinPrefetchStride = 1024;
193     MaxPrefetchIterationsAhead = 4;
194     // FIXME: remove this to enable 64-bit SLP if performance looks good.
195     MinVectorRegisterBitWidth = 128;
196     break;
197   }
198 }
199 
200 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
201                                    const std::string &FS,
202                                    const TargetMachine &TM, bool LittleEndian,
203                                    unsigned MinSVEVectorSizeInBitsOverride,
204                                    unsigned MaxSVEVectorSizeInBitsOverride)
205     : AArch64GenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
206       ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
207       CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
208       IsLittle(LittleEndian),
209       MinSVEVectorSizeInBits(MinSVEVectorSizeInBitsOverride),
210       MaxSVEVectorSizeInBits(MaxSVEVectorSizeInBitsOverride), TargetTriple(TT),
211       FrameLowering(), InstrInfo(initializeSubtargetDependencies(FS, CPU)),
212       TSInfo(), TLInfo(TM, *this) {
213   if (AArch64::isX18ReservedByDefault(TT))
214     ReserveXRegister.set(18);
215 
216   CallLoweringInfo.reset(new AArch64CallLowering(*getTargetLowering()));
217   InlineAsmLoweringInfo.reset(new InlineAsmLowering(getTargetLowering()));
218   Legalizer.reset(new AArch64LegalizerInfo(*this));
219 
220   auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
221 
222   // FIXME: At this point, we can't rely on Subtarget having RBI.
223   // It's awkward to mix passing RBI and the Subtarget; should we pass
224   // TII/TRI as well?
225   InstSelector.reset(createAArch64InstructionSelector(
226       *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
227 
228   RegBankInfo.reset(RBI);
229 }
230 
231 const CallLowering *AArch64Subtarget::getCallLowering() const {
232   return CallLoweringInfo.get();
233 }
234 
235 const InlineAsmLowering *AArch64Subtarget::getInlineAsmLowering() const {
236   return InlineAsmLoweringInfo.get();
237 }
238 
239 InstructionSelector *AArch64Subtarget::getInstructionSelector() const {
240   return InstSelector.get();
241 }
242 
243 const LegalizerInfo *AArch64Subtarget::getLegalizerInfo() const {
244   return Legalizer.get();
245 }
246 
247 const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
248   return RegBankInfo.get();
249 }
250 
251 /// Find the target operand flags that describe how a global value should be
252 /// referenced for the current subtarget.
253 unsigned
254 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
255                                           const TargetMachine &TM) const {
256   // MachO large model always goes via a GOT, simply to get a single 8-byte
257   // absolute relocation on all global addresses.
258   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
259     return AArch64II::MO_GOT;
260 
261   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) {
262     if (GV->hasDLLImportStorageClass())
263       return AArch64II::MO_GOT | AArch64II::MO_DLLIMPORT;
264     if (getTargetTriple().isOSWindows())
265       return AArch64II::MO_GOT | AArch64II::MO_COFFSTUB;
266     return AArch64II::MO_GOT;
267   }
268 
269   // The small code model's direct accesses use ADRP, which cannot
270   // necessarily produce the value 0 (if the code is above 4GB).
271   // Same for the tiny code model, where we have a pc relative LDR.
272   if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&
273       GV->hasExternalWeakLinkage())
274     return AArch64II::MO_GOT;
275 
276   // References to tagged globals are marked with MO_NC | MO_TAGGED to indicate
277   // that their nominal addresses are tagged and outside of the code model. In
278   // AArch64ExpandPseudo::expandMI we emit an additional instruction to set the
279   // tag if necessary based on MO_TAGGED.
280   if (AllowTaggedGlobals && !isa<FunctionType>(GV->getValueType()))
281     return AArch64II::MO_NC | AArch64II::MO_TAGGED;
282 
283   return AArch64II::MO_NO_FLAG;
284 }
285 
286 unsigned AArch64Subtarget::classifyGlobalFunctionReference(
287     const GlobalValue *GV, const TargetMachine &TM) const {
288   // MachO large model always goes via a GOT, because we don't have the
289   // relocations available to do anything else..
290   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
291       !GV->hasInternalLinkage())
292     return AArch64II::MO_GOT;
293 
294   // NonLazyBind goes via GOT unless we know it's available locally.
295   auto *F = dyn_cast<Function>(GV);
296   if (UseNonLazyBind && F && F->hasFnAttribute(Attribute::NonLazyBind) &&
297       !TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
298     return AArch64II::MO_GOT;
299 
300   // Use ClassifyGlobalReference for setting MO_DLLIMPORT/MO_COFFSTUB.
301   if (getTargetTriple().isOSWindows())
302     return ClassifyGlobalReference(GV, TM);
303 
304   return AArch64II::MO_NO_FLAG;
305 }
306 
307 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
308                                            unsigned NumRegionInstrs) const {
309   // LNT run (at least on Cyclone) showed reasonably significant gains for
310   // bi-directional scheduling. 253.perlbmk.
311   Policy.OnlyTopDown = false;
312   Policy.OnlyBottomUp = false;
313   // Enabling or Disabling the latency heuristic is a close call: It seems to
314   // help nearly no benchmark on out-of-order architectures, on the other hand
315   // it regresses register pressure on a few benchmarking.
316   Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
317 }
318 
319 bool AArch64Subtarget::enableEarlyIfConversion() const {
320   return EnableEarlyIfConvert;
321 }
322 
323 bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
324   if (!UseAddressTopByteIgnored)
325     return false;
326 
327   if (TargetTriple.isiOS()) {
328     unsigned Major, Minor, Micro;
329     TargetTriple.getiOSVersion(Major, Minor, Micro);
330     return Major >= 8;
331   }
332 
333   return false;
334 }
335 
336 std::unique_ptr<PBQPRAConstraint>
337 AArch64Subtarget::getCustomPBQPConstraints() const {
338   return balanceFPOps() ? std::make_unique<A57ChainingConstraint>() : nullptr;
339 }
340 
341 void AArch64Subtarget::mirFileLoaded(MachineFunction &MF) const {
342   // We usually compute max call frame size after ISel. Do the computation now
343   // if the .mir file didn't specify it. Note that this will probably give you
344   // bogus values after PEI has eliminated the callframe setup/destroy pseudo
345   // instructions, specify explicitly if you need it to be correct.
346   MachineFrameInfo &MFI = MF.getFrameInfo();
347   if (!MFI.isMaxCallFrameSizeComputed())
348     MFI.computeMaxCallFrameSize(MF);
349 }
350 
351 bool AArch64Subtarget::useSVEForFixedLengthVectors() const {
352   // Prefer NEON unless larger SVE registers are available.
353   return hasSVE() && getMinSVEVectorSizeInBits() >= 256;
354 }
355 
356 bool AArch64Subtarget::useAA() const { return UseAA; }
357