1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the AArch64 specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AArch64InstrInfo.h"
15 #include "AArch64PBQPRegAlloc.h"
16 #include "AArch64Subtarget.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/CodeGen/MachineScheduler.h"
19 #include "llvm/IR/GlobalValue.h"
20 #include "llvm/Support/TargetRegistry.h"
21 
22 using namespace llvm;
23 
24 #define DEBUG_TYPE "aarch64-subtarget"
25 
26 #define GET_SUBTARGETINFO_CTOR
27 #define GET_SUBTARGETINFO_TARGET_DESC
28 #include "AArch64GenSubtargetInfo.inc"
29 
30 static cl::opt<bool>
31 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
32                      "converter pass"), cl::init(true), cl::Hidden);
33 
34 AArch64Subtarget &
35 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS) {
36   // Determine default and user-specified characteristics
37 
38   if (CPUString.empty())
39     CPUString = "generic";
40 
41   ParseSubtargetFeatures(CPUString, FS);
42   return *this;
43 }
44 
45 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
46                                    const std::string &FS,
47                                    const TargetMachine &TM, bool LittleEndian)
48     : AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
49       HasV8_1aOps(false), HasFPARMv8(false), HasNEON(false), HasCrypto(false),
50       HasCRC(false), HasZeroCycleRegMove(false), HasZeroCycleZeroing(false),
51       IsLittle(LittleEndian), CPUString(CPU), TargetTriple(TT), FrameLowering(),
52       InstrInfo(initializeSubtargetDependencies(FS)),
53       TSInfo(TM.getDataLayout()), TLInfo(TM, *this) {}
54 
55 /// ClassifyGlobalReference - Find the target operand flags that describe
56 /// how a global value should be referenced for the current subtarget.
57 unsigned char
58 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
59                                         const TargetMachine &TM) const {
60   bool isDecl = GV->isDeclarationForLinker();
61 
62   // MachO large model always goes via a GOT, simply to get a single 8-byte
63   // absolute relocation on all global addresses.
64   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
65     return AArch64II::MO_GOT;
66 
67   // The small code mode's direct accesses use ADRP, which cannot necessarily
68   // produce the value 0 (if the code is above 4GB).
69   if (TM.getCodeModel() == CodeModel::Small &&
70       GV->isWeakForLinker() && isDecl) {
71     // In PIC mode use the GOT, but in absolute mode use a constant pool load.
72     if (TM.getRelocationModel() == Reloc::Static)
73         return AArch64II::MO_CONSTPOOL;
74     else
75         return AArch64II::MO_GOT;
76   }
77 
78   // If symbol visibility is hidden, the extra load is not needed if
79   // the symbol is definitely defined in the current translation unit.
80 
81   // The handling of non-hidden symbols in PIC mode is rather target-dependent:
82   //   + On MachO, if the symbol is defined in this module the GOT can be
83   //     skipped.
84   //   + On ELF, the R_AARCH64_COPY relocation means that even symbols actually
85   //     defined could end up in unexpected places. Use a GOT.
86   if (TM.getRelocationModel() != Reloc::Static && GV->hasDefaultVisibility()) {
87     if (isTargetMachO())
88       return (isDecl || GV->isWeakForLinker()) ? AArch64II::MO_GOT
89                                                : AArch64II::MO_NO_FLAG;
90     else
91       // No need to go through the GOT for local symbols on ELF.
92       return GV->hasLocalLinkage() ? AArch64II::MO_NO_FLAG : AArch64II::MO_GOT;
93   }
94 
95   return AArch64II::MO_NO_FLAG;
96 }
97 
98 /// This function returns the name of a function which has an interface
99 /// like the non-standard bzero function, if such a function exists on
100 /// the current subtarget and it is considered prefereable over
101 /// memset with zero passed as the second argument. Otherwise it
102 /// returns null.
103 const char *AArch64Subtarget::getBZeroEntry() const {
104   // Prefer bzero on Darwin only.
105   if(isTargetDarwin())
106     return "bzero";
107 
108   return nullptr;
109 }
110 
111 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
112                                          MachineInstr *begin, MachineInstr *end,
113                                          unsigned NumRegionInstrs) const {
114   // LNT run (at least on Cyclone) showed reasonably significant gains for
115   // bi-directional scheduling. 253.perlbmk.
116   Policy.OnlyTopDown = false;
117   Policy.OnlyBottomUp = false;
118 }
119 
120 bool AArch64Subtarget::enableEarlyIfConversion() const {
121   return EnableEarlyIfConvert;
122 }
123 
124 std::unique_ptr<PBQPRAConstraint>
125 AArch64Subtarget::getCustomPBQPConstraints() const {
126   if (!isCortexA57())
127     return nullptr;
128 
129   return llvm::make_unique<A57ChainingConstraint>();
130 }
131