1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the AArch64 specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64Subtarget.h"
14 
15 #include "AArch64.h"
16 #include "AArch64InstrInfo.h"
17 #include "AArch64PBQPRegAlloc.h"
18 #include "AArch64TargetMachine.h"
19 #include "GISel/AArch64CallLowering.h"
20 #include "GISel/AArch64LegalizerInfo.h"
21 #include "GISel/AArch64RegisterBankInfo.h"
22 #include "MCTargetDesc/AArch64AddressingModes.h"
23 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
24 #include "llvm/CodeGen/MachineScheduler.h"
25 #include "llvm/IR/GlobalValue.h"
26 #include "llvm/Support/TargetParser.h"
27 
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "aarch64-subtarget"
31 
32 #define GET_SUBTARGETINFO_CTOR
33 #define GET_SUBTARGETINFO_TARGET_DESC
34 #include "AArch64GenSubtargetInfo.inc"
35 
36 static cl::opt<bool>
37 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
38                      "converter pass"), cl::init(true), cl::Hidden);
39 
40 // If OS supports TBI, use this flag to enable it.
41 static cl::opt<bool>
42 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
43                          "an address is ignored"), cl::init(false), cl::Hidden);
44 
45 static cl::opt<bool>
46     UseNonLazyBind("aarch64-enable-nonlazybind",
47                    cl::desc("Call nonlazybind functions via direct GOT load"),
48                    cl::init(false), cl::Hidden);
49 
50 static cl::opt<unsigned> SVEVectorBitsMax(
51     "aarch64-sve-vector-bits-max",
52     cl::desc("Assume SVE vector registers are at most this big, "
53              "with zero meaning no maximum size is assumed."),
54     cl::init(0), cl::Hidden);
55 
56 static cl::opt<unsigned> SVEVectorBitsMin(
57     "aarch64-sve-vector-bits-min",
58     cl::desc("Assume SVE vector registers are at least this big, "
59              "with zero meaning no minimum size is assumed."),
60     cl::init(0), cl::Hidden);
61 
62 AArch64Subtarget &
63 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS,
64                                                   StringRef CPUString) {
65   // Determine default and user-specified characteristics
66 
67   if (CPUString.empty())
68     CPUString = "generic";
69 
70   ParseSubtargetFeatures(CPUString, FS);
71   initializeProperties();
72 
73   return *this;
74 }
75 
76 void AArch64Subtarget::initializeProperties() {
77   // Initialize CPU specific properties. We should add a tablegen feature for
78   // this in the future so we can specify it together with the subtarget
79   // features.
80   switch (ARMProcFamily) {
81   case Others:
82     break;
83   case Carmel:
84     CacheLineSize = 64;
85     break;
86   case CortexA35:
87     break;
88   case CortexA53:
89     PrefFunctionLogAlignment = 3;
90     break;
91   case CortexA55:
92     break;
93   case CortexA57:
94     MaxInterleaveFactor = 4;
95     PrefFunctionLogAlignment = 4;
96     break;
97   case CortexA65:
98     PrefFunctionLogAlignment = 3;
99     break;
100   case CortexA72:
101   case CortexA73:
102   case CortexA75:
103   case CortexA76:
104   case CortexA77:
105     PrefFunctionLogAlignment = 4;
106     break;
107   case A64FX:
108     CacheLineSize = 256;
109     PrefFunctionLogAlignment = 5;
110     PrefLoopLogAlignment = 5;
111     break;
112   case AppleA7:
113   case AppleA10:
114   case AppleA11:
115   case AppleA12:
116   case AppleA13:
117     CacheLineSize = 64;
118     PrefetchDistance = 280;
119     MinPrefetchStride = 2048;
120     MaxPrefetchIterationsAhead = 3;
121     break;
122   case ExynosM3:
123     MaxInterleaveFactor = 4;
124     MaxJumpTableSize = 20;
125     PrefFunctionLogAlignment = 5;
126     PrefLoopLogAlignment = 4;
127     break;
128   case Falkor:
129     MaxInterleaveFactor = 4;
130     // FIXME: remove this to enable 64-bit SLP if performance looks good.
131     MinVectorRegisterBitWidth = 128;
132     CacheLineSize = 128;
133     PrefetchDistance = 820;
134     MinPrefetchStride = 2048;
135     MaxPrefetchIterationsAhead = 8;
136     break;
137   case Kryo:
138     MaxInterleaveFactor = 4;
139     VectorInsertExtractBaseCost = 2;
140     CacheLineSize = 128;
141     PrefetchDistance = 740;
142     MinPrefetchStride = 1024;
143     MaxPrefetchIterationsAhead = 11;
144     // FIXME: remove this to enable 64-bit SLP if performance looks good.
145     MinVectorRegisterBitWidth = 128;
146     break;
147   case NeoverseE1:
148     PrefFunctionLogAlignment = 3;
149     break;
150   case NeoverseN1:
151     PrefFunctionLogAlignment = 4;
152     break;
153   case Saphira:
154     MaxInterleaveFactor = 4;
155     // FIXME: remove this to enable 64-bit SLP if performance looks good.
156     MinVectorRegisterBitWidth = 128;
157     break;
158   case ThunderX2T99:
159     CacheLineSize = 64;
160     PrefFunctionLogAlignment = 3;
161     PrefLoopLogAlignment = 2;
162     MaxInterleaveFactor = 4;
163     PrefetchDistance = 128;
164     MinPrefetchStride = 1024;
165     MaxPrefetchIterationsAhead = 4;
166     // FIXME: remove this to enable 64-bit SLP if performance looks good.
167     MinVectorRegisterBitWidth = 128;
168     break;
169   case ThunderX:
170   case ThunderXT88:
171   case ThunderXT81:
172   case ThunderXT83:
173     CacheLineSize = 128;
174     PrefFunctionLogAlignment = 3;
175     PrefLoopLogAlignment = 2;
176     // FIXME: remove this to enable 64-bit SLP if performance looks good.
177     MinVectorRegisterBitWidth = 128;
178     break;
179   case TSV110:
180     CacheLineSize = 64;
181     PrefFunctionLogAlignment = 4;
182     PrefLoopLogAlignment = 2;
183     break;
184   case ThunderX3T110:
185     CacheLineSize = 64;
186     PrefFunctionLogAlignment = 4;
187     PrefLoopLogAlignment = 2;
188     MaxInterleaveFactor = 4;
189     PrefetchDistance = 128;
190     MinPrefetchStride = 1024;
191     MaxPrefetchIterationsAhead = 4;
192     // FIXME: remove this to enable 64-bit SLP if performance looks good.
193     MinVectorRegisterBitWidth = 128;
194     break;
195   }
196 }
197 
198 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
199                                    const std::string &FS,
200                                    const TargetMachine &TM, bool LittleEndian)
201     : AArch64GenSubtargetInfo(TT, CPU, FS),
202       ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
203       CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
204       IsLittle(LittleEndian),
205       TargetTriple(TT), FrameLowering(),
206       InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(),
207       TLInfo(TM, *this) {
208   if (AArch64::isX18ReservedByDefault(TT))
209     ReserveXRegister.set(18);
210 
211   CallLoweringInfo.reset(new AArch64CallLowering(*getTargetLowering()));
212   InlineAsmLoweringInfo.reset(new InlineAsmLowering(getTargetLowering()));
213   Legalizer.reset(new AArch64LegalizerInfo(*this));
214 
215   auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
216 
217   // FIXME: At this point, we can't rely on Subtarget having RBI.
218   // It's awkward to mix passing RBI and the Subtarget; should we pass
219   // TII/TRI as well?
220   InstSelector.reset(createAArch64InstructionSelector(
221       *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
222 
223   RegBankInfo.reset(RBI);
224 }
225 
226 const CallLowering *AArch64Subtarget::getCallLowering() const {
227   return CallLoweringInfo.get();
228 }
229 
230 const InlineAsmLowering *AArch64Subtarget::getInlineAsmLowering() const {
231   return InlineAsmLoweringInfo.get();
232 }
233 
234 InstructionSelector *AArch64Subtarget::getInstructionSelector() const {
235   return InstSelector.get();
236 }
237 
238 const LegalizerInfo *AArch64Subtarget::getLegalizerInfo() const {
239   return Legalizer.get();
240 }
241 
242 const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
243   return RegBankInfo.get();
244 }
245 
246 /// Find the target operand flags that describe how a global value should be
247 /// referenced for the current subtarget.
248 unsigned
249 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
250                                           const TargetMachine &TM) const {
251   // MachO large model always goes via a GOT, simply to get a single 8-byte
252   // absolute relocation on all global addresses.
253   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
254     return AArch64II::MO_GOT;
255 
256   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) {
257     if (GV->hasDLLImportStorageClass())
258       return AArch64II::MO_GOT | AArch64II::MO_DLLIMPORT;
259     if (getTargetTriple().isOSWindows())
260       return AArch64II::MO_GOT | AArch64II::MO_COFFSTUB;
261     return AArch64II::MO_GOT;
262   }
263 
264   // The small code model's direct accesses use ADRP, which cannot
265   // necessarily produce the value 0 (if the code is above 4GB).
266   // Same for the tiny code model, where we have a pc relative LDR.
267   if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&
268       GV->hasExternalWeakLinkage())
269     return AArch64II::MO_GOT;
270 
271   // References to tagged globals are marked with MO_NC | MO_TAGGED to indicate
272   // that their nominal addresses are tagged and outside of the code model. In
273   // AArch64ExpandPseudo::expandMI we emit an additional instruction to set the
274   // tag if necessary based on MO_TAGGED.
275   if (AllowTaggedGlobals && !isa<FunctionType>(GV->getValueType()))
276     return AArch64II::MO_NC | AArch64II::MO_TAGGED;
277 
278   return AArch64II::MO_NO_FLAG;
279 }
280 
281 unsigned AArch64Subtarget::classifyGlobalFunctionReference(
282     const GlobalValue *GV, const TargetMachine &TM) const {
283   // MachO large model always goes via a GOT, because we don't have the
284   // relocations available to do anything else..
285   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
286       !GV->hasInternalLinkage())
287     return AArch64II::MO_GOT;
288 
289   // NonLazyBind goes via GOT unless we know it's available locally.
290   auto *F = dyn_cast<Function>(GV);
291   if (UseNonLazyBind && F && F->hasFnAttribute(Attribute::NonLazyBind) &&
292       !TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
293     return AArch64II::MO_GOT;
294 
295   // Use ClassifyGlobalReference for setting MO_DLLIMPORT/MO_COFFSTUB.
296   if (getTargetTriple().isOSWindows())
297     return ClassifyGlobalReference(GV, TM);
298 
299   return AArch64II::MO_NO_FLAG;
300 }
301 
302 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
303                                            unsigned NumRegionInstrs) const {
304   // LNT run (at least on Cyclone) showed reasonably significant gains for
305   // bi-directional scheduling. 253.perlbmk.
306   Policy.OnlyTopDown = false;
307   Policy.OnlyBottomUp = false;
308   // Enabling or Disabling the latency heuristic is a close call: It seems to
309   // help nearly no benchmark on out-of-order architectures, on the other hand
310   // it regresses register pressure on a few benchmarking.
311   Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
312 }
313 
314 bool AArch64Subtarget::enableEarlyIfConversion() const {
315   return EnableEarlyIfConvert;
316 }
317 
318 bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
319   if (!UseAddressTopByteIgnored)
320     return false;
321 
322   if (TargetTriple.isiOS()) {
323     unsigned Major, Minor, Micro;
324     TargetTriple.getiOSVersion(Major, Minor, Micro);
325     return Major >= 8;
326   }
327 
328   return false;
329 }
330 
331 std::unique_ptr<PBQPRAConstraint>
332 AArch64Subtarget::getCustomPBQPConstraints() const {
333   return balanceFPOps() ? std::make_unique<A57ChainingConstraint>() : nullptr;
334 }
335 
336 void AArch64Subtarget::mirFileLoaded(MachineFunction &MF) const {
337   // We usually compute max call frame size after ISel. Do the computation now
338   // if the .mir file didn't specify it. Note that this will probably give you
339   // bogus values after PEI has eliminated the callframe setup/destroy pseudo
340   // instructions, specify explicitly if you need it to be correct.
341   MachineFrameInfo &MFI = MF.getFrameInfo();
342   if (!MFI.isMaxCallFrameSizeComputed())
343     MFI.computeMaxCallFrameSize(MF);
344 }
345 
346 unsigned AArch64Subtarget::getMaxSVEVectorSizeInBits() const {
347   assert(HasSVE && "Tried to get SVE vector length without SVE support!");
348   assert(SVEVectorBitsMax % 128 == 0 &&
349          "SVE requires vector length in multiples of 128!");
350   assert((SVEVectorBitsMax >= SVEVectorBitsMin || SVEVectorBitsMax == 0) &&
351          "Minimum SVE vector size should not be larger than its maximum!");
352   if (SVEVectorBitsMax == 0)
353     return 0;
354   return (std::max(SVEVectorBitsMin, SVEVectorBitsMax) / 128) * 128;
355 }
356 
357 unsigned AArch64Subtarget::getMinSVEVectorSizeInBits() const {
358   assert(HasSVE && "Tried to get SVE vector length without SVE support!");
359   assert(SVEVectorBitsMin % 128 == 0 &&
360          "SVE requires vector length in multiples of 128!");
361   assert((SVEVectorBitsMax >= SVEVectorBitsMin || SVEVectorBitsMax == 0) &&
362          "Minimum SVE vector size should not be larger than its maximum!");
363   if (SVEVectorBitsMax == 0)
364     return (SVEVectorBitsMin / 128) * 128;
365   return (std::min(SVEVectorBitsMin, SVEVectorBitsMax) / 128) * 128;
366 }
367