1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the AArch64 specific subclass of TargetSubtarget. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "AArch64InstrInfo.h" 15 #include "AArch64PBQPRegAlloc.h" 16 #include "AArch64Subtarget.h" 17 #include "llvm/CodeGen/MachineScheduler.h" 18 #include "llvm/IR/GlobalValue.h" 19 #include "llvm/Support/TargetRegistry.h" 20 21 using namespace llvm; 22 23 #define DEBUG_TYPE "aarch64-subtarget" 24 25 #define GET_SUBTARGETINFO_CTOR 26 #define GET_SUBTARGETINFO_TARGET_DESC 27 #include "AArch64GenSubtargetInfo.inc" 28 29 static cl::opt<bool> 30 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if " 31 "converter pass"), cl::init(true), cl::Hidden); 32 33 // If OS supports TBI, use this flag to enable it. 34 static cl::opt<bool> 35 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of " 36 "an address is ignored"), cl::init(false), cl::Hidden); 37 38 AArch64Subtarget & 39 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS) { 40 // Determine default and user-specified characteristics 41 42 if (CPUString.empty()) 43 CPUString = "generic"; 44 45 ParseSubtargetFeatures(CPUString, FS); 46 return *this; 47 } 48 49 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU, 50 const std::string &FS, 51 const TargetMachine &TM, bool LittleEndian) 52 : AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others), 53 HasV8_1aOps(false), HasV8_2aOps(false), HasFPARMv8(false), HasNEON(false), 54 HasCrypto(false), HasCRC(false), HasPerfMon(false), HasFullFP16(false), 55 HasZeroCycleRegMove(false), HasZeroCycleZeroing(false), 56 StrictAlign(false), ReserveX18(TT.isOSDarwin()), IsLittle(LittleEndian), 57 CPUString(CPU), TargetTriple(TT), FrameLowering(), 58 InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(), 59 TLInfo(TM, *this), GISel() {} 60 61 const CallLowering *AArch64Subtarget::getCallLowering() const { 62 assert(GISel && "Access to GlobalISel APIs not set"); 63 return GISel->getCallLowering(); 64 } 65 66 const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const { 67 assert(GISel && "Access to GlobalISel APIs not set"); 68 return GISel->getRegBankInfo(); 69 } 70 71 /// ClassifyGlobalReference - Find the target operand flags that describe 72 /// how a global value should be referenced for the current subtarget. 73 unsigned char 74 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV, 75 const TargetMachine &TM) const { 76 bool isDef = GV->isStrongDefinitionForLinker(); 77 78 // MachO large model always goes via a GOT, simply to get a single 8-byte 79 // absolute relocation on all global addresses. 80 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO()) 81 return AArch64II::MO_GOT; 82 83 // The small code mode's direct accesses use ADRP, which cannot necessarily 84 // produce the value 0 (if the code is above 4GB). 85 if (TM.getCodeModel() == CodeModel::Small && GV->hasExternalWeakLinkage()) { 86 // In PIC mode use the GOT, but in absolute mode use a constant pool load. 87 if (TM.getRelocationModel() == Reloc::Static) 88 return AArch64II::MO_CONSTPOOL; 89 else 90 return AArch64II::MO_GOT; 91 } 92 93 // If symbol visibility is hidden, the extra load is not needed if 94 // the symbol is definitely defined in the current translation unit. 95 96 // The handling of non-hidden symbols in PIC mode is rather target-dependent: 97 // + On MachO, if the symbol is defined in this module the GOT can be 98 // skipped. 99 // + On ELF, the R_AARCH64_COPY relocation means that even symbols actually 100 // defined could end up in unexpected places. Use a GOT. 101 if (TM.getRelocationModel() != Reloc::Static && GV->hasDefaultVisibility()) { 102 if (isTargetMachO()) 103 return isDef ? AArch64II::MO_NO_FLAG : AArch64II::MO_GOT; 104 else 105 // No need to go through the GOT for local symbols on ELF. 106 return GV->hasLocalLinkage() ? AArch64II::MO_NO_FLAG : AArch64II::MO_GOT; 107 } 108 109 return AArch64II::MO_NO_FLAG; 110 } 111 112 /// This function returns the name of a function which has an interface 113 /// like the non-standard bzero function, if such a function exists on 114 /// the current subtarget and it is considered prefereable over 115 /// memset with zero passed as the second argument. Otherwise it 116 /// returns null. 117 const char *AArch64Subtarget::getBZeroEntry() const { 118 // Prefer bzero on Darwin only. 119 if(isTargetDarwin()) 120 return "bzero"; 121 122 return nullptr; 123 } 124 125 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, 126 MachineInstr *begin, MachineInstr *end, 127 unsigned NumRegionInstrs) const { 128 // LNT run (at least on Cyclone) showed reasonably significant gains for 129 // bi-directional scheduling. 253.perlbmk. 130 Policy.OnlyTopDown = false; 131 Policy.OnlyBottomUp = false; 132 // Enabling or Disabling the latency heuristic is a close call: It seems to 133 // help nearly no benchmark on out-of-order architectures, on the other hand 134 // it regresses register pressure on a few benchmarking. 135 if (isCyclone()) 136 Policy.DisableLatencyHeuristic = true; 137 } 138 139 bool AArch64Subtarget::enableEarlyIfConversion() const { 140 return EnableEarlyIfConvert; 141 } 142 143 bool AArch64Subtarget::supportsAddressTopByteIgnored() const { 144 if (!UseAddressTopByteIgnored) 145 return false; 146 147 if (TargetTriple.isiOS()) { 148 unsigned Major, Minor, Micro; 149 TargetTriple.getiOSVersion(Major, Minor, Micro); 150 return Major >= 8; 151 } 152 153 return false; 154 } 155 156 std::unique_ptr<PBQPRAConstraint> 157 AArch64Subtarget::getCustomPBQPConstraints() const { 158 if (!isCortexA57()) 159 return nullptr; 160 161 return llvm::make_unique<A57ChainingConstraint>(); 162 } 163