1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the AArch64 specific subclass of TargetSubtarget. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "AArch64InstrInfo.h" 15 #include "AArch64PBQPRegAlloc.h" 16 #include "AArch64Subtarget.h" 17 #include "llvm/ADT/SmallVector.h" 18 #include "llvm/CodeGen/MachineScheduler.h" 19 #include "llvm/IR/GlobalValue.h" 20 #include "llvm/Support/TargetRegistry.h" 21 22 using namespace llvm; 23 24 #define DEBUG_TYPE "aarch64-subtarget" 25 26 #define GET_SUBTARGETINFO_CTOR 27 #define GET_SUBTARGETINFO_TARGET_DESC 28 #include "AArch64GenSubtargetInfo.inc" 29 30 static cl::opt<bool> 31 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if " 32 "converter pass"), cl::init(true), cl::Hidden); 33 34 // If OS supports TBI, use this flag to enable it. 35 static cl::opt<bool> 36 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of " 37 "an address is ignored"), cl::init(false), cl::Hidden); 38 39 AArch64Subtarget & 40 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS) { 41 // Determine default and user-specified characteristics 42 43 if (CPUString.empty()) 44 CPUString = "generic"; 45 46 ParseSubtargetFeatures(CPUString, FS); 47 return *this; 48 } 49 50 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU, 51 const std::string &FS, 52 const TargetMachine &TM, bool LittleEndian) 53 : AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others), 54 HasV8_1aOps(false), HasV8_2aOps(false), HasFPARMv8(false), HasNEON(false), 55 HasCrypto(false), HasCRC(false), HasPerfMon(false), HasFullFP16(false), 56 HasZeroCycleRegMove(false), HasZeroCycleZeroing(false), 57 StrictAlign(false), ReserveX18(TT.isOSDarwin()), IsLittle(LittleEndian), 58 CPUString(CPU), TargetTriple(TT), FrameLowering(), 59 InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(), 60 TLInfo(TM, *this), CallLoweringInfo(nullptr) {} 61 62 const CallLowering *AArch64Subtarget::getCallLowering() const { 63 if (!CallLoweringInfo) 64 CallLoweringInfo.reset(new AArch64CallLowering(TLInfo)); 65 return CallLoweringInfo.get(); 66 } 67 68 /// ClassifyGlobalReference - Find the target operand flags that describe 69 /// how a global value should be referenced for the current subtarget. 70 unsigned char 71 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV, 72 const TargetMachine &TM) const { 73 bool isDef = GV->isStrongDefinitionForLinker(); 74 75 // MachO large model always goes via a GOT, simply to get a single 8-byte 76 // absolute relocation on all global addresses. 77 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO()) 78 return AArch64II::MO_GOT; 79 80 // The small code mode's direct accesses use ADRP, which cannot necessarily 81 // produce the value 0 (if the code is above 4GB). 82 if (TM.getCodeModel() == CodeModel::Small && GV->hasExternalWeakLinkage()) { 83 // In PIC mode use the GOT, but in absolute mode use a constant pool load. 84 if (TM.getRelocationModel() == Reloc::Static) 85 return AArch64II::MO_CONSTPOOL; 86 else 87 return AArch64II::MO_GOT; 88 } 89 90 // If symbol visibility is hidden, the extra load is not needed if 91 // the symbol is definitely defined in the current translation unit. 92 93 // The handling of non-hidden symbols in PIC mode is rather target-dependent: 94 // + On MachO, if the symbol is defined in this module the GOT can be 95 // skipped. 96 // + On ELF, the R_AARCH64_COPY relocation means that even symbols actually 97 // defined could end up in unexpected places. Use a GOT. 98 if (TM.getRelocationModel() != Reloc::Static && GV->hasDefaultVisibility()) { 99 if (isTargetMachO()) 100 return isDef ? AArch64II::MO_NO_FLAG : AArch64II::MO_GOT; 101 else 102 // No need to go through the GOT for local symbols on ELF. 103 return GV->hasLocalLinkage() ? AArch64II::MO_NO_FLAG : AArch64II::MO_GOT; 104 } 105 106 return AArch64II::MO_NO_FLAG; 107 } 108 109 /// This function returns the name of a function which has an interface 110 /// like the non-standard bzero function, if such a function exists on 111 /// the current subtarget and it is considered prefereable over 112 /// memset with zero passed as the second argument. Otherwise it 113 /// returns null. 114 const char *AArch64Subtarget::getBZeroEntry() const { 115 // Prefer bzero on Darwin only. 116 if(isTargetDarwin()) 117 return "bzero"; 118 119 return nullptr; 120 } 121 122 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, 123 MachineInstr *begin, MachineInstr *end, 124 unsigned NumRegionInstrs) const { 125 // LNT run (at least on Cyclone) showed reasonably significant gains for 126 // bi-directional scheduling. 253.perlbmk. 127 Policy.OnlyTopDown = false; 128 Policy.OnlyBottomUp = false; 129 // Enabling or Disabling the latency heuristic is a close call: It seems to 130 // help nearly no benchmark on out-of-order architectures, on the other hand 131 // it regresses register pressure on a few benchmarking. 132 if (isCyclone()) 133 Policy.DisableLatencyHeuristic = true; 134 } 135 136 bool AArch64Subtarget::enableEarlyIfConversion() const { 137 return EnableEarlyIfConvert; 138 } 139 140 bool AArch64Subtarget::supportsAddressTopByteIgnored() const { 141 if (!UseAddressTopByteIgnored) 142 return false; 143 144 if (TargetTriple.isiOS()) { 145 unsigned Major, Minor, Micro; 146 TargetTriple.getiOSVersion(Major, Minor, Micro); 147 return Major >= 8; 148 } 149 150 return false; 151 } 152 153 std::unique_ptr<PBQPRAConstraint> 154 AArch64Subtarget::getCustomPBQPConstraints() const { 155 if (!isCortexA57()) 156 return nullptr; 157 158 return llvm::make_unique<A57ChainingConstraint>(); 159 } 160