1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the AArch64 specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64Subtarget.h"
14 
15 #include "AArch64.h"
16 #include "AArch64InstrInfo.h"
17 #include "AArch64PBQPRegAlloc.h"
18 #include "AArch64TargetMachine.h"
19 #include "GISel/AArch64CallLowering.h"
20 #include "GISel/AArch64LegalizerInfo.h"
21 #include "GISel/AArch64RegisterBankInfo.h"
22 #include "MCTargetDesc/AArch64AddressingModes.h"
23 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
24 #include "llvm/CodeGen/MachineScheduler.h"
25 #include "llvm/IR/GlobalValue.h"
26 #include "llvm/Support/TargetParser.h"
27 
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "aarch64-subtarget"
31 
32 #define GET_SUBTARGETINFO_CTOR
33 #define GET_SUBTARGETINFO_TARGET_DESC
34 #include "AArch64GenSubtargetInfo.inc"
35 
36 static cl::opt<bool>
37 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
38                      "converter pass"), cl::init(true), cl::Hidden);
39 
40 // If OS supports TBI, use this flag to enable it.
41 static cl::opt<bool>
42 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
43                          "an address is ignored"), cl::init(false), cl::Hidden);
44 
45 static cl::opt<bool>
46     UseNonLazyBind("aarch64-enable-nonlazybind",
47                    cl::desc("Call nonlazybind functions via direct GOT load"),
48                    cl::init(false), cl::Hidden);
49 
50 static cl::opt<unsigned> SVEVectorBitsMax(
51     "aarch64-sve-vector-bits-max",
52     cl::desc("Assume SVE vector registers are at most this big, "
53              "with zero meaning no maximum size is assumed."),
54     cl::init(0), cl::Hidden);
55 
56 static cl::opt<unsigned> SVEVectorBitsMin(
57     "aarch64-sve-vector-bits-min",
58     cl::desc("Assume SVE vector registers are at least this big, "
59              "with zero meaning no minimum size is assumed."),
60     cl::init(0), cl::Hidden);
61 
62 AArch64Subtarget &
63 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS,
64                                                   StringRef CPUString) {
65   // Determine default and user-specified characteristics
66 
67   if (CPUString.empty())
68     CPUString = "generic";
69 
70   ParseSubtargetFeatures(CPUString, /*TuneCPU*/ CPUString, FS);
71   initializeProperties();
72 
73   return *this;
74 }
75 
76 void AArch64Subtarget::initializeProperties() {
77   // Initialize CPU specific properties. We should add a tablegen feature for
78   // this in the future so we can specify it together with the subtarget
79   // features.
80   switch (ARMProcFamily) {
81   case Others:
82     break;
83   case Carmel:
84     CacheLineSize = 64;
85     break;
86   case CortexA35:
87     break;
88   case CortexA53:
89     PrefFunctionLogAlignment = 3;
90     break;
91   case CortexA55:
92     break;
93   case CortexA57:
94     MaxInterleaveFactor = 4;
95     PrefFunctionLogAlignment = 4;
96     break;
97   case CortexA65:
98     PrefFunctionLogAlignment = 3;
99     break;
100   case CortexA72:
101   case CortexA73:
102   case CortexA75:
103   case CortexA76:
104   case CortexA77:
105   case CortexA78:
106   case CortexR82:
107   case CortexX1:
108     PrefFunctionLogAlignment = 4;
109     break;
110   case A64FX:
111     CacheLineSize = 256;
112     PrefFunctionLogAlignment = 5;
113     PrefLoopLogAlignment = 5;
114     break;
115   case AppleA7:
116   case AppleA10:
117   case AppleA11:
118   case AppleA12:
119   case AppleA13:
120     CacheLineSize = 64;
121     PrefetchDistance = 280;
122     MinPrefetchStride = 2048;
123     MaxPrefetchIterationsAhead = 3;
124     break;
125   case ExynosM3:
126     MaxInterleaveFactor = 4;
127     MaxJumpTableSize = 20;
128     PrefFunctionLogAlignment = 5;
129     PrefLoopLogAlignment = 4;
130     break;
131   case Falkor:
132     MaxInterleaveFactor = 4;
133     // FIXME: remove this to enable 64-bit SLP if performance looks good.
134     MinVectorRegisterBitWidth = 128;
135     CacheLineSize = 128;
136     PrefetchDistance = 820;
137     MinPrefetchStride = 2048;
138     MaxPrefetchIterationsAhead = 8;
139     break;
140   case Kryo:
141     MaxInterleaveFactor = 4;
142     VectorInsertExtractBaseCost = 2;
143     CacheLineSize = 128;
144     PrefetchDistance = 740;
145     MinPrefetchStride = 1024;
146     MaxPrefetchIterationsAhead = 11;
147     // FIXME: remove this to enable 64-bit SLP if performance looks good.
148     MinVectorRegisterBitWidth = 128;
149     break;
150   case NeoverseE1:
151     PrefFunctionLogAlignment = 3;
152     break;
153   case NeoverseN1:
154   case NeoverseV1:
155     PrefFunctionLogAlignment = 4;
156     break;
157   case Saphira:
158     MaxInterleaveFactor = 4;
159     // FIXME: remove this to enable 64-bit SLP if performance looks good.
160     MinVectorRegisterBitWidth = 128;
161     break;
162   case ThunderX2T99:
163     CacheLineSize = 64;
164     PrefFunctionLogAlignment = 3;
165     PrefLoopLogAlignment = 2;
166     MaxInterleaveFactor = 4;
167     PrefetchDistance = 128;
168     MinPrefetchStride = 1024;
169     MaxPrefetchIterationsAhead = 4;
170     // FIXME: remove this to enable 64-bit SLP if performance looks good.
171     MinVectorRegisterBitWidth = 128;
172     break;
173   case ThunderX:
174   case ThunderXT88:
175   case ThunderXT81:
176   case ThunderXT83:
177     CacheLineSize = 128;
178     PrefFunctionLogAlignment = 3;
179     PrefLoopLogAlignment = 2;
180     // FIXME: remove this to enable 64-bit SLP if performance looks good.
181     MinVectorRegisterBitWidth = 128;
182     break;
183   case TSV110:
184     CacheLineSize = 64;
185     PrefFunctionLogAlignment = 4;
186     PrefLoopLogAlignment = 2;
187     break;
188   case ThunderX3T110:
189     CacheLineSize = 64;
190     PrefFunctionLogAlignment = 4;
191     PrefLoopLogAlignment = 2;
192     MaxInterleaveFactor = 4;
193     PrefetchDistance = 128;
194     MinPrefetchStride = 1024;
195     MaxPrefetchIterationsAhead = 4;
196     // FIXME: remove this to enable 64-bit SLP if performance looks good.
197     MinVectorRegisterBitWidth = 128;
198     break;
199   }
200 }
201 
202 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
203                                    const std::string &FS,
204                                    const TargetMachine &TM, bool LittleEndian)
205     : AArch64GenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
206       ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
207       CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
208       IsLittle(LittleEndian),
209       TargetTriple(TT), FrameLowering(),
210       InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(),
211       TLInfo(TM, *this) {
212   if (AArch64::isX18ReservedByDefault(TT))
213     ReserveXRegister.set(18);
214 
215   CallLoweringInfo.reset(new AArch64CallLowering(*getTargetLowering()));
216   InlineAsmLoweringInfo.reset(new InlineAsmLowering(getTargetLowering()));
217   Legalizer.reset(new AArch64LegalizerInfo(*this));
218 
219   auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
220 
221   // FIXME: At this point, we can't rely on Subtarget having RBI.
222   // It's awkward to mix passing RBI and the Subtarget; should we pass
223   // TII/TRI as well?
224   InstSelector.reset(createAArch64InstructionSelector(
225       *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
226 
227   RegBankInfo.reset(RBI);
228 }
229 
230 const CallLowering *AArch64Subtarget::getCallLowering() const {
231   return CallLoweringInfo.get();
232 }
233 
234 const InlineAsmLowering *AArch64Subtarget::getInlineAsmLowering() const {
235   return InlineAsmLoweringInfo.get();
236 }
237 
238 InstructionSelector *AArch64Subtarget::getInstructionSelector() const {
239   return InstSelector.get();
240 }
241 
242 const LegalizerInfo *AArch64Subtarget::getLegalizerInfo() const {
243   return Legalizer.get();
244 }
245 
246 const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
247   return RegBankInfo.get();
248 }
249 
250 /// Find the target operand flags that describe how a global value should be
251 /// referenced for the current subtarget.
252 unsigned
253 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
254                                           const TargetMachine &TM) const {
255   // MachO large model always goes via a GOT, simply to get a single 8-byte
256   // absolute relocation on all global addresses.
257   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
258     return AArch64II::MO_GOT;
259 
260   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) {
261     if (GV->hasDLLImportStorageClass())
262       return AArch64II::MO_GOT | AArch64II::MO_DLLIMPORT;
263     if (getTargetTriple().isOSWindows())
264       return AArch64II::MO_GOT | AArch64II::MO_COFFSTUB;
265     return AArch64II::MO_GOT;
266   }
267 
268   // The small code model's direct accesses use ADRP, which cannot
269   // necessarily produce the value 0 (if the code is above 4GB).
270   // Same for the tiny code model, where we have a pc relative LDR.
271   if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&
272       GV->hasExternalWeakLinkage())
273     return AArch64II::MO_GOT;
274 
275   // References to tagged globals are marked with MO_NC | MO_TAGGED to indicate
276   // that their nominal addresses are tagged and outside of the code model. In
277   // AArch64ExpandPseudo::expandMI we emit an additional instruction to set the
278   // tag if necessary based on MO_TAGGED.
279   if (AllowTaggedGlobals && !isa<FunctionType>(GV->getValueType()))
280     return AArch64II::MO_NC | AArch64II::MO_TAGGED;
281 
282   return AArch64II::MO_NO_FLAG;
283 }
284 
285 unsigned AArch64Subtarget::classifyGlobalFunctionReference(
286     const GlobalValue *GV, const TargetMachine &TM) const {
287   // MachO large model always goes via a GOT, because we don't have the
288   // relocations available to do anything else..
289   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
290       !GV->hasInternalLinkage())
291     return AArch64II::MO_GOT;
292 
293   // NonLazyBind goes via GOT unless we know it's available locally.
294   auto *F = dyn_cast<Function>(GV);
295   if (UseNonLazyBind && F && F->hasFnAttribute(Attribute::NonLazyBind) &&
296       !TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
297     return AArch64II::MO_GOT;
298 
299   // Use ClassifyGlobalReference for setting MO_DLLIMPORT/MO_COFFSTUB.
300   if (getTargetTriple().isOSWindows())
301     return ClassifyGlobalReference(GV, TM);
302 
303   return AArch64II::MO_NO_FLAG;
304 }
305 
306 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
307                                            unsigned NumRegionInstrs) const {
308   // LNT run (at least on Cyclone) showed reasonably significant gains for
309   // bi-directional scheduling. 253.perlbmk.
310   Policy.OnlyTopDown = false;
311   Policy.OnlyBottomUp = false;
312   // Enabling or Disabling the latency heuristic is a close call: It seems to
313   // help nearly no benchmark on out-of-order architectures, on the other hand
314   // it regresses register pressure on a few benchmarking.
315   Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
316 }
317 
318 bool AArch64Subtarget::enableEarlyIfConversion() const {
319   return EnableEarlyIfConvert;
320 }
321 
322 bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
323   if (!UseAddressTopByteIgnored)
324     return false;
325 
326   if (TargetTriple.isiOS()) {
327     unsigned Major, Minor, Micro;
328     TargetTriple.getiOSVersion(Major, Minor, Micro);
329     return Major >= 8;
330   }
331 
332   return false;
333 }
334 
335 std::unique_ptr<PBQPRAConstraint>
336 AArch64Subtarget::getCustomPBQPConstraints() const {
337   return balanceFPOps() ? std::make_unique<A57ChainingConstraint>() : nullptr;
338 }
339 
340 void AArch64Subtarget::mirFileLoaded(MachineFunction &MF) const {
341   // We usually compute max call frame size after ISel. Do the computation now
342   // if the .mir file didn't specify it. Note that this will probably give you
343   // bogus values after PEI has eliminated the callframe setup/destroy pseudo
344   // instructions, specify explicitly if you need it to be correct.
345   MachineFrameInfo &MFI = MF.getFrameInfo();
346   if (!MFI.isMaxCallFrameSizeComputed())
347     MFI.computeMaxCallFrameSize(MF);
348 }
349 
350 unsigned AArch64Subtarget::getMaxSVEVectorSizeInBits() const {
351   assert(HasSVE && "Tried to get SVE vector length without SVE support!");
352   assert(SVEVectorBitsMax % 128 == 0 &&
353          "SVE requires vector length in multiples of 128!");
354   assert((SVEVectorBitsMax >= SVEVectorBitsMin || SVEVectorBitsMax == 0) &&
355          "Minimum SVE vector size should not be larger than its maximum!");
356   if (SVEVectorBitsMax == 0)
357     return 0;
358   return (std::max(SVEVectorBitsMin, SVEVectorBitsMax) / 128) * 128;
359 }
360 
361 unsigned AArch64Subtarget::getMinSVEVectorSizeInBits() const {
362   assert(HasSVE && "Tried to get SVE vector length without SVE support!");
363   assert(SVEVectorBitsMin % 128 == 0 &&
364          "SVE requires vector length in multiples of 128!");
365   assert((SVEVectorBitsMax >= SVEVectorBitsMin || SVEVectorBitsMax == 0) &&
366          "Minimum SVE vector size should not be larger than its maximum!");
367   if (SVEVectorBitsMax == 0)
368     return (SVEVectorBitsMin / 128) * 128;
369   return (std::min(SVEVectorBitsMin, SVEVectorBitsMax) / 128) * 128;
370 }
371 
372 bool AArch64Subtarget::useSVEForFixedLengthVectors() const {
373   // Prefer NEON unless larger SVE registers are available.
374   return hasSVE() && getMinSVEVectorSizeInBits() >= 256;
375 }
376