1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the AArch64 specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64Subtarget.h"
14 
15 #include "AArch64.h"
16 #include "AArch64CallLowering.h"
17 #include "AArch64InstrInfo.h"
18 #include "AArch64LegalizerInfo.h"
19 #include "AArch64PBQPRegAlloc.h"
20 #include "AArch64RegisterBankInfo.h"
21 #include "AArch64TargetMachine.h"
22 #include "MCTargetDesc/AArch64AddressingModes.h"
23 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
24 #include "llvm/CodeGen/MachineScheduler.h"
25 #include "llvm/IR/GlobalValue.h"
26 #include "llvm/Support/TargetParser.h"
27 
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "aarch64-subtarget"
31 
32 #define GET_SUBTARGETINFO_CTOR
33 #define GET_SUBTARGETINFO_TARGET_DESC
34 #include "AArch64GenSubtargetInfo.inc"
35 
36 static cl::opt<bool>
37 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
38                      "converter pass"), cl::init(true), cl::Hidden);
39 
40 // If OS supports TBI, use this flag to enable it.
41 static cl::opt<bool>
42 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
43                          "an address is ignored"), cl::init(false), cl::Hidden);
44 
45 static cl::opt<bool>
46     UseNonLazyBind("aarch64-enable-nonlazybind",
47                    cl::desc("Call nonlazybind functions via direct GOT load"),
48                    cl::init(false), cl::Hidden);
49 
50 AArch64Subtarget &
51 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS,
52                                                   StringRef CPUString) {
53   // Determine default and user-specified characteristics
54 
55   if (CPUString.empty())
56     CPUString = "generic";
57 
58   ParseSubtargetFeatures(CPUString, FS);
59   initializeProperties();
60 
61   return *this;
62 }
63 
64 void AArch64Subtarget::initializeProperties() {
65   // Initialize CPU specific properties. We should add a tablegen feature for
66   // this in the future so we can specify it together with the subtarget
67   // features.
68   switch (ARMProcFamily) {
69   case Others:
70     break;
71   case Carmel:
72     CacheLineSize = 64;
73     break;
74   case CortexA35:
75     break;
76   case CortexA53:
77     PrefFunctionLogAlignment = 3;
78     break;
79   case CortexA55:
80     break;
81   case CortexA57:
82     MaxInterleaveFactor = 4;
83     PrefFunctionLogAlignment = 4;
84     break;
85   case CortexA65:
86     PrefFunctionLogAlignment = 3;
87     break;
88   case CortexA72:
89   case CortexA73:
90   case CortexA75:
91   case CortexA76:
92     PrefFunctionLogAlignment = 4;
93     break;
94   case A64FX:
95     CacheLineSize = 256;
96     PrefFunctionLogAlignment = 5;
97     PrefLoopLogAlignment = 5;
98     break;
99   case AppleA7:
100   case AppleA10:
101   case AppleA11:
102   case AppleA12:
103   case AppleA13:
104     CacheLineSize = 64;
105     PrefetchDistance = 280;
106     MinPrefetchStride = 2048;
107     MaxPrefetchIterationsAhead = 3;
108     break;
109   case ExynosM3:
110     MaxInterleaveFactor = 4;
111     MaxJumpTableSize = 20;
112     PrefFunctionLogAlignment = 5;
113     PrefLoopLogAlignment = 4;
114     break;
115   case Falkor:
116     MaxInterleaveFactor = 4;
117     // FIXME: remove this to enable 64-bit SLP if performance looks good.
118     MinVectorRegisterBitWidth = 128;
119     CacheLineSize = 128;
120     PrefetchDistance = 820;
121     MinPrefetchStride = 2048;
122     MaxPrefetchIterationsAhead = 8;
123     break;
124   case Kryo:
125     MaxInterleaveFactor = 4;
126     VectorInsertExtractBaseCost = 2;
127     CacheLineSize = 128;
128     PrefetchDistance = 740;
129     MinPrefetchStride = 1024;
130     MaxPrefetchIterationsAhead = 11;
131     // FIXME: remove this to enable 64-bit SLP if performance looks good.
132     MinVectorRegisterBitWidth = 128;
133     break;
134   case NeoverseE1:
135     PrefFunctionLogAlignment = 3;
136     break;
137   case NeoverseN1:
138     PrefFunctionLogAlignment = 4;
139     break;
140   case Saphira:
141     MaxInterleaveFactor = 4;
142     // FIXME: remove this to enable 64-bit SLP if performance looks good.
143     MinVectorRegisterBitWidth = 128;
144     break;
145   case ThunderX2T99:
146     CacheLineSize = 64;
147     PrefFunctionLogAlignment = 3;
148     PrefLoopLogAlignment = 2;
149     MaxInterleaveFactor = 4;
150     PrefetchDistance = 128;
151     MinPrefetchStride = 1024;
152     MaxPrefetchIterationsAhead = 4;
153     // FIXME: remove this to enable 64-bit SLP if performance looks good.
154     MinVectorRegisterBitWidth = 128;
155     break;
156   case ThunderX:
157   case ThunderXT88:
158   case ThunderXT81:
159   case ThunderXT83:
160     CacheLineSize = 128;
161     PrefFunctionLogAlignment = 3;
162     PrefLoopLogAlignment = 2;
163     // FIXME: remove this to enable 64-bit SLP if performance looks good.
164     MinVectorRegisterBitWidth = 128;
165     break;
166   case TSV110:
167     CacheLineSize = 64;
168     PrefFunctionLogAlignment = 4;
169     PrefLoopLogAlignment = 2;
170     break;
171   }
172 }
173 
174 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
175                                    const std::string &FS,
176                                    const TargetMachine &TM, bool LittleEndian)
177     : AArch64GenSubtargetInfo(TT, CPU, FS),
178       ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
179       CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
180       IsLittle(LittleEndian),
181       TargetTriple(TT), FrameLowering(),
182       InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(),
183       TLInfo(TM, *this) {
184   if (AArch64::isX18ReservedByDefault(TT))
185     ReserveXRegister.set(18);
186 
187   CallLoweringInfo.reset(new AArch64CallLowering(*getTargetLowering()));
188   InlineAsmLoweringInfo.reset(new InlineAsmLowering(getTargetLowering()));
189   Legalizer.reset(new AArch64LegalizerInfo(*this));
190 
191   auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
192 
193   // FIXME: At this point, we can't rely on Subtarget having RBI.
194   // It's awkward to mix passing RBI and the Subtarget; should we pass
195   // TII/TRI as well?
196   InstSelector.reset(createAArch64InstructionSelector(
197       *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
198 
199   RegBankInfo.reset(RBI);
200 }
201 
202 const CallLowering *AArch64Subtarget::getCallLowering() const {
203   return CallLoweringInfo.get();
204 }
205 
206 const InlineAsmLowering *AArch64Subtarget::getInlineAsmLowering() const {
207   return InlineAsmLoweringInfo.get();
208 }
209 
210 InstructionSelector *AArch64Subtarget::getInstructionSelector() const {
211   return InstSelector.get();
212 }
213 
214 const LegalizerInfo *AArch64Subtarget::getLegalizerInfo() const {
215   return Legalizer.get();
216 }
217 
218 const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
219   return RegBankInfo.get();
220 }
221 
222 /// Find the target operand flags that describe how a global value should be
223 /// referenced for the current subtarget.
224 unsigned
225 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
226                                           const TargetMachine &TM) const {
227   // MachO large model always goes via a GOT, simply to get a single 8-byte
228   // absolute relocation on all global addresses.
229   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
230     return AArch64II::MO_GOT;
231 
232   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) {
233     if (GV->hasDLLImportStorageClass())
234       return AArch64II::MO_GOT | AArch64II::MO_DLLIMPORT;
235     if (getTargetTriple().isOSWindows())
236       return AArch64II::MO_GOT | AArch64II::MO_COFFSTUB;
237     return AArch64II::MO_GOT;
238   }
239 
240   // The small code model's direct accesses use ADRP, which cannot
241   // necessarily produce the value 0 (if the code is above 4GB).
242   // Same for the tiny code model, where we have a pc relative LDR.
243   if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&
244       GV->hasExternalWeakLinkage())
245     return AArch64II::MO_GOT;
246 
247   // References to tagged globals are marked with MO_NC | MO_TAGGED to indicate
248   // that their nominal addresses are tagged and outside of the code model. In
249   // AArch64ExpandPseudo::expandMI we emit an additional instruction to set the
250   // tag if necessary based on MO_TAGGED.
251   if (AllowTaggedGlobals && !isa<FunctionType>(GV->getValueType()))
252     return AArch64II::MO_NC | AArch64II::MO_TAGGED;
253 
254   return AArch64II::MO_NO_FLAG;
255 }
256 
257 unsigned AArch64Subtarget::classifyGlobalFunctionReference(
258     const GlobalValue *GV, const TargetMachine &TM) const {
259   // MachO large model always goes via a GOT, because we don't have the
260   // relocations available to do anything else..
261   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
262       !GV->hasInternalLinkage())
263     return AArch64II::MO_GOT;
264 
265   // NonLazyBind goes via GOT unless we know it's available locally.
266   auto *F = dyn_cast<Function>(GV);
267   if (UseNonLazyBind && F && F->hasFnAttribute(Attribute::NonLazyBind) &&
268       !TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
269     return AArch64II::MO_GOT;
270 
271   // Use ClassifyGlobalReference for setting MO_DLLIMPORT/MO_COFFSTUB.
272   if (getTargetTriple().isOSWindows())
273     return ClassifyGlobalReference(GV, TM);
274 
275   return AArch64II::MO_NO_FLAG;
276 }
277 
278 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
279                                            unsigned NumRegionInstrs) const {
280   // LNT run (at least on Cyclone) showed reasonably significant gains for
281   // bi-directional scheduling. 253.perlbmk.
282   Policy.OnlyTopDown = false;
283   Policy.OnlyBottomUp = false;
284   // Enabling or Disabling the latency heuristic is a close call: It seems to
285   // help nearly no benchmark on out-of-order architectures, on the other hand
286   // it regresses register pressure on a few benchmarking.
287   Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
288 }
289 
290 bool AArch64Subtarget::enableEarlyIfConversion() const {
291   return EnableEarlyIfConvert;
292 }
293 
294 bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
295   if (!UseAddressTopByteIgnored)
296     return false;
297 
298   if (TargetTriple.isiOS()) {
299     unsigned Major, Minor, Micro;
300     TargetTriple.getiOSVersion(Major, Minor, Micro);
301     return Major >= 8;
302   }
303 
304   return false;
305 }
306 
307 std::unique_ptr<PBQPRAConstraint>
308 AArch64Subtarget::getCustomPBQPConstraints() const {
309   return balanceFPOps() ? std::make_unique<A57ChainingConstraint>() : nullptr;
310 }
311 
312 void AArch64Subtarget::mirFileLoaded(MachineFunction &MF) const {
313   // We usually compute max call frame size after ISel. Do the computation now
314   // if the .mir file didn't specify it. Note that this will probably give you
315   // bogus values after PEI has eliminated the callframe setup/destroy pseudo
316   // instructions, specify explicitly if you need it to be correct.
317   MachineFrameInfo &MFI = MF.getFrameInfo();
318   if (!MFI.isMaxCallFrameSizeComputed())
319     MFI.computeMaxCallFrameSize(MF);
320 }
321