1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the AArch64 specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64Subtarget.h"
14 
15 #include "AArch64.h"
16 #include "AArch64InstrInfo.h"
17 #include "AArch64PBQPRegAlloc.h"
18 #include "AArch64TargetMachine.h"
19 #include "GISel/AArch64CallLowering.h"
20 #include "GISel/AArch64LegalizerInfo.h"
21 #include "GISel/AArch64RegisterBankInfo.h"
22 #include "MCTargetDesc/AArch64AddressingModes.h"
23 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineScheduler.h"
26 #include "llvm/IR/GlobalValue.h"
27 #include "llvm/Support/AArch64TargetParser.h"
28 #include "llvm/Support/TargetParser.h"
29 
30 using namespace llvm;
31 
32 #define DEBUG_TYPE "aarch64-subtarget"
33 
34 #define GET_SUBTARGETINFO_CTOR
35 #define GET_SUBTARGETINFO_TARGET_DESC
36 #include "AArch64GenSubtargetInfo.inc"
37 
38 static cl::opt<bool>
39 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
40                      "converter pass"), cl::init(true), cl::Hidden);
41 
42 // If OS supports TBI, use this flag to enable it.
43 static cl::opt<bool>
44 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
45                          "an address is ignored"), cl::init(false), cl::Hidden);
46 
47 static cl::opt<bool>
48     UseNonLazyBind("aarch64-enable-nonlazybind",
49                    cl::desc("Call nonlazybind functions via direct GOT load"),
50                    cl::init(false), cl::Hidden);
51 
52 static cl::opt<bool> UseAA("aarch64-use-aa", cl::init(true),
53                            cl::desc("Enable the use of AA during codegen."));
54 
55 AArch64Subtarget &AArch64Subtarget::initializeSubtargetDependencies(
56     StringRef FS, StringRef CPUString, StringRef TuneCPUString) {
57   // Determine default and user-specified characteristics
58 
59   if (CPUString.empty())
60     CPUString = "generic";
61 
62   if (TuneCPUString.empty())
63     TuneCPUString = CPUString;
64 
65   ParseSubtargetFeatures(CPUString, TuneCPUString, FS);
66   initializeProperties();
67 
68   return *this;
69 }
70 
71 void AArch64Subtarget::initializeProperties() {
72   // Initialize CPU specific properties. We should add a tablegen feature for
73   // this in the future so we can specify it together with the subtarget
74   // features.
75   switch (ARMProcFamily) {
76   case Others:
77     break;
78   case Carmel:
79     CacheLineSize = 64;
80     break;
81   case CortexA35:
82   case CortexA53:
83   case CortexA55:
84     PrefFunctionLogAlignment = 4;
85     PrefLoopLogAlignment = 4;
86     MaxBytesForLoopAlignment = 8;
87     break;
88   case CortexA57:
89     MaxInterleaveFactor = 4;
90     PrefFunctionLogAlignment = 4;
91     PrefLoopLogAlignment = 4;
92     MaxBytesForLoopAlignment = 8;
93     break;
94   case CortexA65:
95     PrefFunctionLogAlignment = 3;
96     break;
97   case CortexA72:
98   case CortexA73:
99   case CortexA75:
100     PrefFunctionLogAlignment = 4;
101     PrefLoopLogAlignment = 4;
102     MaxBytesForLoopAlignment = 8;
103     break;
104   case CortexA76:
105   case CortexA77:
106   case CortexA78:
107   case CortexA78C:
108   case CortexR82:
109   case CortexX1:
110   case CortexX1C:
111     PrefFunctionLogAlignment = 4;
112     PrefLoopLogAlignment = 5;
113     MaxBytesForLoopAlignment = 16;
114     break;
115   case CortexA510:
116     PrefFunctionLogAlignment = 4;
117     VScaleForTuning = 1;
118     PrefLoopLogAlignment = 4;
119     MaxBytesForLoopAlignment = 8;
120     break;
121   case CortexA710:
122   case CortexX2:
123     PrefFunctionLogAlignment = 4;
124     VScaleForTuning = 1;
125     PrefLoopLogAlignment = 5;
126     MaxBytesForLoopAlignment = 16;
127     break;
128   case A64FX:
129     CacheLineSize = 256;
130     PrefFunctionLogAlignment = 3;
131     PrefLoopLogAlignment = 2;
132     MaxInterleaveFactor = 4;
133     PrefetchDistance = 128;
134     MinPrefetchStride = 1024;
135     MaxPrefetchIterationsAhead = 4;
136     VScaleForTuning = 4;
137     break;
138   case AppleA7:
139   case AppleA10:
140   case AppleA11:
141   case AppleA12:
142   case AppleA13:
143   case AppleA14:
144     CacheLineSize = 64;
145     PrefetchDistance = 280;
146     MinPrefetchStride = 2048;
147     MaxPrefetchIterationsAhead = 3;
148     break;
149   case ExynosM3:
150     MaxInterleaveFactor = 4;
151     MaxJumpTableSize = 20;
152     PrefFunctionLogAlignment = 5;
153     PrefLoopLogAlignment = 4;
154     break;
155   case Falkor:
156     MaxInterleaveFactor = 4;
157     // FIXME: remove this to enable 64-bit SLP if performance looks good.
158     MinVectorRegisterBitWidth = 128;
159     CacheLineSize = 128;
160     PrefetchDistance = 820;
161     MinPrefetchStride = 2048;
162     MaxPrefetchIterationsAhead = 8;
163     break;
164   case Kryo:
165     MaxInterleaveFactor = 4;
166     VectorInsertExtractBaseCost = 2;
167     CacheLineSize = 128;
168     PrefetchDistance = 740;
169     MinPrefetchStride = 1024;
170     MaxPrefetchIterationsAhead = 11;
171     // FIXME: remove this to enable 64-bit SLP if performance looks good.
172     MinVectorRegisterBitWidth = 128;
173     break;
174   case NeoverseE1:
175     PrefFunctionLogAlignment = 3;
176     break;
177   case NeoverseN1:
178     PrefFunctionLogAlignment = 4;
179     PrefLoopLogAlignment = 5;
180     MaxBytesForLoopAlignment = 16;
181     break;
182   case NeoverseN2:
183     PrefFunctionLogAlignment = 4;
184     PrefLoopLogAlignment = 5;
185     MaxBytesForLoopAlignment = 16;
186     VScaleForTuning = 1;
187     break;
188   case NeoverseV1:
189     PrefFunctionLogAlignment = 4;
190     PrefLoopLogAlignment = 5;
191     MaxBytesForLoopAlignment = 16;
192     VScaleForTuning = 2;
193     break;
194   case Neoverse512TVB:
195     PrefFunctionLogAlignment = 4;
196     VScaleForTuning = 1;
197     MaxInterleaveFactor = 4;
198     break;
199   case Saphira:
200     MaxInterleaveFactor = 4;
201     // FIXME: remove this to enable 64-bit SLP if performance looks good.
202     MinVectorRegisterBitWidth = 128;
203     break;
204   case ThunderX2T99:
205     CacheLineSize = 64;
206     PrefFunctionLogAlignment = 3;
207     PrefLoopLogAlignment = 2;
208     MaxInterleaveFactor = 4;
209     PrefetchDistance = 128;
210     MinPrefetchStride = 1024;
211     MaxPrefetchIterationsAhead = 4;
212     // FIXME: remove this to enable 64-bit SLP if performance looks good.
213     MinVectorRegisterBitWidth = 128;
214     break;
215   case ThunderX:
216   case ThunderXT88:
217   case ThunderXT81:
218   case ThunderXT83:
219     CacheLineSize = 128;
220     PrefFunctionLogAlignment = 3;
221     PrefLoopLogAlignment = 2;
222     // FIXME: remove this to enable 64-bit SLP if performance looks good.
223     MinVectorRegisterBitWidth = 128;
224     break;
225   case TSV110:
226     CacheLineSize = 64;
227     PrefFunctionLogAlignment = 4;
228     PrefLoopLogAlignment = 2;
229     break;
230   case ThunderX3T110:
231     CacheLineSize = 64;
232     PrefFunctionLogAlignment = 4;
233     PrefLoopLogAlignment = 2;
234     MaxInterleaveFactor = 4;
235     PrefetchDistance = 128;
236     MinPrefetchStride = 1024;
237     MaxPrefetchIterationsAhead = 4;
238     // FIXME: remove this to enable 64-bit SLP if performance looks good.
239     MinVectorRegisterBitWidth = 128;
240     break;
241   case Ampere1:
242     CacheLineSize = 64;
243     PrefFunctionLogAlignment = 6;
244     PrefLoopLogAlignment = 6;
245     MaxInterleaveFactor = 4;
246     break;
247   }
248 }
249 
250 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
251                                    const std::string &TuneCPU,
252                                    const std::string &FS,
253                                    const TargetMachine &TM, bool LittleEndian,
254                                    unsigned MinSVEVectorSizeInBitsOverride,
255                                    unsigned MaxSVEVectorSizeInBitsOverride)
256     : AArch64GenSubtargetInfo(TT, CPU, TuneCPU, FS),
257       ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
258       CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
259       IsLittle(LittleEndian),
260       MinSVEVectorSizeInBits(MinSVEVectorSizeInBitsOverride),
261       MaxSVEVectorSizeInBits(MaxSVEVectorSizeInBitsOverride), TargetTriple(TT),
262       InstrInfo(initializeSubtargetDependencies(FS, CPU, TuneCPU)),
263       TLInfo(TM, *this) {
264   if (AArch64::isX18ReservedByDefault(TT))
265     ReserveXRegister.set(18);
266 
267   CallLoweringInfo.reset(new AArch64CallLowering(*getTargetLowering()));
268   InlineAsmLoweringInfo.reset(new InlineAsmLowering(getTargetLowering()));
269   Legalizer.reset(new AArch64LegalizerInfo(*this));
270 
271   auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
272 
273   // FIXME: At this point, we can't rely on Subtarget having RBI.
274   // It's awkward to mix passing RBI and the Subtarget; should we pass
275   // TII/TRI as well?
276   InstSelector.reset(createAArch64InstructionSelector(
277       *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
278 
279   RegBankInfo.reset(RBI);
280 }
281 
282 const CallLowering *AArch64Subtarget::getCallLowering() const {
283   return CallLoweringInfo.get();
284 }
285 
286 const InlineAsmLowering *AArch64Subtarget::getInlineAsmLowering() const {
287   return InlineAsmLoweringInfo.get();
288 }
289 
290 InstructionSelector *AArch64Subtarget::getInstructionSelector() const {
291   return InstSelector.get();
292 }
293 
294 const LegalizerInfo *AArch64Subtarget::getLegalizerInfo() const {
295   return Legalizer.get();
296 }
297 
298 const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
299   return RegBankInfo.get();
300 }
301 
302 /// Find the target operand flags that describe how a global value should be
303 /// referenced for the current subtarget.
304 unsigned
305 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
306                                           const TargetMachine &TM) const {
307   // MachO large model always goes via a GOT, simply to get a single 8-byte
308   // absolute relocation on all global addresses.
309   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
310     return AArch64II::MO_GOT;
311 
312   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) {
313     if (GV->hasDLLImportStorageClass())
314       return AArch64II::MO_GOT | AArch64II::MO_DLLIMPORT;
315     if (getTargetTriple().isOSWindows())
316       return AArch64II::MO_GOT | AArch64II::MO_COFFSTUB;
317     return AArch64II::MO_GOT;
318   }
319 
320   // The small code model's direct accesses use ADRP, which cannot
321   // necessarily produce the value 0 (if the code is above 4GB).
322   // Same for the tiny code model, where we have a pc relative LDR.
323   if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&
324       GV->hasExternalWeakLinkage())
325     return AArch64II::MO_GOT;
326 
327   // References to tagged globals are marked with MO_NC | MO_TAGGED to indicate
328   // that their nominal addresses are tagged and outside of the code model. In
329   // AArch64ExpandPseudo::expandMI we emit an additional instruction to set the
330   // tag if necessary based on MO_TAGGED.
331   if (AllowTaggedGlobals && !isa<FunctionType>(GV->getValueType()))
332     return AArch64II::MO_NC | AArch64II::MO_TAGGED;
333 
334   return AArch64II::MO_NO_FLAG;
335 }
336 
337 unsigned AArch64Subtarget::classifyGlobalFunctionReference(
338     const GlobalValue *GV, const TargetMachine &TM) const {
339   // MachO large model always goes via a GOT, because we don't have the
340   // relocations available to do anything else..
341   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
342       !GV->hasInternalLinkage())
343     return AArch64II::MO_GOT;
344 
345   // NonLazyBind goes via GOT unless we know it's available locally.
346   auto *F = dyn_cast<Function>(GV);
347   if (UseNonLazyBind && F && F->hasFnAttribute(Attribute::NonLazyBind) &&
348       !TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
349     return AArch64II::MO_GOT;
350 
351   // Use ClassifyGlobalReference for setting MO_DLLIMPORT/MO_COFFSTUB.
352   if (getTargetTriple().isOSWindows())
353     return ClassifyGlobalReference(GV, TM);
354 
355   return AArch64II::MO_NO_FLAG;
356 }
357 
358 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
359                                            unsigned NumRegionInstrs) const {
360   // LNT run (at least on Cyclone) showed reasonably significant gains for
361   // bi-directional scheduling. 253.perlbmk.
362   Policy.OnlyTopDown = false;
363   Policy.OnlyBottomUp = false;
364   // Enabling or Disabling the latency heuristic is a close call: It seems to
365   // help nearly no benchmark on out-of-order architectures, on the other hand
366   // it regresses register pressure on a few benchmarking.
367   Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
368 }
369 
370 bool AArch64Subtarget::enableEarlyIfConversion() const {
371   return EnableEarlyIfConvert;
372 }
373 
374 bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
375   if (!UseAddressTopByteIgnored)
376     return false;
377 
378   if (TargetTriple.isDriverKit())
379     return true;
380   if (TargetTriple.isiOS()) {
381     return TargetTriple.getiOSVersion() >= VersionTuple(8);
382   }
383 
384   return false;
385 }
386 
387 std::unique_ptr<PBQPRAConstraint>
388 AArch64Subtarget::getCustomPBQPConstraints() const {
389   return balanceFPOps() ? std::make_unique<A57ChainingConstraint>() : nullptr;
390 }
391 
392 void AArch64Subtarget::mirFileLoaded(MachineFunction &MF) const {
393   // We usually compute max call frame size after ISel. Do the computation now
394   // if the .mir file didn't specify it. Note that this will probably give you
395   // bogus values after PEI has eliminated the callframe setup/destroy pseudo
396   // instructions, specify explicitly if you need it to be correct.
397   MachineFrameInfo &MFI = MF.getFrameInfo();
398   if (!MFI.isMaxCallFrameSizeComputed())
399     MFI.computeMaxCallFrameSize(MF);
400 }
401 
402 bool AArch64Subtarget::useAA() const { return UseAA; }
403