1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the AArch64 specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64Subtarget.h"
14 
15 #include "AArch64.h"
16 #include "AArch64CallLowering.h"
17 #include "AArch64InstrInfo.h"
18 #include "AArch64LegalizerInfo.h"
19 #include "AArch64PBQPRegAlloc.h"
20 #include "AArch64RegisterBankInfo.h"
21 #include "AArch64TargetMachine.h"
22 #include "MCTargetDesc/AArch64AddressingModes.h"
23 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
24 #include "llvm/CodeGen/MachineScheduler.h"
25 #include "llvm/IR/GlobalValue.h"
26 #include "llvm/Support/TargetParser.h"
27 
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "aarch64-subtarget"
31 
32 #define GET_SUBTARGETINFO_CTOR
33 #define GET_SUBTARGETINFO_TARGET_DESC
34 #include "AArch64GenSubtargetInfo.inc"
35 
36 static cl::opt<bool>
37 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
38                      "converter pass"), cl::init(true), cl::Hidden);
39 
40 // If OS supports TBI, use this flag to enable it.
41 static cl::opt<bool>
42 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
43                          "an address is ignored"), cl::init(false), cl::Hidden);
44 
45 static cl::opt<bool>
46     UseNonLazyBind("aarch64-enable-nonlazybind",
47                    cl::desc("Call nonlazybind functions via direct GOT load"),
48                    cl::init(false), cl::Hidden);
49 
50 AArch64Subtarget &
51 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS,
52                                                   StringRef CPUString) {
53   // Determine default and user-specified characteristics
54 
55   if (CPUString.empty())
56     CPUString = "generic";
57 
58   ParseSubtargetFeatures(CPUString, FS);
59   initializeProperties();
60 
61   return *this;
62 }
63 
64 void AArch64Subtarget::initializeProperties() {
65   // Initialize CPU specific properties. We should add a tablegen feature for
66   // this in the future so we can specify it together with the subtarget
67   // features.
68   switch (ARMProcFamily) {
69   case Others:
70     break;
71   case CortexA35:
72     break;
73   case CortexA53:
74     PrefFunctionLogAlignment = 3;
75     break;
76   case CortexA55:
77     break;
78   case CortexA57:
79     MaxInterleaveFactor = 4;
80     PrefFunctionLogAlignment = 4;
81     break;
82   case CortexA65:
83     PrefFunctionLogAlignment = 3;
84     break;
85   case CortexA72:
86   case CortexA73:
87   case CortexA75:
88   case CortexA76:
89     PrefFunctionLogAlignment = 4;
90     break;
91   case A64FX:
92     CacheLineSize = 256;
93     PrefFunctionLogAlignment = 5;
94     PrefLoopLogAlignment = 5;
95     break;
96   case AppleA7:
97   case AppleA10:
98   case AppleA11:
99   case AppleA12:
100   case AppleA13:
101     CacheLineSize = 64;
102     PrefetchDistance = 280;
103     MinPrefetchStride = 2048;
104     MaxPrefetchIterationsAhead = 3;
105     break;
106   case ExynosM3:
107     MaxInterleaveFactor = 4;
108     MaxJumpTableSize = 20;
109     PrefFunctionLogAlignment = 5;
110     PrefLoopLogAlignment = 4;
111     break;
112   case Falkor:
113     MaxInterleaveFactor = 4;
114     // FIXME: remove this to enable 64-bit SLP if performance looks good.
115     MinVectorRegisterBitWidth = 128;
116     CacheLineSize = 128;
117     PrefetchDistance = 820;
118     MinPrefetchStride = 2048;
119     MaxPrefetchIterationsAhead = 8;
120     break;
121   case Kryo:
122     MaxInterleaveFactor = 4;
123     VectorInsertExtractBaseCost = 2;
124     CacheLineSize = 128;
125     PrefetchDistance = 740;
126     MinPrefetchStride = 1024;
127     MaxPrefetchIterationsAhead = 11;
128     // FIXME: remove this to enable 64-bit SLP if performance looks good.
129     MinVectorRegisterBitWidth = 128;
130     break;
131   case NeoverseE1:
132     PrefFunctionLogAlignment = 3;
133     break;
134   case NeoverseN1:
135     PrefFunctionLogAlignment = 4;
136     break;
137   case Saphira:
138     MaxInterleaveFactor = 4;
139     // FIXME: remove this to enable 64-bit SLP if performance looks good.
140     MinVectorRegisterBitWidth = 128;
141     break;
142   case ThunderX2T99:
143     CacheLineSize = 64;
144     PrefFunctionLogAlignment = 3;
145     PrefLoopLogAlignment = 2;
146     MaxInterleaveFactor = 4;
147     PrefetchDistance = 128;
148     MinPrefetchStride = 1024;
149     MaxPrefetchIterationsAhead = 4;
150     // FIXME: remove this to enable 64-bit SLP if performance looks good.
151     MinVectorRegisterBitWidth = 128;
152     break;
153   case ThunderX:
154   case ThunderXT88:
155   case ThunderXT81:
156   case ThunderXT83:
157     CacheLineSize = 128;
158     PrefFunctionLogAlignment = 3;
159     PrefLoopLogAlignment = 2;
160     // FIXME: remove this to enable 64-bit SLP if performance looks good.
161     MinVectorRegisterBitWidth = 128;
162     break;
163   case TSV110:
164     CacheLineSize = 64;
165     PrefFunctionLogAlignment = 4;
166     PrefLoopLogAlignment = 2;
167     break;
168   }
169 }
170 
171 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
172                                    const std::string &FS,
173                                    const TargetMachine &TM, bool LittleEndian)
174     : AArch64GenSubtargetInfo(TT, CPU, FS),
175       ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
176       CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
177       IsLittle(LittleEndian),
178       TargetTriple(TT), FrameLowering(),
179       InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(),
180       TLInfo(TM, *this) {
181   if (AArch64::isX18ReservedByDefault(TT))
182     ReserveXRegister.set(18);
183 
184   CallLoweringInfo.reset(new AArch64CallLowering(*getTargetLowering()));
185   Legalizer.reset(new AArch64LegalizerInfo(*this));
186 
187   auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
188 
189   // FIXME: At this point, we can't rely on Subtarget having RBI.
190   // It's awkward to mix passing RBI and the Subtarget; should we pass
191   // TII/TRI as well?
192   InstSelector.reset(createAArch64InstructionSelector(
193       *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
194 
195   RegBankInfo.reset(RBI);
196 }
197 
198 const CallLowering *AArch64Subtarget::getCallLowering() const {
199   return CallLoweringInfo.get();
200 }
201 
202 InstructionSelector *AArch64Subtarget::getInstructionSelector() const {
203   return InstSelector.get();
204 }
205 
206 const LegalizerInfo *AArch64Subtarget::getLegalizerInfo() const {
207   return Legalizer.get();
208 }
209 
210 const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
211   return RegBankInfo.get();
212 }
213 
214 /// Find the target operand flags that describe how a global value should be
215 /// referenced for the current subtarget.
216 unsigned
217 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
218                                           const TargetMachine &TM) const {
219   // MachO large model always goes via a GOT, simply to get a single 8-byte
220   // absolute relocation on all global addresses.
221   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
222     return AArch64II::MO_GOT;
223 
224   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) {
225     if (GV->hasDLLImportStorageClass())
226       return AArch64II::MO_GOT | AArch64II::MO_DLLIMPORT;
227     if (getTargetTriple().isOSWindows())
228       return AArch64II::MO_GOT | AArch64II::MO_COFFSTUB;
229     return AArch64II::MO_GOT;
230   }
231 
232   // The small code model's direct accesses use ADRP, which cannot
233   // necessarily produce the value 0 (if the code is above 4GB).
234   // Same for the tiny code model, where we have a pc relative LDR.
235   if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&
236       GV->hasExternalWeakLinkage())
237     return AArch64II::MO_GOT;
238 
239   // References to tagged globals are marked with MO_NC | MO_TAGGED to indicate
240   // that their nominal addresses are tagged and outside of the code model. In
241   // AArch64ExpandPseudo::expandMI we emit an additional instruction to set the
242   // tag if necessary based on MO_TAGGED.
243   if (AllowTaggedGlobals && !isa<FunctionType>(GV->getValueType()))
244     return AArch64II::MO_NC | AArch64II::MO_TAGGED;
245 
246   return AArch64II::MO_NO_FLAG;
247 }
248 
249 unsigned AArch64Subtarget::classifyGlobalFunctionReference(
250     const GlobalValue *GV, const TargetMachine &TM) const {
251   // MachO large model always goes via a GOT, because we don't have the
252   // relocations available to do anything else..
253   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
254       !GV->hasInternalLinkage())
255     return AArch64II::MO_GOT;
256 
257   // NonLazyBind goes via GOT unless we know it's available locally.
258   auto *F = dyn_cast<Function>(GV);
259   if (UseNonLazyBind && F && F->hasFnAttribute(Attribute::NonLazyBind) &&
260       !TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
261     return AArch64II::MO_GOT;
262 
263   // Use ClassifyGlobalReference for setting MO_DLLIMPORT/MO_COFFSTUB.
264   if (getTargetTriple().isOSWindows())
265     return ClassifyGlobalReference(GV, TM);
266 
267   return AArch64II::MO_NO_FLAG;
268 }
269 
270 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
271                                            unsigned NumRegionInstrs) const {
272   // LNT run (at least on Cyclone) showed reasonably significant gains for
273   // bi-directional scheduling. 253.perlbmk.
274   Policy.OnlyTopDown = false;
275   Policy.OnlyBottomUp = false;
276   // Enabling or Disabling the latency heuristic is a close call: It seems to
277   // help nearly no benchmark on out-of-order architectures, on the other hand
278   // it regresses register pressure on a few benchmarking.
279   Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
280 }
281 
282 bool AArch64Subtarget::enableEarlyIfConversion() const {
283   return EnableEarlyIfConvert;
284 }
285 
286 bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
287   if (!UseAddressTopByteIgnored)
288     return false;
289 
290   if (TargetTriple.isiOS()) {
291     unsigned Major, Minor, Micro;
292     TargetTriple.getiOSVersion(Major, Minor, Micro);
293     return Major >= 8;
294   }
295 
296   return false;
297 }
298 
299 std::unique_ptr<PBQPRAConstraint>
300 AArch64Subtarget::getCustomPBQPConstraints() const {
301   return balanceFPOps() ? std::make_unique<A57ChainingConstraint>() : nullptr;
302 }
303 
304 void AArch64Subtarget::mirFileLoaded(MachineFunction &MF) const {
305   // We usually compute max call frame size after ISel. Do the computation now
306   // if the .mir file didn't specify it. Note that this will probably give you
307   // bogus values after PEI has eliminated the callframe setup/destroy pseudo
308   // instructions, specify explicitly if you need it to be correct.
309   MachineFrameInfo &MFI = MF.getFrameInfo();
310   if (!MFI.isMaxCallFrameSizeComputed())
311     MFI.computeMaxCallFrameSize(MF);
312 }
313