1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the AArch64 specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AArch64Subtarget.h"
15 #include "AArch64InstrInfo.h"
16 #include "AArch64PBQPRegAlloc.h"
17 #include "llvm/CodeGen/MachineScheduler.h"
18 #include "llvm/IR/GlobalValue.h"
19 #include "llvm/Support/TargetRegistry.h"
20 
21 using namespace llvm;
22 
23 #define DEBUG_TYPE "aarch64-subtarget"
24 
25 #define GET_SUBTARGETINFO_CTOR
26 #define GET_SUBTARGETINFO_TARGET_DESC
27 #include "AArch64GenSubtargetInfo.inc"
28 
29 static cl::opt<bool>
30 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
31                      "converter pass"), cl::init(true), cl::Hidden);
32 
33 // If OS supports TBI, use this flag to enable it.
34 static cl::opt<bool>
35 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
36                          "an address is ignored"), cl::init(false), cl::Hidden);
37 
38 AArch64Subtarget &
39 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS,
40                                                   StringRef CPUString) {
41   // Determine default and user-specified characteristics
42 
43   if (CPUString.empty())
44     CPUString = "generic";
45 
46   ParseSubtargetFeatures(CPUString, FS);
47   initializeProperties();
48 
49   return *this;
50 }
51 
52 void AArch64Subtarget::initializeProperties() {
53   // Initialize CPU specific properties. We should add a tablegen feature for
54   // this in the future so we can specify it together with the subtarget
55   // features.
56   switch (ARMProcFamily) {
57   case Cyclone:
58     CacheLineSize = 64;
59     PrefetchDistance = 280;
60     MinPrefetchStride = 2048;
61     MaxPrefetchIterationsAhead = 3;
62     break;
63   case CortexA57:
64     MaxInterleaveFactor = 4;
65     break;
66   case ExynosM1:
67     MaxInterleaveFactor = 4;
68     MaxJumpTableSize = 8;
69     PrefFunctionAlignment = 4;
70     PrefLoopAlignment = 3;
71     break;
72   case Falkor:
73     MaxInterleaveFactor = 4;
74     VectorInsertExtractBaseCost = 2;
75     break;
76   case Kryo:
77     MaxInterleaveFactor = 4;
78     VectorInsertExtractBaseCost = 2;
79     CacheLineSize = 128;
80     PrefetchDistance = 740;
81     MinPrefetchStride = 1024;
82     MaxPrefetchIterationsAhead = 11;
83     break;
84   case Vulcan:
85     MaxInterleaveFactor = 4;
86     break;
87   case CortexA35: break;
88   case CortexA53: break;
89   case CortexA72: break;
90   case CortexA73: break;
91   case Others: break;
92   }
93 }
94 
95 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
96                                    const std::string &FS,
97                                    const TargetMachine &TM, bool LittleEndian)
98     : AArch64GenSubtargetInfo(TT, CPU, FS), ReserveX18(TT.isOSDarwin()),
99       IsLittle(LittleEndian), TargetTriple(TT), FrameLowering(),
100       InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(),
101       TLInfo(TM, *this), GISel() {}
102 
103 const CallLowering *AArch64Subtarget::getCallLowering() const {
104   assert(GISel && "Access to GlobalISel APIs not set");
105   return GISel->getCallLowering();
106 }
107 
108 const InstructionSelector *AArch64Subtarget::getInstructionSelector() const {
109   assert(GISel && "Access to GlobalISel APIs not set");
110   return GISel->getInstructionSelector();
111 }
112 
113 const LegalizerInfo *AArch64Subtarget::getLegalizerInfo() const {
114   assert(GISel && "Access to GlobalISel APIs not set");
115   return GISel->getLegalizerInfo();
116 }
117 
118 const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
119   assert(GISel && "Access to GlobalISel APIs not set");
120   return GISel->getRegBankInfo();
121 }
122 
123 /// Find the target operand flags that describe how a global value should be
124 /// referenced for the current subtarget.
125 unsigned char
126 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
127                                           const TargetMachine &TM) const {
128   // MachO large model always goes via a GOT, simply to get a single 8-byte
129   // absolute relocation on all global addresses.
130   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
131     return AArch64II::MO_GOT;
132 
133   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
134     return AArch64II::MO_GOT;
135 
136   // The small code mode's direct accesses use ADRP, which cannot necessarily
137   // produce the value 0 (if the code is above 4GB).
138   if (TM.getCodeModel() == CodeModel::Small && GV->hasExternalWeakLinkage())
139     return AArch64II::MO_GOT;
140 
141   return AArch64II::MO_NO_FLAG;
142 }
143 
144 /// This function returns the name of a function which has an interface
145 /// like the non-standard bzero function, if such a function exists on
146 /// the current subtarget and it is considered prefereable over
147 /// memset with zero passed as the second argument. Otherwise it
148 /// returns null.
149 const char *AArch64Subtarget::getBZeroEntry() const {
150   // Prefer bzero on Darwin only.
151   if(isTargetDarwin())
152     return "bzero";
153 
154   return nullptr;
155 }
156 
157 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
158                                            unsigned NumRegionInstrs) const {
159   // LNT run (at least on Cyclone) showed reasonably significant gains for
160   // bi-directional scheduling. 253.perlbmk.
161   Policy.OnlyTopDown = false;
162   Policy.OnlyBottomUp = false;
163   // Enabling or Disabling the latency heuristic is a close call: It seems to
164   // help nearly no benchmark on out-of-order architectures, on the other hand
165   // it regresses register pressure on a few benchmarking.
166   Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
167 }
168 
169 bool AArch64Subtarget::enableEarlyIfConversion() const {
170   return EnableEarlyIfConvert;
171 }
172 
173 bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
174   if (!UseAddressTopByteIgnored)
175     return false;
176 
177   if (TargetTriple.isiOS()) {
178     unsigned Major, Minor, Micro;
179     TargetTriple.getiOSVersion(Major, Minor, Micro);
180     return Major >= 8;
181   }
182 
183   return false;
184 }
185 
186 std::unique_ptr<PBQPRAConstraint>
187 AArch64Subtarget::getCustomPBQPConstraints() const {
188   return balanceFPOps() ? llvm::make_unique<A57ChainingConstraint>() : nullptr;
189 }
190