1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the operating system Host concept. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/Host.h" 14 #include "llvm/ADT/SmallSet.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringMap.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/llvm-config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/TargetParser.h" 25 #include "llvm/Support/raw_ostream.h" 26 #include <assert.h> 27 #include <string.h> 28 29 // Include the platform-specific parts of this class. 30 #ifdef LLVM_ON_UNIX 31 #include "Unix/Host.inc" 32 #endif 33 #ifdef _WIN32 34 #include "Windows/Host.inc" 35 #endif 36 #ifdef _MSC_VER 37 #include <intrin.h> 38 #endif 39 #if defined(__APPLE__) && (!defined(__x86_64__)) 40 #include <mach/host_info.h> 41 #include <mach/mach.h> 42 #include <mach/mach_host.h> 43 #include <mach/machine.h> 44 #endif 45 46 #define DEBUG_TYPE "host-detection" 47 48 //===----------------------------------------------------------------------===// 49 // 50 // Implementations of the CPU detection routines 51 // 52 //===----------------------------------------------------------------------===// 53 54 using namespace llvm; 55 56 static std::unique_ptr<llvm::MemoryBuffer> 57 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 58 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 59 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 60 if (std::error_code EC = Text.getError()) { 61 llvm::errs() << "Can't read " 62 << "/proc/cpuinfo: " << EC.message() << "\n"; 63 return nullptr; 64 } 65 return std::move(*Text); 66 } 67 68 StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) { 69 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 70 // and so we must use an operating-system interface to determine the current 71 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 72 const char *generic = "generic"; 73 74 // The cpu line is second (after the 'processor: 0' line), so if this 75 // buffer is too small then something has changed (or is wrong). 76 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 77 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 78 79 StringRef::const_iterator CIP = CPUInfoStart; 80 81 StringRef::const_iterator CPUStart = 0; 82 size_t CPULen = 0; 83 84 // We need to find the first line which starts with cpu, spaces, and a colon. 85 // After the colon, there may be some additional spaces and then the cpu type. 86 while (CIP < CPUInfoEnd && CPUStart == 0) { 87 if (CIP < CPUInfoEnd && *CIP == '\n') 88 ++CIP; 89 90 if (CIP < CPUInfoEnd && *CIP == 'c') { 91 ++CIP; 92 if (CIP < CPUInfoEnd && *CIP == 'p') { 93 ++CIP; 94 if (CIP < CPUInfoEnd && *CIP == 'u') { 95 ++CIP; 96 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 97 ++CIP; 98 99 if (CIP < CPUInfoEnd && *CIP == ':') { 100 ++CIP; 101 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 102 ++CIP; 103 104 if (CIP < CPUInfoEnd) { 105 CPUStart = CIP; 106 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 107 *CIP != ',' && *CIP != '\n')) 108 ++CIP; 109 CPULen = CIP - CPUStart; 110 } 111 } 112 } 113 } 114 } 115 116 if (CPUStart == 0) 117 while (CIP < CPUInfoEnd && *CIP != '\n') 118 ++CIP; 119 } 120 121 if (CPUStart == 0) 122 return generic; 123 124 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 125 .Case("604e", "604e") 126 .Case("604", "604") 127 .Case("7400", "7400") 128 .Case("7410", "7400") 129 .Case("7447", "7400") 130 .Case("7455", "7450") 131 .Case("G4", "g4") 132 .Case("POWER4", "970") 133 .Case("PPC970FX", "970") 134 .Case("PPC970MP", "970") 135 .Case("G5", "g5") 136 .Case("POWER5", "g5") 137 .Case("A2", "a2") 138 .Case("POWER6", "pwr6") 139 .Case("POWER7", "pwr7") 140 .Case("POWER8", "pwr8") 141 .Case("POWER8E", "pwr8") 142 .Case("POWER8NVL", "pwr8") 143 .Case("POWER9", "pwr9") 144 // FIXME: If we get a simulator or machine with the capabilities of 145 // mcpu=future, we should revisit this and add the name reported by the 146 // simulator/machine. 147 .Default(generic); 148 } 149 150 StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { 151 // The cpuid register on arm is not accessible from user space. On Linux, 152 // it is exposed through the /proc/cpuinfo file. 153 154 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 155 // in all cases. 156 SmallVector<StringRef, 32> Lines; 157 ProcCpuinfoContent.split(Lines, "\n"); 158 159 // Look for the CPU implementer line. 160 StringRef Implementer; 161 StringRef Hardware; 162 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 163 if (Lines[I].startswith("CPU implementer")) 164 Implementer = Lines[I].substr(15).ltrim("\t :"); 165 if (Lines[I].startswith("Hardware")) 166 Hardware = Lines[I].substr(8).ltrim("\t :"); 167 } 168 169 if (Implementer == "0x41") { // ARM Ltd. 170 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 171 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 172 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 173 return "cortex-a53"; 174 175 176 // Look for the CPU part line. 177 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 178 if (Lines[I].startswith("CPU part")) 179 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 180 // values correspond to the "Part number" in the CP15/c0 register. The 181 // contents are specified in the various processor manuals. 182 // This corresponds to the Main ID Register in Technical Reference Manuals. 183 // and is used in programs like sys-utils 184 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 185 .Case("0x926", "arm926ej-s") 186 .Case("0xb02", "mpcore") 187 .Case("0xb36", "arm1136j-s") 188 .Case("0xb56", "arm1156t2-s") 189 .Case("0xb76", "arm1176jz-s") 190 .Case("0xc08", "cortex-a8") 191 .Case("0xc09", "cortex-a9") 192 .Case("0xc0f", "cortex-a15") 193 .Case("0xc20", "cortex-m0") 194 .Case("0xc23", "cortex-m3") 195 .Case("0xc24", "cortex-m4") 196 .Case("0xd22", "cortex-m55") 197 .Case("0xd02", "cortex-a34") 198 .Case("0xd04", "cortex-a35") 199 .Case("0xd03", "cortex-a53") 200 .Case("0xd07", "cortex-a57") 201 .Case("0xd08", "cortex-a72") 202 .Case("0xd09", "cortex-a73") 203 .Case("0xd0a", "cortex-a75") 204 .Case("0xd0b", "cortex-a76") 205 .Default("generic"); 206 } 207 208 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium. 209 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 210 if (Lines[I].startswith("CPU part")) { 211 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 212 .Case("0x516", "thunderx2t99") 213 .Case("0x0516", "thunderx2t99") 214 .Case("0xaf", "thunderx2t99") 215 .Case("0x0af", "thunderx2t99") 216 .Case("0xa1", "thunderxt88") 217 .Case("0x0a1", "thunderxt88") 218 .Default("generic"); 219 } 220 } 221 } 222 223 if (Implementer == "0x46") { // Fujitsu Ltd. 224 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 225 if (Lines[I].startswith("CPU part")) { 226 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 227 .Case("0x001", "a64fx") 228 .Default("generic"); 229 } 230 } 231 } 232 233 if (Implementer == "0x48") // HiSilicon Technologies, Inc. 234 // Look for the CPU part line. 235 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 236 if (Lines[I].startswith("CPU part")) 237 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 238 // values correspond to the "Part number" in the CP15/c0 register. The 239 // contents are specified in the various processor manuals. 240 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 241 .Case("0xd01", "tsv110") 242 .Default("generic"); 243 244 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 245 // Look for the CPU part line. 246 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 247 if (Lines[I].startswith("CPU part")) 248 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 249 // values correspond to the "Part number" in the CP15/c0 register. The 250 // contents are specified in the various processor manuals. 251 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 252 .Case("0x06f", "krait") // APQ8064 253 .Case("0x201", "kryo") 254 .Case("0x205", "kryo") 255 .Case("0x211", "kryo") 256 .Case("0x800", "cortex-a73") 257 .Case("0x801", "cortex-a73") 258 .Case("0x802", "cortex-a73") 259 .Case("0x803", "cortex-a73") 260 .Case("0x804", "cortex-a73") 261 .Case("0x805", "cortex-a73") 262 .Case("0xc00", "falkor") 263 .Case("0xc01", "saphira") 264 .Default("generic"); 265 266 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. 267 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow 268 // any predictive pattern across variants and parts. 269 unsigned Variant = 0, Part = 0; 270 271 // Look for the CPU variant line, whose value is a 1 digit hexadecimal 272 // number, corresponding to the Variant bits in the CP15/C0 register. 273 for (auto I : Lines) 274 if (I.consume_front("CPU variant")) 275 I.ltrim("\t :").getAsInteger(0, Variant); 276 277 // Look for the CPU part line, whose value is a 3 digit hexadecimal 278 // number, corresponding to the PartNum bits in the CP15/C0 register. 279 for (auto I : Lines) 280 if (I.consume_front("CPU part")) 281 I.ltrim("\t :").getAsInteger(0, Part); 282 283 unsigned Exynos = (Variant << 12) | Part; 284 switch (Exynos) { 285 default: 286 // Default by falling through to Exynos M3. 287 LLVM_FALLTHROUGH; 288 case 0x1002: 289 return "exynos-m3"; 290 case 0x1003: 291 return "exynos-m4"; 292 } 293 } 294 295 return "generic"; 296 } 297 298 StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { 299 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 300 301 // The "processor 0:" line comes after a fair amount of other information, 302 // including a cache breakdown, but this should be plenty. 303 SmallVector<StringRef, 32> Lines; 304 ProcCpuinfoContent.split(Lines, "\n"); 305 306 // Look for the CPU features. 307 SmallVector<StringRef, 32> CPUFeatures; 308 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 309 if (Lines[I].startswith("features")) { 310 size_t Pos = Lines[I].find(":"); 311 if (Pos != StringRef::npos) { 312 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 313 break; 314 } 315 } 316 317 // We need to check for the presence of vector support independently of 318 // the machine type, since we may only use the vector register set when 319 // supported by the kernel (and hypervisor). 320 bool HaveVectorSupport = false; 321 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 322 if (CPUFeatures[I] == "vx") 323 HaveVectorSupport = true; 324 } 325 326 // Now check the processor machine type. 327 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 328 if (Lines[I].startswith("processor ")) { 329 size_t Pos = Lines[I].find("machine = "); 330 if (Pos != StringRef::npos) { 331 Pos += sizeof("machine = ") - 1; 332 unsigned int Id; 333 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 334 if (Id >= 8561 && HaveVectorSupport) 335 return "z15"; 336 if (Id >= 3906 && HaveVectorSupport) 337 return "z14"; 338 if (Id >= 2964 && HaveVectorSupport) 339 return "z13"; 340 if (Id >= 2827) 341 return "zEC12"; 342 if (Id >= 2817) 343 return "z196"; 344 } 345 } 346 break; 347 } 348 } 349 350 return "generic"; 351 } 352 353 StringRef sys::detail::getHostCPUNameForBPF() { 354 #if !defined(__linux__) || !defined(__x86_64__) 355 return "generic"; 356 #else 357 uint8_t v3_insns[40] __attribute__ ((aligned (8))) = 358 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 359 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 360 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 361 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 362 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 363 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 364 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 365 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 366 /* BPF_EXIT_INSN() */ 367 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 368 369 uint8_t v2_insns[40] __attribute__ ((aligned (8))) = 370 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 371 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 372 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 373 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 374 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 375 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 376 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 377 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 378 /* BPF_EXIT_INSN() */ 379 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 380 381 struct bpf_prog_load_attr { 382 uint32_t prog_type; 383 uint32_t insn_cnt; 384 uint64_t insns; 385 uint64_t license; 386 uint32_t log_level; 387 uint32_t log_size; 388 uint64_t log_buf; 389 uint32_t kern_version; 390 uint32_t prog_flags; 391 } attr = {}; 392 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 393 attr.insn_cnt = 5; 394 attr.insns = (uint64_t)v3_insns; 395 attr.license = (uint64_t)"DUMMY"; 396 397 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, 398 sizeof(attr)); 399 if (fd >= 0) { 400 close(fd); 401 return "v3"; 402 } 403 404 /* Clear the whole attr in case its content changed by syscall. */ 405 memset(&attr, 0, sizeof(attr)); 406 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 407 attr.insn_cnt = 5; 408 attr.insns = (uint64_t)v2_insns; 409 attr.license = (uint64_t)"DUMMY"; 410 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 411 if (fd >= 0) { 412 close(fd); 413 return "v2"; 414 } 415 return "v1"; 416 #endif 417 } 418 419 #if defined(__i386__) || defined(_M_IX86) || \ 420 defined(__x86_64__) || defined(_M_X64) 421 422 enum VendorSignatures { 423 SIG_INTEL = 0x756e6547 /* Genu */, 424 SIG_AMD = 0x68747541 /* Auth */ 425 }; 426 427 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 428 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 429 // support. Consequently, for i386, the presence of CPUID is checked first 430 // via the corresponding eflags bit. 431 // Removal of cpuid.h header motivated by PR30384 432 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 433 // or test-suite, but are used in external projects e.g. libstdcxx 434 static bool isCpuIdSupported() { 435 #if defined(__GNUC__) || defined(__clang__) 436 #if defined(__i386__) 437 int __cpuid_supported; 438 __asm__(" pushfl\n" 439 " popl %%eax\n" 440 " movl %%eax,%%ecx\n" 441 " xorl $0x00200000,%%eax\n" 442 " pushl %%eax\n" 443 " popfl\n" 444 " pushfl\n" 445 " popl %%eax\n" 446 " movl $0,%0\n" 447 " cmpl %%eax,%%ecx\n" 448 " je 1f\n" 449 " movl $1,%0\n" 450 "1:" 451 : "=r"(__cpuid_supported) 452 : 453 : "eax", "ecx"); 454 if (!__cpuid_supported) 455 return false; 456 #endif 457 return true; 458 #endif 459 return true; 460 } 461 462 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 463 /// the specified arguments. If we can't run cpuid on the host, return true. 464 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 465 unsigned *rECX, unsigned *rEDX) { 466 #if defined(__GNUC__) || defined(__clang__) 467 #if defined(__x86_64__) 468 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 469 // FIXME: should we save this for Clang? 470 __asm__("movq\t%%rbx, %%rsi\n\t" 471 "cpuid\n\t" 472 "xchgq\t%%rbx, %%rsi\n\t" 473 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 474 : "a"(value)); 475 return false; 476 #elif defined(__i386__) 477 __asm__("movl\t%%ebx, %%esi\n\t" 478 "cpuid\n\t" 479 "xchgl\t%%ebx, %%esi\n\t" 480 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 481 : "a"(value)); 482 return false; 483 #else 484 return true; 485 #endif 486 #elif defined(_MSC_VER) 487 // The MSVC intrinsic is portable across x86 and x64. 488 int registers[4]; 489 __cpuid(registers, value); 490 *rEAX = registers[0]; 491 *rEBX = registers[1]; 492 *rECX = registers[2]; 493 *rEDX = registers[3]; 494 return false; 495 #else 496 return true; 497 #endif 498 } 499 500 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 501 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 502 /// return true. 503 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 504 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 505 unsigned *rEDX) { 506 #if defined(__GNUC__) || defined(__clang__) 507 #if defined(__x86_64__) 508 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 509 // FIXME: should we save this for Clang? 510 __asm__("movq\t%%rbx, %%rsi\n\t" 511 "cpuid\n\t" 512 "xchgq\t%%rbx, %%rsi\n\t" 513 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 514 : "a"(value), "c"(subleaf)); 515 return false; 516 #elif defined(__i386__) 517 __asm__("movl\t%%ebx, %%esi\n\t" 518 "cpuid\n\t" 519 "xchgl\t%%ebx, %%esi\n\t" 520 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 521 : "a"(value), "c"(subleaf)); 522 return false; 523 #else 524 return true; 525 #endif 526 #elif defined(_MSC_VER) 527 int registers[4]; 528 __cpuidex(registers, value, subleaf); 529 *rEAX = registers[0]; 530 *rEBX = registers[1]; 531 *rECX = registers[2]; 532 *rEDX = registers[3]; 533 return false; 534 #else 535 return true; 536 #endif 537 } 538 539 // Read control register 0 (XCR0). Used to detect features such as AVX. 540 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 541 #if defined(__GNUC__) || defined(__clang__) 542 // Check xgetbv; this uses a .byte sequence instead of the instruction 543 // directly because older assemblers do not include support for xgetbv and 544 // there is no easy way to conditionally compile based on the assembler used. 545 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 546 return false; 547 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 548 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 549 *rEAX = Result; 550 *rEDX = Result >> 32; 551 return false; 552 #else 553 return true; 554 #endif 555 } 556 557 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 558 unsigned *Model) { 559 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 560 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 561 if (*Family == 6 || *Family == 0xf) { 562 if (*Family == 0xf) 563 // Examine extended family ID if family ID is F. 564 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 565 // Examine extended model ID if family ID is 6 or F. 566 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 567 } 568 } 569 570 static void 571 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 572 unsigned Brand_id, unsigned Features, 573 unsigned Features2, unsigned Features3, 574 unsigned *Type, unsigned *Subtype) { 575 if (Brand_id != 0) 576 return; 577 switch (Family) { 578 case 3: 579 *Type = X86::INTEL_i386; 580 break; 581 case 4: 582 *Type = X86::INTEL_i486; 583 break; 584 case 5: 585 if (Features & (1 << X86::FEATURE_MMX)) { 586 *Type = X86::INTEL_PENTIUM_MMX; 587 break; 588 } 589 *Type = X86::INTEL_PENTIUM; 590 break; 591 case 6: 592 switch (Model) { 593 case 0x01: // Pentium Pro processor 594 *Type = X86::INTEL_PENTIUM_PRO; 595 break; 596 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 597 // model 03 598 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 599 // model 05, and Intel Celeron processor, model 05 600 case 0x06: // Celeron processor, model 06 601 *Type = X86::INTEL_PENTIUM_II; 602 break; 603 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 604 // processor, model 07 605 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 606 // model 08, and Celeron processor, model 08 607 case 0x0a: // Pentium III Xeon processor, model 0Ah 608 case 0x0b: // Pentium III processor, model 0Bh 609 *Type = X86::INTEL_PENTIUM_III; 610 break; 611 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 612 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 613 // 0Dh. All processors are manufactured using the 90 nm process. 614 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 615 // Integrated Processor with Intel QuickAssist Technology 616 *Type = X86::INTEL_PENTIUM_M; 617 break; 618 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 619 // 0Eh. All processors are manufactured using the 65 nm process. 620 *Type = X86::INTEL_CORE_DUO; 621 break; // yonah 622 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 623 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 624 // mobile processor, Intel Core 2 Extreme processor, Intel 625 // Pentium Dual-Core processor, Intel Xeon processor, model 626 // 0Fh. All processors are manufactured using the 65 nm process. 627 case 0x16: // Intel Celeron processor model 16h. All processors are 628 // manufactured using the 65 nm process 629 *Type = X86::INTEL_CORE2; // "core2" 630 *Subtype = X86::INTEL_CORE2_65; 631 break; 632 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 633 // 17h. All processors are manufactured using the 45 nm process. 634 // 635 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 636 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 637 // the 45 nm process. 638 *Type = X86::INTEL_CORE2; // "penryn" 639 *Subtype = X86::INTEL_CORE2_45; 640 break; 641 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 642 // processors are manufactured using the 45 nm process. 643 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 644 // As found in a Summer 2010 model iMac. 645 case 0x1f: 646 case 0x2e: // Nehalem EX 647 *Type = X86::INTEL_COREI7; // "nehalem" 648 *Subtype = X86::INTEL_COREI7_NEHALEM; 649 break; 650 case 0x25: // Intel Core i7, laptop version. 651 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 652 // processors are manufactured using the 32 nm process. 653 case 0x2f: // Westmere EX 654 *Type = X86::INTEL_COREI7; // "westmere" 655 *Subtype = X86::INTEL_COREI7_WESTMERE; 656 break; 657 case 0x2a: // Intel Core i7 processor. All processors are manufactured 658 // using the 32 nm process. 659 case 0x2d: 660 *Type = X86::INTEL_COREI7; //"sandybridge" 661 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 662 break; 663 case 0x3a: 664 case 0x3e: // Ivy Bridge EP 665 *Type = X86::INTEL_COREI7; // "ivybridge" 666 *Subtype = X86::INTEL_COREI7_IVYBRIDGE; 667 break; 668 669 // Haswell: 670 case 0x3c: 671 case 0x3f: 672 case 0x45: 673 case 0x46: 674 *Type = X86::INTEL_COREI7; // "haswell" 675 *Subtype = X86::INTEL_COREI7_HASWELL; 676 break; 677 678 // Broadwell: 679 case 0x3d: 680 case 0x47: 681 case 0x4f: 682 case 0x56: 683 *Type = X86::INTEL_COREI7; // "broadwell" 684 *Subtype = X86::INTEL_COREI7_BROADWELL; 685 break; 686 687 // Skylake: 688 case 0x4e: // Skylake mobile 689 case 0x5e: // Skylake desktop 690 case 0x8e: // Kaby Lake mobile 691 case 0x9e: // Kaby Lake desktop 692 *Type = X86::INTEL_COREI7; // "skylake" 693 *Subtype = X86::INTEL_COREI7_SKYLAKE; 694 break; 695 696 // Skylake Xeon: 697 case 0x55: 698 *Type = X86::INTEL_COREI7; 699 if (Features2 & (1 << (X86::FEATURE_AVX512BF16 - 32))) 700 *Subtype = X86::INTEL_COREI7_COOPERLAKE; // "cooperlake" 701 else if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) 702 *Subtype = X86::INTEL_COREI7_CASCADELAKE; // "cascadelake" 703 else 704 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 705 break; 706 707 // Cannonlake: 708 case 0x66: 709 *Type = X86::INTEL_COREI7; 710 *Subtype = X86::INTEL_COREI7_CANNONLAKE; // "cannonlake" 711 break; 712 713 // Icelake: 714 case 0x7d: 715 case 0x7e: 716 *Type = X86::INTEL_COREI7; 717 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; // "icelake-client" 718 break; 719 720 // Icelake Xeon: 721 case 0x6a: 722 case 0x6c: 723 *Type = X86::INTEL_COREI7; 724 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; // "icelake-server" 725 break; 726 727 case 0x1c: // Most 45 nm Intel Atom processors 728 case 0x26: // 45 nm Atom Lincroft 729 case 0x27: // 32 nm Atom Medfield 730 case 0x35: // 32 nm Atom Midview 731 case 0x36: // 32 nm Atom Midview 732 *Type = X86::INTEL_BONNELL; 733 break; // "bonnell" 734 735 // Atom Silvermont codes from the Intel software optimization guide. 736 case 0x37: 737 case 0x4a: 738 case 0x4d: 739 case 0x5a: 740 case 0x5d: 741 case 0x4c: // really airmont 742 *Type = X86::INTEL_SILVERMONT; 743 break; // "silvermont" 744 // Goldmont: 745 case 0x5c: // Apollo Lake 746 case 0x5f: // Denverton 747 *Type = X86::INTEL_GOLDMONT; 748 break; // "goldmont" 749 case 0x7a: 750 *Type = X86::INTEL_GOLDMONT_PLUS; 751 break; 752 case 0x86: 753 *Type = X86::INTEL_TREMONT; 754 break; 755 756 case 0x57: 757 *Type = X86::INTEL_KNL; // knl 758 break; 759 760 case 0x85: 761 *Type = X86::INTEL_KNM; // knm 762 break; 763 764 default: // Unknown family 6 CPU, try to guess. 765 // TODO detect tigerlake host 766 if (Features3 & (1 << (X86::FEATURE_AVX512VP2INTERSECT - 64))) { 767 *Type = X86::INTEL_COREI7; 768 *Subtype = X86::INTEL_COREI7_TIGERLAKE; 769 break; 770 } 771 772 if (Features & (1 << X86::FEATURE_AVX512VBMI2)) { 773 *Type = X86::INTEL_COREI7; 774 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; 775 break; 776 } 777 778 if (Features & (1 << X86::FEATURE_AVX512VBMI)) { 779 *Type = X86::INTEL_COREI7; 780 *Subtype = X86::INTEL_COREI7_CANNONLAKE; 781 break; 782 } 783 784 if (Features2 & (1 << (X86::FEATURE_AVX512BF16 - 32))) { 785 *Type = X86::INTEL_COREI7; 786 *Subtype = X86::INTEL_COREI7_COOPERLAKE; 787 break; 788 } 789 790 if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) { 791 *Type = X86::INTEL_COREI7; 792 *Subtype = X86::INTEL_COREI7_CASCADELAKE; 793 break; 794 } 795 796 if (Features & (1 << X86::FEATURE_AVX512VL)) { 797 *Type = X86::INTEL_COREI7; 798 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; 799 break; 800 } 801 802 if (Features & (1 << X86::FEATURE_AVX512ER)) { 803 *Type = X86::INTEL_KNL; // knl 804 break; 805 } 806 807 if (Features3 & (1 << (X86::FEATURE_CLFLUSHOPT - 64))) { 808 if (Features3 & (1 << (X86::FEATURE_SHA - 64))) { 809 *Type = X86::INTEL_GOLDMONT; 810 } else { 811 *Type = X86::INTEL_COREI7; 812 *Subtype = X86::INTEL_COREI7_SKYLAKE; 813 } 814 break; 815 } 816 if (Features3 & (1 << (X86::FEATURE_ADX - 64))) { 817 *Type = X86::INTEL_COREI7; 818 *Subtype = X86::INTEL_COREI7_BROADWELL; 819 break; 820 } 821 if (Features & (1 << X86::FEATURE_AVX2)) { 822 *Type = X86::INTEL_COREI7; 823 *Subtype = X86::INTEL_COREI7_HASWELL; 824 break; 825 } 826 if (Features & (1 << X86::FEATURE_AVX)) { 827 *Type = X86::INTEL_COREI7; 828 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 829 break; 830 } 831 if (Features & (1 << X86::FEATURE_SSE4_2)) { 832 if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { 833 *Type = X86::INTEL_SILVERMONT; 834 } else { 835 *Type = X86::INTEL_COREI7; 836 *Subtype = X86::INTEL_COREI7_NEHALEM; 837 } 838 break; 839 } 840 if (Features & (1 << X86::FEATURE_SSE4_1)) { 841 *Type = X86::INTEL_CORE2; // "penryn" 842 *Subtype = X86::INTEL_CORE2_45; 843 break; 844 } 845 if (Features & (1 << X86::FEATURE_SSSE3)) { 846 if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { 847 *Type = X86::INTEL_BONNELL; // "bonnell" 848 } else { 849 *Type = X86::INTEL_CORE2; // "core2" 850 *Subtype = X86::INTEL_CORE2_65; 851 } 852 break; 853 } 854 if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { 855 *Type = X86::INTEL_CORE2; // "core2" 856 *Subtype = X86::INTEL_CORE2_65; 857 break; 858 } 859 if (Features & (1 << X86::FEATURE_SSE3)) { 860 *Type = X86::INTEL_CORE_DUO; 861 break; 862 } 863 if (Features & (1 << X86::FEATURE_SSE2)) { 864 *Type = X86::INTEL_PENTIUM_M; 865 break; 866 } 867 if (Features & (1 << X86::FEATURE_SSE)) { 868 *Type = X86::INTEL_PENTIUM_III; 869 break; 870 } 871 if (Features & (1 << X86::FEATURE_MMX)) { 872 *Type = X86::INTEL_PENTIUM_II; 873 break; 874 } 875 *Type = X86::INTEL_PENTIUM_PRO; 876 break; 877 } 878 break; 879 case 15: { 880 if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { 881 *Type = X86::INTEL_NOCONA; 882 break; 883 } 884 if (Features & (1 << X86::FEATURE_SSE3)) { 885 *Type = X86::INTEL_PRESCOTT; 886 break; 887 } 888 *Type = X86::INTEL_PENTIUM_IV; 889 break; 890 } 891 default: 892 break; /*"generic"*/ 893 } 894 } 895 896 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 897 unsigned Features, unsigned *Type, 898 unsigned *Subtype) { 899 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 900 // appears to be no way to generate the wide variety of AMD-specific targets 901 // from the information returned from CPUID. 902 switch (Family) { 903 case 4: 904 *Type = X86::AMD_i486; 905 break; 906 case 5: 907 *Type = X86::AMDPENTIUM; 908 switch (Model) { 909 case 6: 910 case 7: 911 *Subtype = X86::AMDPENTIUM_K6; 912 break; // "k6" 913 case 8: 914 *Subtype = X86::AMDPENTIUM_K62; 915 break; // "k6-2" 916 case 9: 917 case 13: 918 *Subtype = X86::AMDPENTIUM_K63; 919 break; // "k6-3" 920 case 10: 921 *Subtype = X86::AMDPENTIUM_GEODE; 922 break; // "geode" 923 } 924 break; 925 case 6: 926 if (Features & (1 << X86::FEATURE_SSE)) { 927 *Type = X86::AMD_ATHLON_XP; 928 break; // "athlon-xp" 929 } 930 *Type = X86::AMD_ATHLON; 931 break; // "athlon" 932 case 15: 933 if (Features & (1 << X86::FEATURE_SSE3)) { 934 *Type = X86::AMD_K8SSE3; 935 break; // "k8-sse3" 936 } 937 *Type = X86::AMD_K8; 938 break; // "k8" 939 case 16: 940 *Type = X86::AMDFAM10H; // "amdfam10" 941 switch (Model) { 942 case 2: 943 *Subtype = X86::AMDFAM10H_BARCELONA; 944 break; 945 case 4: 946 *Subtype = X86::AMDFAM10H_SHANGHAI; 947 break; 948 case 8: 949 *Subtype = X86::AMDFAM10H_ISTANBUL; 950 break; 951 } 952 break; 953 case 20: 954 *Type = X86::AMD_BTVER1; 955 break; // "btver1"; 956 case 21: 957 *Type = X86::AMDFAM15H; 958 if (Model >= 0x60 && Model <= 0x7f) { 959 *Subtype = X86::AMDFAM15H_BDVER4; 960 break; // "bdver4"; 60h-7Fh: Excavator 961 } 962 if (Model >= 0x30 && Model <= 0x3f) { 963 *Subtype = X86::AMDFAM15H_BDVER3; 964 break; // "bdver3"; 30h-3Fh: Steamroller 965 } 966 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) { 967 *Subtype = X86::AMDFAM15H_BDVER2; 968 break; // "bdver2"; 02h, 10h-1Fh: Piledriver 969 } 970 if (Model <= 0x0f) { 971 *Subtype = X86::AMDFAM15H_BDVER1; 972 break; // "bdver1"; 00h-0Fh: Bulldozer 973 } 974 break; 975 case 22: 976 *Type = X86::AMD_BTVER2; 977 break; // "btver2" 978 case 23: 979 *Type = X86::AMDFAM17H; 980 if ((Model >= 0x30 && Model <= 0x3f) || Model == 0x71) { 981 *Subtype = X86::AMDFAM17H_ZNVER2; 982 break; // "znver2"; 30h-3fh, 71h: Zen2 983 } 984 if (Model <= 0x0f) { 985 *Subtype = X86::AMDFAM17H_ZNVER1; 986 break; // "znver1"; 00h-0Fh: Zen1 987 } 988 break; 989 default: 990 break; // "generic" 991 } 992 } 993 994 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 995 unsigned *FeaturesOut, unsigned *Features2Out, 996 unsigned *Features3Out) { 997 unsigned Features = 0; 998 unsigned Features2 = 0; 999 unsigned Features3 = 0; 1000 unsigned EAX, EBX; 1001 1002 auto setFeature = [&](unsigned F) { 1003 if (F < 32) 1004 Features |= 1U << (F & 0x1f); 1005 else if (F < 64) 1006 Features2 |= 1U << ((F - 32) & 0x1f); 1007 else if (F < 96) 1008 Features3 |= 1U << ((F - 64) & 0x1f); 1009 else 1010 llvm_unreachable("Unexpected FeatureBit"); 1011 }; 1012 1013 if ((EDX >> 15) & 1) 1014 setFeature(X86::FEATURE_CMOV); 1015 if ((EDX >> 23) & 1) 1016 setFeature(X86::FEATURE_MMX); 1017 if ((EDX >> 25) & 1) 1018 setFeature(X86::FEATURE_SSE); 1019 if ((EDX >> 26) & 1) 1020 setFeature(X86::FEATURE_SSE2); 1021 1022 if ((ECX >> 0) & 1) 1023 setFeature(X86::FEATURE_SSE3); 1024 if ((ECX >> 1) & 1) 1025 setFeature(X86::FEATURE_PCLMUL); 1026 if ((ECX >> 9) & 1) 1027 setFeature(X86::FEATURE_SSSE3); 1028 if ((ECX >> 12) & 1) 1029 setFeature(X86::FEATURE_FMA); 1030 if ((ECX >> 19) & 1) 1031 setFeature(X86::FEATURE_SSE4_1); 1032 if ((ECX >> 20) & 1) 1033 setFeature(X86::FEATURE_SSE4_2); 1034 if ((ECX >> 23) & 1) 1035 setFeature(X86::FEATURE_POPCNT); 1036 if ((ECX >> 25) & 1) 1037 setFeature(X86::FEATURE_AES); 1038 1039 if ((ECX >> 22) & 1) 1040 setFeature(X86::FEATURE_MOVBE); 1041 1042 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1043 // indicates that the AVX registers will be saved and restored on context 1044 // switch, then we have full AVX support. 1045 const unsigned AVXBits = (1 << 27) | (1 << 28); 1046 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 1047 ((EAX & 0x6) == 0x6); 1048 #if defined(__APPLE__) 1049 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1050 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1051 // set right now. 1052 bool HasAVX512Save = true; 1053 #else 1054 // AVX512 requires additional context to be saved by the OS. 1055 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 1056 #endif 1057 1058 if (HasAVX) 1059 setFeature(X86::FEATURE_AVX); 1060 1061 bool HasLeaf7 = 1062 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1063 1064 if (HasLeaf7 && ((EBX >> 3) & 1)) 1065 setFeature(X86::FEATURE_BMI); 1066 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 1067 setFeature(X86::FEATURE_AVX2); 1068 if (HasLeaf7 && ((EBX >> 8) & 1)) 1069 setFeature(X86::FEATURE_BMI2); 1070 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 1071 setFeature(X86::FEATURE_AVX512F); 1072 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 1073 setFeature(X86::FEATURE_AVX512DQ); 1074 if (HasLeaf7 && ((EBX >> 19) & 1)) 1075 setFeature(X86::FEATURE_ADX); 1076 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 1077 setFeature(X86::FEATURE_AVX512IFMA); 1078 if (HasLeaf7 && ((EBX >> 23) & 1)) 1079 setFeature(X86::FEATURE_CLFLUSHOPT); 1080 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 1081 setFeature(X86::FEATURE_AVX512PF); 1082 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 1083 setFeature(X86::FEATURE_AVX512ER); 1084 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 1085 setFeature(X86::FEATURE_AVX512CD); 1086 if (HasLeaf7 && ((EBX >> 29) & 1)) 1087 setFeature(X86::FEATURE_SHA); 1088 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 1089 setFeature(X86::FEATURE_AVX512BW); 1090 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 1091 setFeature(X86::FEATURE_AVX512VL); 1092 1093 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 1094 setFeature(X86::FEATURE_AVX512VBMI); 1095 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save) 1096 setFeature(X86::FEATURE_AVX512VBMI2); 1097 if (HasLeaf7 && ((ECX >> 8) & 1)) 1098 setFeature(X86::FEATURE_GFNI); 1099 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX) 1100 setFeature(X86::FEATURE_VPCLMULQDQ); 1101 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save) 1102 setFeature(X86::FEATURE_AVX512VNNI); 1103 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save) 1104 setFeature(X86::FEATURE_AVX512BITALG); 1105 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1106 setFeature(X86::FEATURE_AVX512VPOPCNTDQ); 1107 1108 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1109 setFeature(X86::FEATURE_AVX5124VNNIW); 1110 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1111 setFeature(X86::FEATURE_AVX5124FMAPS); 1112 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save) 1113 setFeature(X86::FEATURE_AVX512VP2INTERSECT); 1114 1115 bool HasLeaf7Subleaf1 = 1116 MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1117 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save) 1118 setFeature(X86::FEATURE_AVX512BF16); 1119 1120 unsigned MaxExtLevel; 1121 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1122 1123 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1124 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1125 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1126 setFeature(X86::FEATURE_SSE4_A); 1127 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1128 setFeature(X86::FEATURE_XOP); 1129 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1130 setFeature(X86::FEATURE_FMA4); 1131 1132 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1133 setFeature(X86::FEATURE_EM64T); 1134 1135 *FeaturesOut = Features; 1136 *Features2Out = Features2; 1137 *Features3Out = Features3; 1138 } 1139 1140 StringRef sys::getHostCPUName() { 1141 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1142 unsigned MaxLeaf, Vendor; 1143 1144 #if defined(__GNUC__) || defined(__clang__) 1145 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here 1146 // and simplify it to not invoke __cpuid (like cpu_model.c in 1147 // compiler-rt/lib/builtins/cpu_model.c? 1148 // Opting for the second option. 1149 if(!isCpuIdSupported()) 1150 return "generic"; 1151 #endif 1152 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) 1153 return "generic"; 1154 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1155 1156 unsigned Brand_id = EBX & 0xff; 1157 unsigned Family = 0, Model = 0; 1158 unsigned Features = 0, Features2 = 0, Features3 = 0; 1159 detectX86FamilyModel(EAX, &Family, &Model); 1160 getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2, &Features3); 1161 1162 unsigned Type = 0; 1163 unsigned Subtype = 0; 1164 1165 if (Vendor == SIG_INTEL) { 1166 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, 1167 Features2, Features3, &Type, &Subtype); 1168 } else if (Vendor == SIG_AMD) { 1169 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1170 } 1171 1172 // Check subtypes first since those are more specific. 1173 #define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \ 1174 if (Subtype == X86::ENUM) \ 1175 return ARCHNAME; 1176 #include "llvm/Support/X86TargetParser.def" 1177 1178 // Now check types. 1179 #define X86_CPU_TYPE(ARCHNAME, ENUM) \ 1180 if (Type == X86::ENUM) \ 1181 return ARCHNAME; 1182 #include "llvm/Support/X86TargetParser.def" 1183 1184 return "generic"; 1185 } 1186 1187 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1188 StringRef sys::getHostCPUName() { 1189 host_basic_info_data_t hostInfo; 1190 mach_msg_type_number_t infoCount; 1191 1192 infoCount = HOST_BASIC_INFO_COUNT; 1193 mach_port_t hostPort = mach_host_self(); 1194 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1195 &infoCount); 1196 mach_port_deallocate(mach_task_self(), hostPort); 1197 1198 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1199 return "generic"; 1200 1201 switch (hostInfo.cpu_subtype) { 1202 case CPU_SUBTYPE_POWERPC_601: 1203 return "601"; 1204 case CPU_SUBTYPE_POWERPC_602: 1205 return "602"; 1206 case CPU_SUBTYPE_POWERPC_603: 1207 return "603"; 1208 case CPU_SUBTYPE_POWERPC_603e: 1209 return "603e"; 1210 case CPU_SUBTYPE_POWERPC_603ev: 1211 return "603ev"; 1212 case CPU_SUBTYPE_POWERPC_604: 1213 return "604"; 1214 case CPU_SUBTYPE_POWERPC_604e: 1215 return "604e"; 1216 case CPU_SUBTYPE_POWERPC_620: 1217 return "620"; 1218 case CPU_SUBTYPE_POWERPC_750: 1219 return "750"; 1220 case CPU_SUBTYPE_POWERPC_7400: 1221 return "7400"; 1222 case CPU_SUBTYPE_POWERPC_7450: 1223 return "7450"; 1224 case CPU_SUBTYPE_POWERPC_970: 1225 return "970"; 1226 default:; 1227 } 1228 1229 return "generic"; 1230 } 1231 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1232 StringRef sys::getHostCPUName() { 1233 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1234 StringRef Content = P ? P->getBuffer() : ""; 1235 return detail::getHostCPUNameForPowerPC(Content); 1236 } 1237 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1238 StringRef sys::getHostCPUName() { 1239 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1240 StringRef Content = P ? P->getBuffer() : ""; 1241 return detail::getHostCPUNameForARM(Content); 1242 } 1243 #elif defined(__linux__) && defined(__s390x__) 1244 StringRef sys::getHostCPUName() { 1245 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1246 StringRef Content = P ? P->getBuffer() : ""; 1247 return detail::getHostCPUNameForS390x(Content); 1248 } 1249 #elif defined(__APPLE__) && defined(__aarch64__) 1250 StringRef sys::getHostCPUName() { 1251 return "cyclone"; 1252 } 1253 #elif defined(__APPLE__) && defined(__arm__) 1254 StringRef sys::getHostCPUName() { 1255 host_basic_info_data_t hostInfo; 1256 mach_msg_type_number_t infoCount; 1257 1258 infoCount = HOST_BASIC_INFO_COUNT; 1259 mach_port_t hostPort = mach_host_self(); 1260 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1261 &infoCount); 1262 mach_port_deallocate(mach_task_self(), hostPort); 1263 1264 if (hostInfo.cpu_type != CPU_TYPE_ARM) { 1265 assert(false && "CPUType not equal to ARM should not be possible on ARM"); 1266 return "generic"; 1267 } 1268 switch (hostInfo.cpu_subtype) { 1269 case CPU_SUBTYPE_ARM_V7S: 1270 return "swift"; 1271 default:; 1272 } 1273 1274 return "generic"; 1275 } 1276 #else 1277 StringRef sys::getHostCPUName() { return "generic"; } 1278 #endif 1279 1280 #if defined(__linux__) && defined(__x86_64__) 1281 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1282 // using the number of unique physical/core id pairs. The following 1283 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1284 int computeHostNumPhysicalCores() { 1285 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1286 // mmapped because it appears to have 0 size. 1287 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1288 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1289 if (std::error_code EC = Text.getError()) { 1290 llvm::errs() << "Can't read " 1291 << "/proc/cpuinfo: " << EC.message() << "\n"; 1292 return -1; 1293 } 1294 SmallVector<StringRef, 8> strs; 1295 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1296 /*KeepEmpty=*/false); 1297 int CurPhysicalId = -1; 1298 int CurCoreId = -1; 1299 SmallSet<std::pair<int, int>, 32> UniqueItems; 1300 for (auto &Line : strs) { 1301 Line = Line.trim(); 1302 if (!Line.startswith("physical id") && !Line.startswith("core id")) 1303 continue; 1304 std::pair<StringRef, StringRef> Data = Line.split(':'); 1305 auto Name = Data.first.trim(); 1306 auto Val = Data.second.trim(); 1307 if (Name == "physical id") { 1308 assert(CurPhysicalId == -1 && 1309 "Expected a core id before seeing another physical id"); 1310 Val.getAsInteger(10, CurPhysicalId); 1311 } 1312 if (Name == "core id") { 1313 assert(CurCoreId == -1 && 1314 "Expected a physical id before seeing another core id"); 1315 Val.getAsInteger(10, CurCoreId); 1316 } 1317 if (CurPhysicalId != -1 && CurCoreId != -1) { 1318 UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId)); 1319 CurPhysicalId = -1; 1320 CurCoreId = -1; 1321 } 1322 } 1323 return UniqueItems.size(); 1324 } 1325 #elif defined(__APPLE__) && defined(__x86_64__) 1326 #include <sys/param.h> 1327 #include <sys/sysctl.h> 1328 1329 // Gets the number of *physical cores* on the machine. 1330 int computeHostNumPhysicalCores() { 1331 uint32_t count; 1332 size_t len = sizeof(count); 1333 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1334 if (count < 1) { 1335 int nm[2]; 1336 nm[0] = CTL_HW; 1337 nm[1] = HW_AVAILCPU; 1338 sysctl(nm, 2, &count, &len, NULL, 0); 1339 if (count < 1) 1340 return -1; 1341 } 1342 return count; 1343 } 1344 #elif defined(_WIN32) && LLVM_ENABLE_THREADS != 0 1345 // Defined in llvm/lib/Support/Windows/Threading.inc 1346 int computeHostNumPhysicalCores(); 1347 #else 1348 // On other systems, return -1 to indicate unknown. 1349 static int computeHostNumPhysicalCores() { return -1; } 1350 #endif 1351 1352 int sys::getHostNumPhysicalCores() { 1353 static int NumCores = computeHostNumPhysicalCores(); 1354 return NumCores; 1355 } 1356 1357 #if defined(__i386__) || defined(_M_IX86) || \ 1358 defined(__x86_64__) || defined(_M_X64) 1359 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1360 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1361 unsigned MaxLevel; 1362 union { 1363 unsigned u[3]; 1364 char c[12]; 1365 } text; 1366 1367 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1368 MaxLevel < 1) 1369 return false; 1370 1371 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1372 1373 Features["cx8"] = (EDX >> 8) & 1; 1374 Features["cmov"] = (EDX >> 15) & 1; 1375 Features["mmx"] = (EDX >> 23) & 1; 1376 Features["fxsr"] = (EDX >> 24) & 1; 1377 Features["sse"] = (EDX >> 25) & 1; 1378 Features["sse2"] = (EDX >> 26) & 1; 1379 1380 Features["sse3"] = (ECX >> 0) & 1; 1381 Features["pclmul"] = (ECX >> 1) & 1; 1382 Features["ssse3"] = (ECX >> 9) & 1; 1383 Features["cx16"] = (ECX >> 13) & 1; 1384 Features["sse4.1"] = (ECX >> 19) & 1; 1385 Features["sse4.2"] = (ECX >> 20) & 1; 1386 Features["movbe"] = (ECX >> 22) & 1; 1387 Features["popcnt"] = (ECX >> 23) & 1; 1388 Features["aes"] = (ECX >> 25) & 1; 1389 Features["rdrnd"] = (ECX >> 30) & 1; 1390 1391 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1392 // indicates that the AVX registers will be saved and restored on context 1393 // switch, then we have full AVX support. 1394 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1395 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1396 #if defined(__APPLE__) 1397 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1398 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1399 // set right now. 1400 bool HasAVX512Save = true; 1401 #else 1402 // AVX512 requires additional context to be saved by the OS. 1403 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1404 #endif 1405 1406 Features["avx"] = HasAVXSave; 1407 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave; 1408 // Only enable XSAVE if OS has enabled support for saving YMM state. 1409 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave; 1410 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave; 1411 1412 unsigned MaxExtLevel; 1413 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1414 1415 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1416 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1417 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1); 1418 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1419 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1420 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1421 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1422 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1423 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1424 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1425 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1426 1427 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1); 1428 1429 // Miscellaneous memory related features, detected by 1430 // using the 0x80000008 leaf of the CPUID instruction 1431 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1432 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX); 1433 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1434 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1); 1435 1436 bool HasLeaf7 = 1437 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1438 1439 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1440 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1441 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1442 // AVX2 is only supported if we have the OS save support from AVX. 1443 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave; 1444 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1445 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1446 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1447 // AVX512 is only supported if the OS supports the context save for it. 1448 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1449 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1450 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1451 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1452 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1453 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1454 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1455 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1456 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1457 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1458 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1459 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1460 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1461 1462 Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1); 1463 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1464 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1465 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1); 1466 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save; 1467 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1); 1468 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1); 1469 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave; 1470 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave; 1471 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save; 1472 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save; 1473 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1474 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1); 1475 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1); 1476 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1); 1477 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1); 1478 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1); 1479 1480 // There are two CPUID leafs which information associated with the pconfig 1481 // instruction: 1482 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th 1483 // bit of EDX), while the EAX=0x1b leaf returns information on the 1484 // availability of specific pconfig leafs. 1485 // The target feature here only refers to the the first of these two. 1486 // Users might need to check for the availability of specific pconfig 1487 // leaves using cpuid, since that information is ignored while 1488 // detecting features using the "-march=native" flag. 1489 // For more info, see X86 ISA docs. 1490 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1); 1491 bool HasLeaf7Subleaf1 = 1492 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1493 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save; 1494 1495 bool HasLeafD = MaxLevel >= 0xd && 1496 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1497 1498 // Only enable XSAVE if OS has enabled support for saving YMM state. 1499 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave; 1500 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave; 1501 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave; 1502 1503 bool HasLeaf14 = MaxLevel >= 0x14 && 1504 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX); 1505 1506 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1); 1507 1508 return true; 1509 } 1510 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1511 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1512 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1513 if (!P) 1514 return false; 1515 1516 SmallVector<StringRef, 32> Lines; 1517 P->getBuffer().split(Lines, "\n"); 1518 1519 SmallVector<StringRef, 32> CPUFeatures; 1520 1521 // Look for the CPU features. 1522 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1523 if (Lines[I].startswith("Features")) { 1524 Lines[I].split(CPUFeatures, ' '); 1525 break; 1526 } 1527 1528 #if defined(__aarch64__) 1529 // Keep track of which crypto features we have seen 1530 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1531 uint32_t crypto = 0; 1532 #endif 1533 1534 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1535 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1536 #if defined(__aarch64__) 1537 .Case("asimd", "neon") 1538 .Case("fp", "fp-armv8") 1539 .Case("crc32", "crc") 1540 #else 1541 .Case("half", "fp16") 1542 .Case("neon", "neon") 1543 .Case("vfpv3", "vfp3") 1544 .Case("vfpv3d16", "d16") 1545 .Case("vfpv4", "vfp4") 1546 .Case("idiva", "hwdiv-arm") 1547 .Case("idivt", "hwdiv") 1548 #endif 1549 .Default(""); 1550 1551 #if defined(__aarch64__) 1552 // We need to check crypto separately since we need all of the crypto 1553 // extensions to enable the subtarget feature 1554 if (CPUFeatures[I] == "aes") 1555 crypto |= CAP_AES; 1556 else if (CPUFeatures[I] == "pmull") 1557 crypto |= CAP_PMULL; 1558 else if (CPUFeatures[I] == "sha1") 1559 crypto |= CAP_SHA1; 1560 else if (CPUFeatures[I] == "sha2") 1561 crypto |= CAP_SHA2; 1562 #endif 1563 1564 if (LLVMFeatureStr != "") 1565 Features[LLVMFeatureStr] = true; 1566 } 1567 1568 #if defined(__aarch64__) 1569 // If we have all crypto bits we can add the feature 1570 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1571 Features["crypto"] = true; 1572 #endif 1573 1574 return true; 1575 } 1576 #elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64)) 1577 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1578 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE)) 1579 Features["neon"] = true; 1580 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE)) 1581 Features["crc"] = true; 1582 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) 1583 Features["crypto"] = true; 1584 1585 return true; 1586 } 1587 #else 1588 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1589 #endif 1590 1591 std::string sys::getProcessTriple() { 1592 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1593 Triple PT(Triple::normalize(TargetTripleString)); 1594 1595 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1596 PT = PT.get64BitArchVariant(); 1597 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1598 PT = PT.get32BitArchVariant(); 1599 1600 return PT.str(); 1601 } 1602