1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the operating system Host concept. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/Host.h" 14 #include "llvm/ADT/SmallSet.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringMap.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/llvm-config.h" 21 #include "llvm/Support/BCD.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/FileSystem.h" 24 #include "llvm/Support/MemoryBuffer.h" 25 #include "llvm/Support/X86TargetParser.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <assert.h> 28 #include <string.h> 29 30 // Include the platform-specific parts of this class. 31 #ifdef LLVM_ON_UNIX 32 #include "Unix/Host.inc" 33 #include <sched.h> 34 #endif 35 #ifdef _WIN32 36 #include "Windows/Host.inc" 37 #endif 38 #ifdef _MSC_VER 39 #include <intrin.h> 40 #endif 41 #if defined(__APPLE__) && (!defined(__x86_64__)) 42 #include <mach/host_info.h> 43 #include <mach/mach.h> 44 #include <mach/mach_host.h> 45 #include <mach/machine.h> 46 #endif 47 #ifdef _AIX 48 #include <sys/systemcfg.h> 49 #endif 50 51 #define DEBUG_TYPE "host-detection" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // Implementations of the CPU detection routines 56 // 57 //===----------------------------------------------------------------------===// 58 59 using namespace llvm; 60 61 static std::unique_ptr<llvm::MemoryBuffer> 62 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 63 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 64 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 65 if (std::error_code EC = Text.getError()) { 66 llvm::errs() << "Can't read " 67 << "/proc/cpuinfo: " << EC.message() << "\n"; 68 return nullptr; 69 } 70 return std::move(*Text); 71 } 72 73 StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) { 74 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 75 // and so we must use an operating-system interface to determine the current 76 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 77 const char *generic = "generic"; 78 79 // The cpu line is second (after the 'processor: 0' line), so if this 80 // buffer is too small then something has changed (or is wrong). 81 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 82 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 83 84 StringRef::const_iterator CIP = CPUInfoStart; 85 86 StringRef::const_iterator CPUStart = nullptr; 87 size_t CPULen = 0; 88 89 // We need to find the first line which starts with cpu, spaces, and a colon. 90 // After the colon, there may be some additional spaces and then the cpu type. 91 while (CIP < CPUInfoEnd && CPUStart == nullptr) { 92 if (CIP < CPUInfoEnd && *CIP == '\n') 93 ++CIP; 94 95 if (CIP < CPUInfoEnd && *CIP == 'c') { 96 ++CIP; 97 if (CIP < CPUInfoEnd && *CIP == 'p') { 98 ++CIP; 99 if (CIP < CPUInfoEnd && *CIP == 'u') { 100 ++CIP; 101 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 102 ++CIP; 103 104 if (CIP < CPUInfoEnd && *CIP == ':') { 105 ++CIP; 106 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 107 ++CIP; 108 109 if (CIP < CPUInfoEnd) { 110 CPUStart = CIP; 111 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 112 *CIP != ',' && *CIP != '\n')) 113 ++CIP; 114 CPULen = CIP - CPUStart; 115 } 116 } 117 } 118 } 119 } 120 121 if (CPUStart == nullptr) 122 while (CIP < CPUInfoEnd && *CIP != '\n') 123 ++CIP; 124 } 125 126 if (CPUStart == nullptr) 127 return generic; 128 129 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 130 .Case("604e", "604e") 131 .Case("604", "604") 132 .Case("7400", "7400") 133 .Case("7410", "7400") 134 .Case("7447", "7400") 135 .Case("7455", "7450") 136 .Case("G4", "g4") 137 .Case("POWER4", "970") 138 .Case("PPC970FX", "970") 139 .Case("PPC970MP", "970") 140 .Case("G5", "g5") 141 .Case("POWER5", "g5") 142 .Case("A2", "a2") 143 .Case("POWER6", "pwr6") 144 .Case("POWER7", "pwr7") 145 .Case("POWER8", "pwr8") 146 .Case("POWER8E", "pwr8") 147 .Case("POWER8NVL", "pwr8") 148 .Case("POWER9", "pwr9") 149 .Case("POWER10", "pwr10") 150 // FIXME: If we get a simulator or machine with the capabilities of 151 // mcpu=future, we should revisit this and add the name reported by the 152 // simulator/machine. 153 .Default(generic); 154 } 155 156 StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { 157 // The cpuid register on arm is not accessible from user space. On Linux, 158 // it is exposed through the /proc/cpuinfo file. 159 160 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 161 // in all cases. 162 SmallVector<StringRef, 32> Lines; 163 ProcCpuinfoContent.split(Lines, "\n"); 164 165 // Look for the CPU implementer line. 166 StringRef Implementer; 167 StringRef Hardware; 168 StringRef Part; 169 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 170 if (Lines[I].startswith("CPU implementer")) 171 Implementer = Lines[I].substr(15).ltrim("\t :"); 172 if (Lines[I].startswith("Hardware")) 173 Hardware = Lines[I].substr(8).ltrim("\t :"); 174 if (Lines[I].startswith("CPU part")) 175 Part = Lines[I].substr(8).ltrim("\t :"); 176 } 177 178 if (Implementer == "0x41") { // ARM Ltd. 179 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 180 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 181 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 182 return "cortex-a53"; 183 184 185 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 186 // values correspond to the "Part number" in the CP15/c0 register. The 187 // contents are specified in the various processor manuals. 188 // This corresponds to the Main ID Register in Technical Reference Manuals. 189 // and is used in programs like sys-utils 190 return StringSwitch<const char *>(Part) 191 .Case("0x926", "arm926ej-s") 192 .Case("0xb02", "mpcore") 193 .Case("0xb36", "arm1136j-s") 194 .Case("0xb56", "arm1156t2-s") 195 .Case("0xb76", "arm1176jz-s") 196 .Case("0xc08", "cortex-a8") 197 .Case("0xc09", "cortex-a9") 198 .Case("0xc0f", "cortex-a15") 199 .Case("0xc20", "cortex-m0") 200 .Case("0xc23", "cortex-m3") 201 .Case("0xc24", "cortex-m4") 202 .Case("0xd22", "cortex-m55") 203 .Case("0xd02", "cortex-a34") 204 .Case("0xd04", "cortex-a35") 205 .Case("0xd03", "cortex-a53") 206 .Case("0xd07", "cortex-a57") 207 .Case("0xd08", "cortex-a72") 208 .Case("0xd09", "cortex-a73") 209 .Case("0xd0a", "cortex-a75") 210 .Case("0xd0b", "cortex-a76") 211 .Case("0xd0d", "cortex-a77") 212 .Case("0xd41", "cortex-a78") 213 .Case("0xd44", "cortex-x1") 214 .Case("0xd4c", "cortex-x1c") 215 .Case("0xd0c", "neoverse-n1") 216 .Case("0xd49", "neoverse-n2") 217 .Case("0xd40", "neoverse-v1") 218 .Default("generic"); 219 } 220 221 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium. 222 return StringSwitch<const char *>(Part) 223 .Case("0x516", "thunderx2t99") 224 .Case("0x0516", "thunderx2t99") 225 .Case("0xaf", "thunderx2t99") 226 .Case("0x0af", "thunderx2t99") 227 .Case("0xa1", "thunderxt88") 228 .Case("0x0a1", "thunderxt88") 229 .Default("generic"); 230 } 231 232 if (Implementer == "0x46") { // Fujitsu Ltd. 233 return StringSwitch<const char *>(Part) 234 .Case("0x001", "a64fx") 235 .Default("generic"); 236 } 237 238 if (Implementer == "0x4e") { // NVIDIA Corporation 239 return StringSwitch<const char *>(Part) 240 .Case("0x004", "carmel") 241 .Default("generic"); 242 } 243 244 if (Implementer == "0x48") // HiSilicon Technologies, Inc. 245 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 246 // values correspond to the "Part number" in the CP15/c0 register. The 247 // contents are specified in the various processor manuals. 248 return StringSwitch<const char *>(Part) 249 .Case("0xd01", "tsv110") 250 .Default("generic"); 251 252 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 253 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 254 // values correspond to the "Part number" in the CP15/c0 register. The 255 // contents are specified in the various processor manuals. 256 return StringSwitch<const char *>(Part) 257 .Case("0x06f", "krait") // APQ8064 258 .Case("0x201", "kryo") 259 .Case("0x205", "kryo") 260 .Case("0x211", "kryo") 261 .Case("0x800", "cortex-a73") // Kryo 2xx Gold 262 .Case("0x801", "cortex-a73") // Kryo 2xx Silver 263 .Case("0x802", "cortex-a75") // Kryo 3xx Gold 264 .Case("0x803", "cortex-a75") // Kryo 3xx Silver 265 .Case("0x804", "cortex-a76") // Kryo 4xx Gold 266 .Case("0x805", "cortex-a76") // Kryo 4xx/5xx Silver 267 .Case("0xc00", "falkor") 268 .Case("0xc01", "saphira") 269 .Default("generic"); 270 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. 271 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow 272 // any predictive pattern across variants and parts. 273 unsigned Variant = 0, Part = 0; 274 275 // Look for the CPU variant line, whose value is a 1 digit hexadecimal 276 // number, corresponding to the Variant bits in the CP15/C0 register. 277 for (auto I : Lines) 278 if (I.consume_front("CPU variant")) 279 I.ltrim("\t :").getAsInteger(0, Variant); 280 281 // Look for the CPU part line, whose value is a 3 digit hexadecimal 282 // number, corresponding to the PartNum bits in the CP15/C0 register. 283 for (auto I : Lines) 284 if (I.consume_front("CPU part")) 285 I.ltrim("\t :").getAsInteger(0, Part); 286 287 unsigned Exynos = (Variant << 12) | Part; 288 switch (Exynos) { 289 default: 290 // Default by falling through to Exynos M3. 291 LLVM_FALLTHROUGH; 292 case 0x1002: 293 return "exynos-m3"; 294 case 0x1003: 295 return "exynos-m4"; 296 } 297 } 298 299 return "generic"; 300 } 301 302 namespace { 303 StringRef getCPUNameFromS390Model(unsigned int Id, bool HaveVectorSupport) { 304 switch (Id) { 305 case 2064: // z900 not supported by LLVM 306 case 2066: 307 case 2084: // z990 not supported by LLVM 308 case 2086: 309 case 2094: // z9-109 not supported by LLVM 310 case 2096: 311 return "generic"; 312 case 2097: 313 case 2098: 314 return "z10"; 315 case 2817: 316 case 2818: 317 return "z196"; 318 case 2827: 319 case 2828: 320 return "zEC12"; 321 case 2964: 322 case 2965: 323 return HaveVectorSupport? "z13" : "zEC12"; 324 case 3906: 325 case 3907: 326 return HaveVectorSupport? "z14" : "zEC12"; 327 case 8561: 328 case 8562: 329 return HaveVectorSupport? "z15" : "zEC12"; 330 case 3931: 331 case 3932: 332 default: 333 return HaveVectorSupport? "arch14" : "zEC12"; 334 } 335 } 336 } // end anonymous namespace 337 338 StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { 339 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 340 341 // The "processor 0:" line comes after a fair amount of other information, 342 // including a cache breakdown, but this should be plenty. 343 SmallVector<StringRef, 32> Lines; 344 ProcCpuinfoContent.split(Lines, "\n"); 345 346 // Look for the CPU features. 347 SmallVector<StringRef, 32> CPUFeatures; 348 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 349 if (Lines[I].startswith("features")) { 350 size_t Pos = Lines[I].find(':'); 351 if (Pos != StringRef::npos) { 352 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 353 break; 354 } 355 } 356 357 // We need to check for the presence of vector support independently of 358 // the machine type, since we may only use the vector register set when 359 // supported by the kernel (and hypervisor). 360 bool HaveVectorSupport = false; 361 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 362 if (CPUFeatures[I] == "vx") 363 HaveVectorSupport = true; 364 } 365 366 // Now check the processor machine type. 367 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 368 if (Lines[I].startswith("processor ")) { 369 size_t Pos = Lines[I].find("machine = "); 370 if (Pos != StringRef::npos) { 371 Pos += sizeof("machine = ") - 1; 372 unsigned int Id; 373 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) 374 return getCPUNameFromS390Model(Id, HaveVectorSupport); 375 } 376 break; 377 } 378 } 379 380 return "generic"; 381 } 382 383 StringRef sys::detail::getHostCPUNameForBPF() { 384 #if !defined(__linux__) || !defined(__x86_64__) 385 return "generic"; 386 #else 387 uint8_t v3_insns[40] __attribute__ ((aligned (8))) = 388 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 389 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 390 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 391 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 392 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 393 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 394 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 395 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 396 /* BPF_EXIT_INSN() */ 397 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 398 399 uint8_t v2_insns[40] __attribute__ ((aligned (8))) = 400 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 401 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 402 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 403 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 404 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 405 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 406 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 407 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 408 /* BPF_EXIT_INSN() */ 409 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 410 411 struct bpf_prog_load_attr { 412 uint32_t prog_type; 413 uint32_t insn_cnt; 414 uint64_t insns; 415 uint64_t license; 416 uint32_t log_level; 417 uint32_t log_size; 418 uint64_t log_buf; 419 uint32_t kern_version; 420 uint32_t prog_flags; 421 } attr = {}; 422 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 423 attr.insn_cnt = 5; 424 attr.insns = (uint64_t)v3_insns; 425 attr.license = (uint64_t)"DUMMY"; 426 427 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, 428 sizeof(attr)); 429 if (fd >= 0) { 430 close(fd); 431 return "v3"; 432 } 433 434 /* Clear the whole attr in case its content changed by syscall. */ 435 memset(&attr, 0, sizeof(attr)); 436 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 437 attr.insn_cnt = 5; 438 attr.insns = (uint64_t)v2_insns; 439 attr.license = (uint64_t)"DUMMY"; 440 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 441 if (fd >= 0) { 442 close(fd); 443 return "v2"; 444 } 445 return "v1"; 446 #endif 447 } 448 449 #if defined(__i386__) || defined(_M_IX86) || \ 450 defined(__x86_64__) || defined(_M_X64) 451 452 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 453 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 454 // support. Consequently, for i386, the presence of CPUID is checked first 455 // via the corresponding eflags bit. 456 // Removal of cpuid.h header motivated by PR30384 457 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 458 // or test-suite, but are used in external projects e.g. libstdcxx 459 static bool isCpuIdSupported() { 460 #if defined(__GNUC__) || defined(__clang__) 461 #if defined(__i386__) 462 int __cpuid_supported; 463 __asm__(" pushfl\n" 464 " popl %%eax\n" 465 " movl %%eax,%%ecx\n" 466 " xorl $0x00200000,%%eax\n" 467 " pushl %%eax\n" 468 " popfl\n" 469 " pushfl\n" 470 " popl %%eax\n" 471 " movl $0,%0\n" 472 " cmpl %%eax,%%ecx\n" 473 " je 1f\n" 474 " movl $1,%0\n" 475 "1:" 476 : "=r"(__cpuid_supported) 477 : 478 : "eax", "ecx"); 479 if (!__cpuid_supported) 480 return false; 481 #endif 482 return true; 483 #endif 484 return true; 485 } 486 487 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 488 /// the specified arguments. If we can't run cpuid on the host, return true. 489 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 490 unsigned *rECX, unsigned *rEDX) { 491 #if defined(__GNUC__) || defined(__clang__) 492 #if defined(__x86_64__) 493 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 494 // FIXME: should we save this for Clang? 495 __asm__("movq\t%%rbx, %%rsi\n\t" 496 "cpuid\n\t" 497 "xchgq\t%%rbx, %%rsi\n\t" 498 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 499 : "a"(value)); 500 return false; 501 #elif defined(__i386__) 502 __asm__("movl\t%%ebx, %%esi\n\t" 503 "cpuid\n\t" 504 "xchgl\t%%ebx, %%esi\n\t" 505 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 506 : "a"(value)); 507 return false; 508 #else 509 return true; 510 #endif 511 #elif defined(_MSC_VER) 512 // The MSVC intrinsic is portable across x86 and x64. 513 int registers[4]; 514 __cpuid(registers, value); 515 *rEAX = registers[0]; 516 *rEBX = registers[1]; 517 *rECX = registers[2]; 518 *rEDX = registers[3]; 519 return false; 520 #else 521 return true; 522 #endif 523 } 524 525 namespace llvm { 526 namespace sys { 527 namespace detail { 528 namespace x86 { 529 530 VendorSignatures getVendorSignature(unsigned *MaxLeaf) { 531 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 532 if (MaxLeaf == nullptr) 533 MaxLeaf = &EAX; 534 else 535 *MaxLeaf = 0; 536 537 if (!isCpuIdSupported()) 538 return VendorSignatures::UNKNOWN; 539 540 if (getX86CpuIDAndInfo(0, MaxLeaf, &EBX, &ECX, &EDX) || *MaxLeaf < 1) 541 return VendorSignatures::UNKNOWN; 542 543 // "Genu ineI ntel" 544 if (EBX == 0x756e6547 && EDX == 0x49656e69 && ECX == 0x6c65746e) 545 return VendorSignatures::GENUINE_INTEL; 546 547 // "Auth enti cAMD" 548 if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163) 549 return VendorSignatures::AUTHENTIC_AMD; 550 551 return VendorSignatures::UNKNOWN; 552 } 553 554 } // namespace x86 555 } // namespace detail 556 } // namespace sys 557 } // namespace llvm 558 559 using namespace llvm::sys::detail::x86; 560 561 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 562 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 563 /// return true. 564 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 565 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 566 unsigned *rEDX) { 567 #if defined(__GNUC__) || defined(__clang__) 568 #if defined(__x86_64__) 569 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 570 // FIXME: should we save this for Clang? 571 __asm__("movq\t%%rbx, %%rsi\n\t" 572 "cpuid\n\t" 573 "xchgq\t%%rbx, %%rsi\n\t" 574 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 575 : "a"(value), "c"(subleaf)); 576 return false; 577 #elif defined(__i386__) 578 __asm__("movl\t%%ebx, %%esi\n\t" 579 "cpuid\n\t" 580 "xchgl\t%%ebx, %%esi\n\t" 581 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 582 : "a"(value), "c"(subleaf)); 583 return false; 584 #else 585 return true; 586 #endif 587 #elif defined(_MSC_VER) 588 int registers[4]; 589 __cpuidex(registers, value, subleaf); 590 *rEAX = registers[0]; 591 *rEBX = registers[1]; 592 *rECX = registers[2]; 593 *rEDX = registers[3]; 594 return false; 595 #else 596 return true; 597 #endif 598 } 599 600 // Read control register 0 (XCR0). Used to detect features such as AVX. 601 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 602 #if defined(__GNUC__) || defined(__clang__) 603 // Check xgetbv; this uses a .byte sequence instead of the instruction 604 // directly because older assemblers do not include support for xgetbv and 605 // there is no easy way to conditionally compile based on the assembler used. 606 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 607 return false; 608 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 609 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 610 *rEAX = Result; 611 *rEDX = Result >> 32; 612 return false; 613 #else 614 return true; 615 #endif 616 } 617 618 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 619 unsigned *Model) { 620 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 621 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 622 if (*Family == 6 || *Family == 0xf) { 623 if (*Family == 0xf) 624 // Examine extended family ID if family ID is F. 625 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 626 // Examine extended model ID if family ID is 6 or F. 627 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 628 } 629 } 630 631 static StringRef 632 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 633 const unsigned *Features, 634 unsigned *Type, unsigned *Subtype) { 635 auto testFeature = [&](unsigned F) { 636 return (Features[F / 32] & (1U << (F % 32))) != 0; 637 }; 638 639 StringRef CPU; 640 641 switch (Family) { 642 case 3: 643 CPU = "i386"; 644 break; 645 case 4: 646 CPU = "i486"; 647 break; 648 case 5: 649 if (testFeature(X86::FEATURE_MMX)) { 650 CPU = "pentium-mmx"; 651 break; 652 } 653 CPU = "pentium"; 654 break; 655 case 6: 656 switch (Model) { 657 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 658 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 659 // mobile processor, Intel Core 2 Extreme processor, Intel 660 // Pentium Dual-Core processor, Intel Xeon processor, model 661 // 0Fh. All processors are manufactured using the 65 nm process. 662 case 0x16: // Intel Celeron processor model 16h. All processors are 663 // manufactured using the 65 nm process 664 CPU = "core2"; 665 *Type = X86::INTEL_CORE2; 666 break; 667 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 668 // 17h. All processors are manufactured using the 45 nm process. 669 // 670 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 671 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 672 // the 45 nm process. 673 CPU = "penryn"; 674 *Type = X86::INTEL_CORE2; 675 break; 676 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 677 // processors are manufactured using the 45 nm process. 678 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 679 // As found in a Summer 2010 model iMac. 680 case 0x1f: 681 case 0x2e: // Nehalem EX 682 CPU = "nehalem"; 683 *Type = X86::INTEL_COREI7; 684 *Subtype = X86::INTEL_COREI7_NEHALEM; 685 break; 686 case 0x25: // Intel Core i7, laptop version. 687 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 688 // processors are manufactured using the 32 nm process. 689 case 0x2f: // Westmere EX 690 CPU = "westmere"; 691 *Type = X86::INTEL_COREI7; 692 *Subtype = X86::INTEL_COREI7_WESTMERE; 693 break; 694 case 0x2a: // Intel Core i7 processor. All processors are manufactured 695 // using the 32 nm process. 696 case 0x2d: 697 CPU = "sandybridge"; 698 *Type = X86::INTEL_COREI7; 699 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 700 break; 701 case 0x3a: 702 case 0x3e: // Ivy Bridge EP 703 CPU = "ivybridge"; 704 *Type = X86::INTEL_COREI7; 705 *Subtype = X86::INTEL_COREI7_IVYBRIDGE; 706 break; 707 708 // Haswell: 709 case 0x3c: 710 case 0x3f: 711 case 0x45: 712 case 0x46: 713 CPU = "haswell"; 714 *Type = X86::INTEL_COREI7; 715 *Subtype = X86::INTEL_COREI7_HASWELL; 716 break; 717 718 // Broadwell: 719 case 0x3d: 720 case 0x47: 721 case 0x4f: 722 case 0x56: 723 CPU = "broadwell"; 724 *Type = X86::INTEL_COREI7; 725 *Subtype = X86::INTEL_COREI7_BROADWELL; 726 break; 727 728 // Skylake: 729 case 0x4e: // Skylake mobile 730 case 0x5e: // Skylake desktop 731 case 0x8e: // Kaby Lake mobile 732 case 0x9e: // Kaby Lake desktop 733 case 0xa5: // Comet Lake-H/S 734 case 0xa6: // Comet Lake-U 735 CPU = "skylake"; 736 *Type = X86::INTEL_COREI7; 737 *Subtype = X86::INTEL_COREI7_SKYLAKE; 738 break; 739 740 // Rocketlake: 741 case 0xa7: 742 CPU = "rocketlake"; 743 *Type = X86::INTEL_COREI7; 744 *Subtype = X86::INTEL_COREI7_ROCKETLAKE; 745 break; 746 747 // Skylake Xeon: 748 case 0x55: 749 *Type = X86::INTEL_COREI7; 750 if (testFeature(X86::FEATURE_AVX512BF16)) { 751 CPU = "cooperlake"; 752 *Subtype = X86::INTEL_COREI7_COOPERLAKE; 753 } else if (testFeature(X86::FEATURE_AVX512VNNI)) { 754 CPU = "cascadelake"; 755 *Subtype = X86::INTEL_COREI7_CASCADELAKE; 756 } else { 757 CPU = "skylake-avx512"; 758 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; 759 } 760 break; 761 762 // Cannonlake: 763 case 0x66: 764 CPU = "cannonlake"; 765 *Type = X86::INTEL_COREI7; 766 *Subtype = X86::INTEL_COREI7_CANNONLAKE; 767 break; 768 769 // Icelake: 770 case 0x7d: 771 case 0x7e: 772 CPU = "icelake-client"; 773 *Type = X86::INTEL_COREI7; 774 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; 775 break; 776 777 // Tigerlake: 778 case 0x8c: 779 case 0x8d: 780 CPU = "tigerlake"; 781 *Type = X86::INTEL_COREI7; 782 *Subtype = X86::INTEL_COREI7_TIGERLAKE; 783 break; 784 785 // Alderlake: 786 case 0x97: 787 case 0x9a: 788 CPU = "alderlake"; 789 *Type = X86::INTEL_COREI7; 790 *Subtype = X86::INTEL_COREI7_ALDERLAKE; 791 break; 792 793 // Icelake Xeon: 794 case 0x6a: 795 case 0x6c: 796 CPU = "icelake-server"; 797 *Type = X86::INTEL_COREI7; 798 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; 799 break; 800 801 // Sapphire Rapids: 802 case 0x8f: 803 CPU = "sapphirerapids"; 804 *Type = X86::INTEL_COREI7; 805 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS; 806 break; 807 808 case 0x1c: // Most 45 nm Intel Atom processors 809 case 0x26: // 45 nm Atom Lincroft 810 case 0x27: // 32 nm Atom Medfield 811 case 0x35: // 32 nm Atom Midview 812 case 0x36: // 32 nm Atom Midview 813 CPU = "bonnell"; 814 *Type = X86::INTEL_BONNELL; 815 break; 816 817 // Atom Silvermont codes from the Intel software optimization guide. 818 case 0x37: 819 case 0x4a: 820 case 0x4d: 821 case 0x5a: 822 case 0x5d: 823 case 0x4c: // really airmont 824 CPU = "silvermont"; 825 *Type = X86::INTEL_SILVERMONT; 826 break; 827 // Goldmont: 828 case 0x5c: // Apollo Lake 829 case 0x5f: // Denverton 830 CPU = "goldmont"; 831 *Type = X86::INTEL_GOLDMONT; 832 break; 833 case 0x7a: 834 CPU = "goldmont-plus"; 835 *Type = X86::INTEL_GOLDMONT_PLUS; 836 break; 837 case 0x86: 838 CPU = "tremont"; 839 *Type = X86::INTEL_TREMONT; 840 break; 841 842 // Xeon Phi (Knights Landing + Knights Mill): 843 case 0x57: 844 CPU = "knl"; 845 *Type = X86::INTEL_KNL; 846 break; 847 case 0x85: 848 CPU = "knm"; 849 *Type = X86::INTEL_KNM; 850 break; 851 852 default: // Unknown family 6 CPU, try to guess. 853 // Don't both with Type/Subtype here, they aren't used by the caller. 854 // They're used above to keep the code in sync with compiler-rt. 855 // TODO detect tigerlake host from model 856 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) { 857 CPU = "tigerlake"; 858 } else if (testFeature(X86::FEATURE_AVX512VBMI2)) { 859 CPU = "icelake-client"; 860 } else if (testFeature(X86::FEATURE_AVX512VBMI)) { 861 CPU = "cannonlake"; 862 } else if (testFeature(X86::FEATURE_AVX512BF16)) { 863 CPU = "cooperlake"; 864 } else if (testFeature(X86::FEATURE_AVX512VNNI)) { 865 CPU = "cascadelake"; 866 } else if (testFeature(X86::FEATURE_AVX512VL)) { 867 CPU = "skylake-avx512"; 868 } else if (testFeature(X86::FEATURE_AVX512ER)) { 869 CPU = "knl"; 870 } else if (testFeature(X86::FEATURE_CLFLUSHOPT)) { 871 if (testFeature(X86::FEATURE_SHA)) 872 CPU = "goldmont"; 873 else 874 CPU = "skylake"; 875 } else if (testFeature(X86::FEATURE_ADX)) { 876 CPU = "broadwell"; 877 } else if (testFeature(X86::FEATURE_AVX2)) { 878 CPU = "haswell"; 879 } else if (testFeature(X86::FEATURE_AVX)) { 880 CPU = "sandybridge"; 881 } else if (testFeature(X86::FEATURE_SSE4_2)) { 882 if (testFeature(X86::FEATURE_MOVBE)) 883 CPU = "silvermont"; 884 else 885 CPU = "nehalem"; 886 } else if (testFeature(X86::FEATURE_SSE4_1)) { 887 CPU = "penryn"; 888 } else if (testFeature(X86::FEATURE_SSSE3)) { 889 if (testFeature(X86::FEATURE_MOVBE)) 890 CPU = "bonnell"; 891 else 892 CPU = "core2"; 893 } else if (testFeature(X86::FEATURE_64BIT)) { 894 CPU = "core2"; 895 } else if (testFeature(X86::FEATURE_SSE3)) { 896 CPU = "yonah"; 897 } else if (testFeature(X86::FEATURE_SSE2)) { 898 CPU = "pentium-m"; 899 } else if (testFeature(X86::FEATURE_SSE)) { 900 CPU = "pentium3"; 901 } else if (testFeature(X86::FEATURE_MMX)) { 902 CPU = "pentium2"; 903 } else { 904 CPU = "pentiumpro"; 905 } 906 break; 907 } 908 break; 909 case 15: { 910 if (testFeature(X86::FEATURE_64BIT)) { 911 CPU = "nocona"; 912 break; 913 } 914 if (testFeature(X86::FEATURE_SSE3)) { 915 CPU = "prescott"; 916 break; 917 } 918 CPU = "pentium4"; 919 break; 920 } 921 default: 922 break; // Unknown. 923 } 924 925 return CPU; 926 } 927 928 static StringRef 929 getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 930 const unsigned *Features, 931 unsigned *Type, unsigned *Subtype) { 932 auto testFeature = [&](unsigned F) { 933 return (Features[F / 32] & (1U << (F % 32))) != 0; 934 }; 935 936 StringRef CPU; 937 938 switch (Family) { 939 case 4: 940 CPU = "i486"; 941 break; 942 case 5: 943 CPU = "pentium"; 944 switch (Model) { 945 case 6: 946 case 7: 947 CPU = "k6"; 948 break; 949 case 8: 950 CPU = "k6-2"; 951 break; 952 case 9: 953 case 13: 954 CPU = "k6-3"; 955 break; 956 case 10: 957 CPU = "geode"; 958 break; 959 } 960 break; 961 case 6: 962 if (testFeature(X86::FEATURE_SSE)) { 963 CPU = "athlon-xp"; 964 break; 965 } 966 CPU = "athlon"; 967 break; 968 case 15: 969 if (testFeature(X86::FEATURE_SSE3)) { 970 CPU = "k8-sse3"; 971 break; 972 } 973 CPU = "k8"; 974 break; 975 case 16: 976 CPU = "amdfam10"; 977 *Type = X86::AMDFAM10H; // "amdfam10" 978 switch (Model) { 979 case 2: 980 *Subtype = X86::AMDFAM10H_BARCELONA; 981 break; 982 case 4: 983 *Subtype = X86::AMDFAM10H_SHANGHAI; 984 break; 985 case 8: 986 *Subtype = X86::AMDFAM10H_ISTANBUL; 987 break; 988 } 989 break; 990 case 20: 991 CPU = "btver1"; 992 *Type = X86::AMD_BTVER1; 993 break; 994 case 21: 995 CPU = "bdver1"; 996 *Type = X86::AMDFAM15H; 997 if (Model >= 0x60 && Model <= 0x7f) { 998 CPU = "bdver4"; 999 *Subtype = X86::AMDFAM15H_BDVER4; 1000 break; // 60h-7Fh: Excavator 1001 } 1002 if (Model >= 0x30 && Model <= 0x3f) { 1003 CPU = "bdver3"; 1004 *Subtype = X86::AMDFAM15H_BDVER3; 1005 break; // 30h-3Fh: Steamroller 1006 } 1007 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) { 1008 CPU = "bdver2"; 1009 *Subtype = X86::AMDFAM15H_BDVER2; 1010 break; // 02h, 10h-1Fh: Piledriver 1011 } 1012 if (Model <= 0x0f) { 1013 *Subtype = X86::AMDFAM15H_BDVER1; 1014 break; // 00h-0Fh: Bulldozer 1015 } 1016 break; 1017 case 22: 1018 CPU = "btver2"; 1019 *Type = X86::AMD_BTVER2; 1020 break; 1021 case 23: 1022 CPU = "znver1"; 1023 *Type = X86::AMDFAM17H; 1024 if ((Model >= 0x30 && Model <= 0x3f) || Model == 0x71) { 1025 CPU = "znver2"; 1026 *Subtype = X86::AMDFAM17H_ZNVER2; 1027 break; // 30h-3fh, 71h: Zen2 1028 } 1029 if (Model <= 0x0f) { 1030 *Subtype = X86::AMDFAM17H_ZNVER1; 1031 break; // 00h-0Fh: Zen1 1032 } 1033 break; 1034 case 25: 1035 CPU = "znver3"; 1036 *Type = X86::AMDFAM19H; 1037 if (Model <= 0x0f) { 1038 *Subtype = X86::AMDFAM19H_ZNVER3; 1039 break; // 00h-0Fh: Zen3 1040 } 1041 break; 1042 default: 1043 break; // Unknown AMD CPU. 1044 } 1045 1046 return CPU; 1047 } 1048 1049 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 1050 unsigned *Features) { 1051 unsigned EAX, EBX; 1052 1053 auto setFeature = [&](unsigned F) { 1054 Features[F / 32] |= 1U << (F % 32); 1055 }; 1056 1057 if ((EDX >> 15) & 1) 1058 setFeature(X86::FEATURE_CMOV); 1059 if ((EDX >> 23) & 1) 1060 setFeature(X86::FEATURE_MMX); 1061 if ((EDX >> 25) & 1) 1062 setFeature(X86::FEATURE_SSE); 1063 if ((EDX >> 26) & 1) 1064 setFeature(X86::FEATURE_SSE2); 1065 1066 if ((ECX >> 0) & 1) 1067 setFeature(X86::FEATURE_SSE3); 1068 if ((ECX >> 1) & 1) 1069 setFeature(X86::FEATURE_PCLMUL); 1070 if ((ECX >> 9) & 1) 1071 setFeature(X86::FEATURE_SSSE3); 1072 if ((ECX >> 12) & 1) 1073 setFeature(X86::FEATURE_FMA); 1074 if ((ECX >> 19) & 1) 1075 setFeature(X86::FEATURE_SSE4_1); 1076 if ((ECX >> 20) & 1) { 1077 setFeature(X86::FEATURE_SSE4_2); 1078 setFeature(X86::FEATURE_CRC32); 1079 } 1080 if ((ECX >> 23) & 1) 1081 setFeature(X86::FEATURE_POPCNT); 1082 if ((ECX >> 25) & 1) 1083 setFeature(X86::FEATURE_AES); 1084 1085 if ((ECX >> 22) & 1) 1086 setFeature(X86::FEATURE_MOVBE); 1087 1088 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1089 // indicates that the AVX registers will be saved and restored on context 1090 // switch, then we have full AVX support. 1091 const unsigned AVXBits = (1 << 27) | (1 << 28); 1092 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 1093 ((EAX & 0x6) == 0x6); 1094 #if defined(__APPLE__) 1095 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1096 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1097 // set right now. 1098 bool HasAVX512Save = true; 1099 #else 1100 // AVX512 requires additional context to be saved by the OS. 1101 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 1102 #endif 1103 1104 if (HasAVX) 1105 setFeature(X86::FEATURE_AVX); 1106 1107 bool HasLeaf7 = 1108 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1109 1110 if (HasLeaf7 && ((EBX >> 3) & 1)) 1111 setFeature(X86::FEATURE_BMI); 1112 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 1113 setFeature(X86::FEATURE_AVX2); 1114 if (HasLeaf7 && ((EBX >> 8) & 1)) 1115 setFeature(X86::FEATURE_BMI2); 1116 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 1117 setFeature(X86::FEATURE_AVX512F); 1118 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 1119 setFeature(X86::FEATURE_AVX512DQ); 1120 if (HasLeaf7 && ((EBX >> 19) & 1)) 1121 setFeature(X86::FEATURE_ADX); 1122 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 1123 setFeature(X86::FEATURE_AVX512IFMA); 1124 if (HasLeaf7 && ((EBX >> 23) & 1)) 1125 setFeature(X86::FEATURE_CLFLUSHOPT); 1126 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 1127 setFeature(X86::FEATURE_AVX512PF); 1128 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 1129 setFeature(X86::FEATURE_AVX512ER); 1130 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 1131 setFeature(X86::FEATURE_AVX512CD); 1132 if (HasLeaf7 && ((EBX >> 29) & 1)) 1133 setFeature(X86::FEATURE_SHA); 1134 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 1135 setFeature(X86::FEATURE_AVX512BW); 1136 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 1137 setFeature(X86::FEATURE_AVX512VL); 1138 1139 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 1140 setFeature(X86::FEATURE_AVX512VBMI); 1141 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save) 1142 setFeature(X86::FEATURE_AVX512VBMI2); 1143 if (HasLeaf7 && ((ECX >> 8) & 1)) 1144 setFeature(X86::FEATURE_GFNI); 1145 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX) 1146 setFeature(X86::FEATURE_VPCLMULQDQ); 1147 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save) 1148 setFeature(X86::FEATURE_AVX512VNNI); 1149 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save) 1150 setFeature(X86::FEATURE_AVX512BITALG); 1151 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1152 setFeature(X86::FEATURE_AVX512VPOPCNTDQ); 1153 1154 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1155 setFeature(X86::FEATURE_AVX5124VNNIW); 1156 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1157 setFeature(X86::FEATURE_AVX5124FMAPS); 1158 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save) 1159 setFeature(X86::FEATURE_AVX512VP2INTERSECT); 1160 1161 bool HasLeaf7Subleaf1 = 1162 MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1163 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save) 1164 setFeature(X86::FEATURE_AVX512BF16); 1165 1166 unsigned MaxExtLevel; 1167 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1168 1169 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1170 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1171 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1172 setFeature(X86::FEATURE_SSE4_A); 1173 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1174 setFeature(X86::FEATURE_XOP); 1175 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1176 setFeature(X86::FEATURE_FMA4); 1177 1178 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1179 setFeature(X86::FEATURE_64BIT); 1180 } 1181 1182 StringRef sys::getHostCPUName() { 1183 unsigned MaxLeaf = 0; 1184 const VendorSignatures Vendor = getVendorSignature(&MaxLeaf); 1185 if (Vendor == VendorSignatures::UNKNOWN) 1186 return "generic"; 1187 1188 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1189 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1190 1191 unsigned Family = 0, Model = 0; 1192 unsigned Features[(X86::CPU_FEATURE_MAX + 31) / 32] = {0}; 1193 detectX86FamilyModel(EAX, &Family, &Model); 1194 getAvailableFeatures(ECX, EDX, MaxLeaf, Features); 1195 1196 // These aren't consumed in this file, but we try to keep some source code the 1197 // same or similar to compiler-rt. 1198 unsigned Type = 0; 1199 unsigned Subtype = 0; 1200 1201 StringRef CPU; 1202 1203 if (Vendor == VendorSignatures::GENUINE_INTEL) { 1204 CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &Type, 1205 &Subtype); 1206 } else if (Vendor == VendorSignatures::AUTHENTIC_AMD) { 1207 CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, 1208 &Subtype); 1209 } 1210 1211 if (!CPU.empty()) 1212 return CPU; 1213 1214 return "generic"; 1215 } 1216 1217 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1218 StringRef sys::getHostCPUName() { 1219 host_basic_info_data_t hostInfo; 1220 mach_msg_type_number_t infoCount; 1221 1222 infoCount = HOST_BASIC_INFO_COUNT; 1223 mach_port_t hostPort = mach_host_self(); 1224 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1225 &infoCount); 1226 mach_port_deallocate(mach_task_self(), hostPort); 1227 1228 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1229 return "generic"; 1230 1231 switch (hostInfo.cpu_subtype) { 1232 case CPU_SUBTYPE_POWERPC_601: 1233 return "601"; 1234 case CPU_SUBTYPE_POWERPC_602: 1235 return "602"; 1236 case CPU_SUBTYPE_POWERPC_603: 1237 return "603"; 1238 case CPU_SUBTYPE_POWERPC_603e: 1239 return "603e"; 1240 case CPU_SUBTYPE_POWERPC_603ev: 1241 return "603ev"; 1242 case CPU_SUBTYPE_POWERPC_604: 1243 return "604"; 1244 case CPU_SUBTYPE_POWERPC_604e: 1245 return "604e"; 1246 case CPU_SUBTYPE_POWERPC_620: 1247 return "620"; 1248 case CPU_SUBTYPE_POWERPC_750: 1249 return "750"; 1250 case CPU_SUBTYPE_POWERPC_7400: 1251 return "7400"; 1252 case CPU_SUBTYPE_POWERPC_7450: 1253 return "7450"; 1254 case CPU_SUBTYPE_POWERPC_970: 1255 return "970"; 1256 default:; 1257 } 1258 1259 return "generic"; 1260 } 1261 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1262 StringRef sys::getHostCPUName() { 1263 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1264 StringRef Content = P ? P->getBuffer() : ""; 1265 return detail::getHostCPUNameForPowerPC(Content); 1266 } 1267 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1268 StringRef sys::getHostCPUName() { 1269 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1270 StringRef Content = P ? P->getBuffer() : ""; 1271 return detail::getHostCPUNameForARM(Content); 1272 } 1273 #elif defined(__linux__) && defined(__s390x__) 1274 StringRef sys::getHostCPUName() { 1275 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1276 StringRef Content = P ? P->getBuffer() : ""; 1277 return detail::getHostCPUNameForS390x(Content); 1278 } 1279 #elif defined(__MVS__) 1280 StringRef sys::getHostCPUName() { 1281 // Get pointer to Communications Vector Table (CVT). 1282 // The pointer is located at offset 16 of the Prefixed Save Area (PSA). 1283 // It is stored as 31 bit pointer and will be zero-extended to 64 bit. 1284 int *StartToCVTOffset = reinterpret_cast<int *>(0x10); 1285 // Since its stored as a 31-bit pointer, get the 4 bytes from the start 1286 // of address. 1287 int ReadValue = *StartToCVTOffset; 1288 // Explicitly clear the high order bit. 1289 ReadValue = (ReadValue & 0x7FFFFFFF); 1290 char *CVT = reinterpret_cast<char *>(ReadValue); 1291 // The model number is located in the CVT prefix at offset -6 and stored as 1292 // signless packed decimal. 1293 uint16_t Id = *(uint16_t *)&CVT[-6]; 1294 // Convert number to integer. 1295 Id = decodePackedBCD<uint16_t>(Id, false); 1296 // Check for vector support. It's stored in field CVTFLAG5 (offset 244), 1297 // bit CVTVEF (X'80'). The facilities list is part of the PSA but the vector 1298 // extension can only be used if bit CVTVEF is on. 1299 bool HaveVectorSupport = CVT[244] & 0x80; 1300 return getCPUNameFromS390Model(Id, HaveVectorSupport); 1301 } 1302 #elif defined(__APPLE__) && defined(__aarch64__) 1303 StringRef sys::getHostCPUName() { 1304 return "cyclone"; 1305 } 1306 #elif defined(__APPLE__) && defined(__arm__) 1307 StringRef sys::getHostCPUName() { 1308 host_basic_info_data_t hostInfo; 1309 mach_msg_type_number_t infoCount; 1310 1311 infoCount = HOST_BASIC_INFO_COUNT; 1312 mach_port_t hostPort = mach_host_self(); 1313 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1314 &infoCount); 1315 mach_port_deallocate(mach_task_self(), hostPort); 1316 1317 if (hostInfo.cpu_type != CPU_TYPE_ARM) { 1318 assert(false && "CPUType not equal to ARM should not be possible on ARM"); 1319 return "generic"; 1320 } 1321 switch (hostInfo.cpu_subtype) { 1322 case CPU_SUBTYPE_ARM_V7S: 1323 return "swift"; 1324 default:; 1325 } 1326 1327 return "generic"; 1328 } 1329 #elif defined(_AIX) 1330 StringRef sys::getHostCPUName() { 1331 switch (_system_configuration.implementation) { 1332 case POWER_4: 1333 if (_system_configuration.version == PV_4_3) 1334 return "970"; 1335 return "pwr4"; 1336 case POWER_5: 1337 if (_system_configuration.version == PV_5) 1338 return "pwr5"; 1339 return "pwr5x"; 1340 case POWER_6: 1341 if (_system_configuration.version == PV_6_Compat) 1342 return "pwr6"; 1343 return "pwr6x"; 1344 case POWER_7: 1345 return "pwr7"; 1346 case POWER_8: 1347 return "pwr8"; 1348 case POWER_9: 1349 return "pwr9"; 1350 // TODO: simplify this once the macro is available in all OS levels. 1351 #ifdef POWER_10 1352 case POWER_10: 1353 #else 1354 case 0x40000: 1355 #endif 1356 return "pwr10"; 1357 default: 1358 return "generic"; 1359 } 1360 } 1361 #elif defined(__riscv) 1362 StringRef sys::getHostCPUName() { 1363 #if __riscv_xlen == 64 1364 return "generic-rv64"; 1365 #elif __riscv_xlen == 32 1366 return "generic-rv32"; 1367 #else 1368 #error "Unhandled value of __riscv_xlen" 1369 #endif 1370 } 1371 #else 1372 StringRef sys::getHostCPUName() { return "generic"; } 1373 namespace llvm { 1374 namespace sys { 1375 namespace detail { 1376 namespace x86 { 1377 1378 VendorSignatures getVendorSignature(unsigned *MaxLeaf) { 1379 return VendorSignatures::UNKNOWN; 1380 } 1381 1382 } // namespace x86 1383 } // namespace detail 1384 } // namespace sys 1385 } // namespace llvm 1386 #endif 1387 1388 #if defined(__linux__) && (defined(__i386__) || defined(__x86_64__)) 1389 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1390 // using the number of unique physical/core id pairs. The following 1391 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1392 int computeHostNumPhysicalCores() { 1393 // Enabled represents the number of physical id/core id pairs with at least 1394 // one processor id enabled by the CPU affinity mask. 1395 cpu_set_t Affinity, Enabled; 1396 if (sched_getaffinity(0, sizeof(Affinity), &Affinity) != 0) 1397 return -1; 1398 CPU_ZERO(&Enabled); 1399 1400 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1401 // mmapped because it appears to have 0 size. 1402 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1403 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1404 if (std::error_code EC = Text.getError()) { 1405 llvm::errs() << "Can't read " 1406 << "/proc/cpuinfo: " << EC.message() << "\n"; 1407 return -1; 1408 } 1409 SmallVector<StringRef, 8> strs; 1410 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1411 /*KeepEmpty=*/false); 1412 int CurProcessor = -1; 1413 int CurPhysicalId = -1; 1414 int CurSiblings = -1; 1415 int CurCoreId = -1; 1416 for (StringRef Line : strs) { 1417 std::pair<StringRef, StringRef> Data = Line.split(':'); 1418 auto Name = Data.first.trim(); 1419 auto Val = Data.second.trim(); 1420 // These fields are available if the kernel is configured with CONFIG_SMP. 1421 if (Name == "processor") 1422 Val.getAsInteger(10, CurProcessor); 1423 else if (Name == "physical id") 1424 Val.getAsInteger(10, CurPhysicalId); 1425 else if (Name == "siblings") 1426 Val.getAsInteger(10, CurSiblings); 1427 else if (Name == "core id") { 1428 Val.getAsInteger(10, CurCoreId); 1429 // The processor id corresponds to an index into cpu_set_t. 1430 if (CPU_ISSET(CurProcessor, &Affinity)) 1431 CPU_SET(CurPhysicalId * CurSiblings + CurCoreId, &Enabled); 1432 } 1433 } 1434 return CPU_COUNT(&Enabled); 1435 } 1436 #elif defined(__linux__) && defined(__powerpc__) 1437 int computeHostNumPhysicalCores() { 1438 cpu_set_t Affinity; 1439 if (sched_getaffinity(0, sizeof(Affinity), &Affinity) == 0) 1440 return CPU_COUNT(&Affinity); 1441 1442 // The call to sched_getaffinity() may have failed because the Affinity 1443 // mask is too small for the number of CPU's on the system (i.e. the 1444 // system has more than 1024 CPUs). Allocate a mask large enough for 1445 // twice as many CPUs. 1446 cpu_set_t *DynAffinity; 1447 DynAffinity = CPU_ALLOC(2048); 1448 if (sched_getaffinity(0, CPU_ALLOC_SIZE(2048), DynAffinity) == 0) { 1449 int NumCPUs = CPU_COUNT(DynAffinity); 1450 CPU_FREE(DynAffinity); 1451 return NumCPUs; 1452 } 1453 return -1; 1454 } 1455 #elif defined(__linux__) && defined(__s390x__) 1456 int computeHostNumPhysicalCores() { return sysconf(_SC_NPROCESSORS_ONLN); } 1457 #elif defined(__APPLE__) 1458 #include <sys/param.h> 1459 #include <sys/sysctl.h> 1460 1461 // Gets the number of *physical cores* on the machine. 1462 int computeHostNumPhysicalCores() { 1463 uint32_t count; 1464 size_t len = sizeof(count); 1465 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1466 if (count < 1) { 1467 int nm[2]; 1468 nm[0] = CTL_HW; 1469 nm[1] = HW_AVAILCPU; 1470 sysctl(nm, 2, &count, &len, NULL, 0); 1471 if (count < 1) 1472 return -1; 1473 } 1474 return count; 1475 } 1476 #elif defined(__MVS__) 1477 int computeHostNumPhysicalCores() { 1478 enum { 1479 // Byte offset of the pointer to the Communications Vector Table (CVT) in 1480 // the Prefixed Save Area (PSA). The table entry is a 31-bit pointer and 1481 // will be zero-extended to uintptr_t. 1482 FLCCVT = 16, 1483 // Byte offset of the pointer to the Common System Data Area (CSD) in the 1484 // CVT. The table entry is a 31-bit pointer and will be zero-extended to 1485 // uintptr_t. 1486 CVTCSD = 660, 1487 // Byte offset to the number of live CPs in the LPAR, stored as a signed 1488 // 32-bit value in the table. 1489 CSD_NUMBER_ONLINE_STANDARD_CPS = 264, 1490 }; 1491 char *PSA = 0; 1492 char *CVT = reinterpret_cast<char *>( 1493 static_cast<uintptr_t>(reinterpret_cast<unsigned int &>(PSA[FLCCVT]))); 1494 char *CSD = reinterpret_cast<char *>( 1495 static_cast<uintptr_t>(reinterpret_cast<unsigned int &>(CVT[CVTCSD]))); 1496 return reinterpret_cast<int &>(CSD[CSD_NUMBER_ONLINE_STANDARD_CPS]); 1497 } 1498 #elif defined(_WIN32) && LLVM_ENABLE_THREADS != 0 1499 // Defined in llvm/lib/Support/Windows/Threading.inc 1500 int computeHostNumPhysicalCores(); 1501 #else 1502 // On other systems, return -1 to indicate unknown. 1503 static int computeHostNumPhysicalCores() { return -1; } 1504 #endif 1505 1506 int sys::getHostNumPhysicalCores() { 1507 static int NumCores = computeHostNumPhysicalCores(); 1508 return NumCores; 1509 } 1510 1511 #if defined(__i386__) || defined(_M_IX86) || \ 1512 defined(__x86_64__) || defined(_M_X64) 1513 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1514 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1515 unsigned MaxLevel; 1516 1517 if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1) 1518 return false; 1519 1520 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1521 1522 Features["cx8"] = (EDX >> 8) & 1; 1523 Features["cmov"] = (EDX >> 15) & 1; 1524 Features["mmx"] = (EDX >> 23) & 1; 1525 Features["fxsr"] = (EDX >> 24) & 1; 1526 Features["sse"] = (EDX >> 25) & 1; 1527 Features["sse2"] = (EDX >> 26) & 1; 1528 1529 Features["sse3"] = (ECX >> 0) & 1; 1530 Features["pclmul"] = (ECX >> 1) & 1; 1531 Features["ssse3"] = (ECX >> 9) & 1; 1532 Features["cx16"] = (ECX >> 13) & 1; 1533 Features["sse4.1"] = (ECX >> 19) & 1; 1534 Features["sse4.2"] = (ECX >> 20) & 1; 1535 Features["crc32"] = Features["sse4.2"]; 1536 Features["movbe"] = (ECX >> 22) & 1; 1537 Features["popcnt"] = (ECX >> 23) & 1; 1538 Features["aes"] = (ECX >> 25) & 1; 1539 Features["rdrnd"] = (ECX >> 30) & 1; 1540 1541 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1542 // indicates that the AVX registers will be saved and restored on context 1543 // switch, then we have full AVX support. 1544 bool HasXSave = ((ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX); 1545 bool HasAVXSave = HasXSave && ((ECX >> 28) & 1) && ((EAX & 0x6) == 0x6); 1546 #if defined(__APPLE__) 1547 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1548 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1549 // set right now. 1550 bool HasAVX512Save = true; 1551 #else 1552 // AVX512 requires additional context to be saved by the OS. 1553 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1554 #endif 1555 // AMX requires additional context to be saved by the OS. 1556 const unsigned AMXBits = (1 << 17) | (1 << 18); 1557 bool HasAMXSave = HasXSave && ((EAX & AMXBits) == AMXBits); 1558 1559 Features["avx"] = HasAVXSave; 1560 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave; 1561 // Only enable XSAVE if OS has enabled support for saving YMM state. 1562 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave; 1563 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave; 1564 1565 unsigned MaxExtLevel; 1566 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1567 1568 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1569 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1570 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1); 1571 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1572 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1573 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1574 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1575 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1576 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1577 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1578 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1579 1580 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1); 1581 1582 // Miscellaneous memory related features, detected by 1583 // using the 0x80000008 leaf of the CPUID instruction 1584 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1585 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX); 1586 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1587 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1); 1588 1589 bool HasLeaf7 = 1590 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1591 1592 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1593 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1594 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1595 // AVX2 is only supported if we have the OS save support from AVX. 1596 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave; 1597 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1598 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1599 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1600 // AVX512 is only supported if the OS supports the context save for it. 1601 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1602 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1603 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1604 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1605 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1606 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1607 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1608 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1609 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1610 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1611 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1612 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1613 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1614 1615 Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1); 1616 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1617 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1618 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1); 1619 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save; 1620 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1); 1621 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1); 1622 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave; 1623 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave; 1624 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save; 1625 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save; 1626 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1627 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1); 1628 Features["kl"] = HasLeaf7 && ((ECX >> 23) & 1); // key locker 1629 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1); 1630 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1); 1631 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1); 1632 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1); 1633 1634 Features["uintr"] = HasLeaf7 && ((EDX >> 5) & 1); 1635 Features["avx512vp2intersect"] = 1636 HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save; 1637 Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1); 1638 Features["tsxldtrk"] = HasLeaf7 && ((EDX >> 16) & 1); 1639 // There are two CPUID leafs which information associated with the pconfig 1640 // instruction: 1641 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th 1642 // bit of EDX), while the EAX=0x1b leaf returns information on the 1643 // availability of specific pconfig leafs. 1644 // The target feature here only refers to the the first of these two. 1645 // Users might need to check for the availability of specific pconfig 1646 // leaves using cpuid, since that information is ignored while 1647 // detecting features using the "-march=native" flag. 1648 // For more info, see X86 ISA docs. 1649 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1); 1650 Features["amx-bf16"] = HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave; 1651 Features["avx512fp16"] = HasLeaf7 && ((EDX >> 23) & 1) && HasAVX512Save; 1652 Features["amx-tile"] = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave; 1653 Features["amx-int8"] = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave; 1654 bool HasLeaf7Subleaf1 = 1655 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1656 Features["avxvnni"] = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave; 1657 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save; 1658 Features["hreset"] = HasLeaf7Subleaf1 && ((EAX >> 22) & 1); 1659 1660 bool HasLeafD = MaxLevel >= 0xd && 1661 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1662 1663 // Only enable XSAVE if OS has enabled support for saving YMM state. 1664 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave; 1665 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave; 1666 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave; 1667 1668 bool HasLeaf14 = MaxLevel >= 0x14 && 1669 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX); 1670 1671 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1); 1672 1673 bool HasLeaf19 = 1674 MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX); 1675 Features["widekl"] = HasLeaf7 && HasLeaf19 && ((EBX >> 2) & 1); 1676 1677 return true; 1678 } 1679 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1680 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1681 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1682 if (!P) 1683 return false; 1684 1685 SmallVector<StringRef, 32> Lines; 1686 P->getBuffer().split(Lines, "\n"); 1687 1688 SmallVector<StringRef, 32> CPUFeatures; 1689 1690 // Look for the CPU features. 1691 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1692 if (Lines[I].startswith("Features")) { 1693 Lines[I].split(CPUFeatures, ' '); 1694 break; 1695 } 1696 1697 #if defined(__aarch64__) 1698 // Keep track of which crypto features we have seen 1699 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1700 uint32_t crypto = 0; 1701 #endif 1702 1703 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1704 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1705 #if defined(__aarch64__) 1706 .Case("asimd", "neon") 1707 .Case("fp", "fp-armv8") 1708 .Case("crc32", "crc") 1709 #else 1710 .Case("half", "fp16") 1711 .Case("neon", "neon") 1712 .Case("vfpv3", "vfp3") 1713 .Case("vfpv3d16", "d16") 1714 .Case("vfpv4", "vfp4") 1715 .Case("idiva", "hwdiv-arm") 1716 .Case("idivt", "hwdiv") 1717 #endif 1718 .Default(""); 1719 1720 #if defined(__aarch64__) 1721 // We need to check crypto separately since we need all of the crypto 1722 // extensions to enable the subtarget feature 1723 if (CPUFeatures[I] == "aes") 1724 crypto |= CAP_AES; 1725 else if (CPUFeatures[I] == "pmull") 1726 crypto |= CAP_PMULL; 1727 else if (CPUFeatures[I] == "sha1") 1728 crypto |= CAP_SHA1; 1729 else if (CPUFeatures[I] == "sha2") 1730 crypto |= CAP_SHA2; 1731 #endif 1732 1733 if (LLVMFeatureStr != "") 1734 Features[LLVMFeatureStr] = true; 1735 } 1736 1737 #if defined(__aarch64__) 1738 // If we have all crypto bits we can add the feature 1739 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1740 Features["crypto"] = true; 1741 #endif 1742 1743 return true; 1744 } 1745 #elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64)) 1746 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1747 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE)) 1748 Features["neon"] = true; 1749 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE)) 1750 Features["crc"] = true; 1751 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) 1752 Features["crypto"] = true; 1753 1754 return true; 1755 } 1756 #else 1757 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1758 #endif 1759 1760 std::string sys::getProcessTriple() { 1761 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1762 Triple PT(Triple::normalize(TargetTripleString)); 1763 1764 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1765 PT = PT.get64BitArchVariant(); 1766 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1767 PT = PT.get32BitArchVariant(); 1768 1769 return PT.str(); 1770 } 1771