1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the operating system Host concept. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Support/Host.h" 15 #include "llvm/ADT/SmallSet.h" 16 #include "llvm/ADT/SmallVector.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include <assert.h> 26 #include <string.h> 27 28 // Include the platform-specific parts of this class. 29 #ifdef LLVM_ON_UNIX 30 #include "Unix/Host.inc" 31 #endif 32 #ifdef LLVM_ON_WIN32 33 #include "Windows/Host.inc" 34 #endif 35 #ifdef _MSC_VER 36 #include <intrin.h> 37 #endif 38 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 39 #include <mach/host_info.h> 40 #include <mach/mach.h> 41 #include <mach/mach_host.h> 42 #include <mach/machine.h> 43 #endif 44 45 #define DEBUG_TYPE "host-detection" 46 47 //===----------------------------------------------------------------------===// 48 // 49 // Implementations of the CPU detection routines 50 // 51 //===----------------------------------------------------------------------===// 52 53 using namespace llvm; 54 55 static std::unique_ptr<llvm::MemoryBuffer> 56 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 57 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 58 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 59 if (std::error_code EC = Text.getError()) { 60 llvm::errs() << "Can't read " 61 << "/proc/cpuinfo: " << EC.message() << "\n"; 62 return nullptr; 63 } 64 return std::move(*Text); 65 } 66 67 StringRef sys::detail::getHostCPUNameForPowerPC( 68 const StringRef &ProcCpuinfoContent) { 69 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 70 // and so we must use an operating-system interface to determine the current 71 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 72 const char *generic = "generic"; 73 74 // The cpu line is second (after the 'processor: 0' line), so if this 75 // buffer is too small then something has changed (or is wrong). 76 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 77 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 78 79 StringRef::const_iterator CIP = CPUInfoStart; 80 81 StringRef::const_iterator CPUStart = 0; 82 size_t CPULen = 0; 83 84 // We need to find the first line which starts with cpu, spaces, and a colon. 85 // After the colon, there may be some additional spaces and then the cpu type. 86 while (CIP < CPUInfoEnd && CPUStart == 0) { 87 if (CIP < CPUInfoEnd && *CIP == '\n') 88 ++CIP; 89 90 if (CIP < CPUInfoEnd && *CIP == 'c') { 91 ++CIP; 92 if (CIP < CPUInfoEnd && *CIP == 'p') { 93 ++CIP; 94 if (CIP < CPUInfoEnd && *CIP == 'u') { 95 ++CIP; 96 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 97 ++CIP; 98 99 if (CIP < CPUInfoEnd && *CIP == ':') { 100 ++CIP; 101 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 102 ++CIP; 103 104 if (CIP < CPUInfoEnd) { 105 CPUStart = CIP; 106 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 107 *CIP != ',' && *CIP != '\n')) 108 ++CIP; 109 CPULen = CIP - CPUStart; 110 } 111 } 112 } 113 } 114 } 115 116 if (CPUStart == 0) 117 while (CIP < CPUInfoEnd && *CIP != '\n') 118 ++CIP; 119 } 120 121 if (CPUStart == 0) 122 return generic; 123 124 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 125 .Case("604e", "604e") 126 .Case("604", "604") 127 .Case("7400", "7400") 128 .Case("7410", "7400") 129 .Case("7447", "7400") 130 .Case("7455", "7450") 131 .Case("G4", "g4") 132 .Case("POWER4", "970") 133 .Case("PPC970FX", "970") 134 .Case("PPC970MP", "970") 135 .Case("G5", "g5") 136 .Case("POWER5", "g5") 137 .Case("A2", "a2") 138 .Case("POWER6", "pwr6") 139 .Case("POWER7", "pwr7") 140 .Case("POWER8", "pwr8") 141 .Case("POWER8E", "pwr8") 142 .Case("POWER8NVL", "pwr8") 143 .Case("POWER9", "pwr9") 144 .Default(generic); 145 } 146 147 StringRef sys::detail::getHostCPUNameForARM( 148 const StringRef &ProcCpuinfoContent) { 149 // The cpuid register on arm is not accessible from user space. On Linux, 150 // it is exposed through the /proc/cpuinfo file. 151 152 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 153 // in all cases. 154 SmallVector<StringRef, 32> Lines; 155 ProcCpuinfoContent.split(Lines, "\n"); 156 157 // Look for the CPU implementer line. 158 StringRef Implementer; 159 StringRef Hardware; 160 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 161 if (Lines[I].startswith("CPU implementer")) 162 Implementer = Lines[I].substr(15).ltrim("\t :"); 163 if (Lines[I].startswith("Hardware")) 164 Hardware = Lines[I].substr(8).ltrim("\t :"); 165 } 166 167 if (Implementer == "0x41") { // ARM Ltd. 168 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 169 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 170 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 171 return "cortex-a53"; 172 173 174 // Look for the CPU part line. 175 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 176 if (Lines[I].startswith("CPU part")) 177 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 178 // values correspond to the "Part number" in the CP15/c0 register. The 179 // contents are specified in the various processor manuals. 180 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 181 .Case("0x926", "arm926ej-s") 182 .Case("0xb02", "mpcore") 183 .Case("0xb36", "arm1136j-s") 184 .Case("0xb56", "arm1156t2-s") 185 .Case("0xb76", "arm1176jz-s") 186 .Case("0xc08", "cortex-a8") 187 .Case("0xc09", "cortex-a9") 188 .Case("0xc0f", "cortex-a15") 189 .Case("0xc20", "cortex-m0") 190 .Case("0xc23", "cortex-m3") 191 .Case("0xc24", "cortex-m4") 192 .Case("0xd04", "cortex-a35") 193 .Case("0xd03", "cortex-a53") 194 .Case("0xd07", "cortex-a57") 195 .Case("0xd08", "cortex-a72") 196 .Case("0xd09", "cortex-a73") 197 .Default("generic"); 198 } 199 200 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 201 // Look for the CPU part line. 202 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 203 if (Lines[I].startswith("CPU part")) 204 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 205 // values correspond to the "Part number" in the CP15/c0 register. The 206 // contents are specified in the various processor manuals. 207 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 208 .Case("0x06f", "krait") // APQ8064 209 .Case("0x201", "kryo") 210 .Case("0x205", "kryo") 211 .Case("0x211", "kryo") 212 .Case("0x800", "cortex-a73") 213 .Case("0x801", "cortex-a73") 214 .Case("0xc00", "falkor") 215 .Case("0xc01", "saphira") 216 .Default("generic"); 217 218 return "generic"; 219 } 220 221 StringRef sys::detail::getHostCPUNameForS390x( 222 const StringRef &ProcCpuinfoContent) { 223 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 224 225 // The "processor 0:" line comes after a fair amount of other information, 226 // including a cache breakdown, but this should be plenty. 227 SmallVector<StringRef, 32> Lines; 228 ProcCpuinfoContent.split(Lines, "\n"); 229 230 // Look for the CPU features. 231 SmallVector<StringRef, 32> CPUFeatures; 232 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 233 if (Lines[I].startswith("features")) { 234 size_t Pos = Lines[I].find(":"); 235 if (Pos != StringRef::npos) { 236 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 237 break; 238 } 239 } 240 241 // We need to check for the presence of vector support independently of 242 // the machine type, since we may only use the vector register set when 243 // supported by the kernel (and hypervisor). 244 bool HaveVectorSupport = false; 245 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 246 if (CPUFeatures[I] == "vx") 247 HaveVectorSupport = true; 248 } 249 250 // Now check the processor machine type. 251 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 252 if (Lines[I].startswith("processor ")) { 253 size_t Pos = Lines[I].find("machine = "); 254 if (Pos != StringRef::npos) { 255 Pos += sizeof("machine = ") - 1; 256 unsigned int Id; 257 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 258 if (Id >= 3906 && HaveVectorSupport) 259 return "z14"; 260 if (Id >= 2964 && HaveVectorSupport) 261 return "z13"; 262 if (Id >= 2827) 263 return "zEC12"; 264 if (Id >= 2817) 265 return "z196"; 266 } 267 } 268 break; 269 } 270 } 271 272 return "generic"; 273 } 274 275 StringRef sys::detail::getHostCPUNameForBPF() { 276 #if !defined(__linux__) || !defined(__x86_64__) 277 return "generic"; 278 #else 279 uint8_t insns[40] __attribute__ ((aligned (8))) = 280 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 281 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 282 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 283 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 284 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 285 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 286 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 287 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 288 /* BPF_EXIT_INSN() */ 289 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 290 291 struct bpf_prog_load_attr { 292 uint32_t prog_type; 293 uint32_t insn_cnt; 294 uint64_t insns; 295 uint64_t license; 296 uint32_t log_level; 297 uint32_t log_size; 298 uint64_t log_buf; 299 uint32_t kern_version; 300 uint32_t prog_flags; 301 } attr = {}; 302 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 303 attr.insn_cnt = 5; 304 attr.insns = (uint64_t)insns; 305 attr.license = (uint64_t)"DUMMY"; 306 307 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 308 if (fd >= 0) { 309 close(fd); 310 return "v2"; 311 } 312 return "v1"; 313 #endif 314 } 315 316 #if defined(__i386__) || defined(_M_IX86) || \ 317 defined(__x86_64__) || defined(_M_X64) 318 319 enum VendorSignatures { 320 SIG_INTEL = 0x756e6547 /* Genu */, 321 SIG_AMD = 0x68747541 /* Auth */ 322 }; 323 324 enum ProcessorVendors { 325 VENDOR_INTEL = 1, 326 VENDOR_AMD, 327 VENDOR_OTHER, 328 VENDOR_MAX 329 }; 330 331 enum ProcessorTypes { 332 INTEL_BONNELL = 1, 333 INTEL_CORE2, 334 INTEL_COREI7, 335 AMDFAM10H, 336 AMDFAM15H, 337 INTEL_SILVERMONT, 338 INTEL_KNL, 339 AMD_BTVER1, 340 AMD_BTVER2, 341 AMDFAM17H, 342 INTEL_KNM, 343 // Entries below this are not in libgcc/compiler-rt. 344 INTEL_i386, 345 INTEL_i486, 346 INTEL_PENTIUM, 347 INTEL_PENTIUM_MMX, 348 INTEL_PENTIUM_PRO, 349 INTEL_PENTIUM_II, 350 INTEL_PENTIUM_III, 351 INTEL_PENTIUM_IV, 352 INTEL_PENTIUM_M, 353 INTEL_CORE_DUO, 354 INTEL_NOCONA, 355 INTEL_PRESCOTT, 356 AMD_i486, 357 AMDPENTIUM, 358 AMD_ATHLON, 359 AMD_ATHLON_XP, 360 AMD_K8, 361 AMD_K8SSE3, 362 INTEL_GOLDMONT, 363 CPU_TYPE_MAX 364 }; 365 366 enum ProcessorSubtypes { 367 INTEL_COREI7_NEHALEM = 1, 368 INTEL_COREI7_WESTMERE, 369 INTEL_COREI7_SANDYBRIDGE, 370 AMDFAM10H_BARCELONA, 371 AMDFAM10H_SHANGHAI, 372 AMDFAM10H_ISTANBUL, 373 AMDFAM15H_BDVER1, 374 AMDFAM15H_BDVER2, 375 AMDFAM15H_BDVER3, 376 AMDFAM15H_BDVER4, 377 AMDFAM17H_ZNVER1, 378 INTEL_COREI7_IVYBRIDGE, 379 INTEL_COREI7_HASWELL, 380 INTEL_COREI7_BROADWELL, 381 INTEL_COREI7_SKYLAKE, 382 INTEL_COREI7_SKYLAKE_AVX512, 383 // Entries below this are not in libgcc/compiler-rt. 384 INTEL_CORE2_65, 385 INTEL_CORE2_45, 386 AMDPENTIUM_K6, 387 AMDPENTIUM_K62, 388 AMDPENTIUM_K63, 389 AMDPENTIUM_GEODE, 390 CPU_SUBTYPE_MAX 391 }; 392 393 enum ProcessorFeatures { 394 FEATURE_CMOV = 0, 395 FEATURE_MMX, 396 FEATURE_POPCNT, 397 FEATURE_SSE, 398 FEATURE_SSE2, 399 FEATURE_SSE3, 400 FEATURE_SSSE3, 401 FEATURE_SSE4_1, 402 FEATURE_SSE4_2, 403 FEATURE_AVX, 404 FEATURE_AVX2, 405 FEATURE_SSE4_A, 406 FEATURE_FMA4, 407 FEATURE_XOP, 408 FEATURE_FMA, 409 FEATURE_AVX512F, 410 FEATURE_BMI, 411 FEATURE_BMI2, 412 FEATURE_AES, 413 FEATURE_PCLMUL, 414 FEATURE_AVX512VL, 415 FEATURE_AVX512BW, 416 FEATURE_AVX512DQ, 417 FEATURE_AVX512CD, 418 FEATURE_AVX512ER, 419 FEATURE_AVX512PF, 420 FEATURE_AVX512VBMI, 421 FEATURE_AVX512IFMA, 422 FEATURE_AVX5124VNNIW, 423 FEATURE_AVX5124FMAPS, 424 FEATURE_AVX512VPOPCNTDQ, 425 // Only one bit free left in the first 32 features. 426 FEATURE_MOVBE = 32, 427 FEATURE_ADX, 428 FEATURE_EM64T, 429 FEATURE_CLFLUSHOPT, 430 FEATURE_SHA, 431 }; 432 433 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 434 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 435 // support. Consequently, for i386, the presence of CPUID is checked first 436 // via the corresponding eflags bit. 437 // Removal of cpuid.h header motivated by PR30384 438 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 439 // or test-suite, but are used in external projects e.g. libstdcxx 440 static bool isCpuIdSupported() { 441 #if defined(__GNUC__) || defined(__clang__) 442 #if defined(__i386__) 443 int __cpuid_supported; 444 __asm__(" pushfl\n" 445 " popl %%eax\n" 446 " movl %%eax,%%ecx\n" 447 " xorl $0x00200000,%%eax\n" 448 " pushl %%eax\n" 449 " popfl\n" 450 " pushfl\n" 451 " popl %%eax\n" 452 " movl $0,%0\n" 453 " cmpl %%eax,%%ecx\n" 454 " je 1f\n" 455 " movl $1,%0\n" 456 "1:" 457 : "=r"(__cpuid_supported) 458 : 459 : "eax", "ecx"); 460 if (!__cpuid_supported) 461 return false; 462 #endif 463 return true; 464 #endif 465 return true; 466 } 467 468 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 469 /// the specified arguments. If we can't run cpuid on the host, return true. 470 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 471 unsigned *rECX, unsigned *rEDX) { 472 #if defined(__GNUC__) || defined(__clang__) 473 #if defined(__x86_64__) 474 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 475 // FIXME: should we save this for Clang? 476 __asm__("movq\t%%rbx, %%rsi\n\t" 477 "cpuid\n\t" 478 "xchgq\t%%rbx, %%rsi\n\t" 479 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 480 : "a"(value)); 481 return false; 482 #elif defined(__i386__) 483 __asm__("movl\t%%ebx, %%esi\n\t" 484 "cpuid\n\t" 485 "xchgl\t%%ebx, %%esi\n\t" 486 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 487 : "a"(value)); 488 return false; 489 #else 490 return true; 491 #endif 492 #elif defined(_MSC_VER) 493 // The MSVC intrinsic is portable across x86 and x64. 494 int registers[4]; 495 __cpuid(registers, value); 496 *rEAX = registers[0]; 497 *rEBX = registers[1]; 498 *rECX = registers[2]; 499 *rEDX = registers[3]; 500 return false; 501 #else 502 return true; 503 #endif 504 } 505 506 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 507 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 508 /// return true. 509 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 510 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 511 unsigned *rEDX) { 512 #if defined(__GNUC__) || defined(__clang__) 513 #if defined(__x86_64__) 514 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 515 // FIXME: should we save this for Clang? 516 __asm__("movq\t%%rbx, %%rsi\n\t" 517 "cpuid\n\t" 518 "xchgq\t%%rbx, %%rsi\n\t" 519 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 520 : "a"(value), "c"(subleaf)); 521 return false; 522 #elif defined(__i386__) 523 __asm__("movl\t%%ebx, %%esi\n\t" 524 "cpuid\n\t" 525 "xchgl\t%%ebx, %%esi\n\t" 526 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 527 : "a"(value), "c"(subleaf)); 528 return false; 529 #else 530 return true; 531 #endif 532 #elif defined(_MSC_VER) 533 int registers[4]; 534 __cpuidex(registers, value, subleaf); 535 *rEAX = registers[0]; 536 *rEBX = registers[1]; 537 *rECX = registers[2]; 538 *rEDX = registers[3]; 539 return false; 540 #else 541 return true; 542 #endif 543 } 544 545 // Read control register 0 (XCR0). Used to detect features such as AVX. 546 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 547 #if defined(__GNUC__) || defined(__clang__) 548 // Check xgetbv; this uses a .byte sequence instead of the instruction 549 // directly because older assemblers do not include support for xgetbv and 550 // there is no easy way to conditionally compile based on the assembler used. 551 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 552 return false; 553 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 554 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 555 *rEAX = Result; 556 *rEDX = Result >> 32; 557 return false; 558 #else 559 return true; 560 #endif 561 } 562 563 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 564 unsigned *Model) { 565 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 566 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 567 if (*Family == 6 || *Family == 0xf) { 568 if (*Family == 0xf) 569 // Examine extended family ID if family ID is F. 570 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 571 // Examine extended model ID if family ID is 6 or F. 572 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 573 } 574 } 575 576 static void 577 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 578 unsigned Brand_id, unsigned Features, 579 unsigned Features2, unsigned *Type, 580 unsigned *Subtype) { 581 if (Brand_id != 0) 582 return; 583 switch (Family) { 584 case 3: 585 *Type = INTEL_i386; 586 break; 587 case 4: 588 *Type = INTEL_i486; 589 break; 590 case 5: 591 if (Features & (1 << FEATURE_MMX)) { 592 *Type = INTEL_PENTIUM_MMX; 593 break; 594 } 595 *Type = INTEL_PENTIUM; 596 break; 597 case 6: 598 switch (Model) { 599 case 0x01: // Pentium Pro processor 600 *Type = INTEL_PENTIUM_PRO; 601 break; 602 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 603 // model 03 604 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 605 // model 05, and Intel Celeron processor, model 05 606 case 0x06: // Celeron processor, model 06 607 *Type = INTEL_PENTIUM_II; 608 break; 609 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 610 // processor, model 07 611 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 612 // model 08, and Celeron processor, model 08 613 case 0x0a: // Pentium III Xeon processor, model 0Ah 614 case 0x0b: // Pentium III processor, model 0Bh 615 *Type = INTEL_PENTIUM_III; 616 break; 617 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 618 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 619 // 0Dh. All processors are manufactured using the 90 nm process. 620 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 621 // Integrated Processor with Intel QuickAssist Technology 622 *Type = INTEL_PENTIUM_M; 623 break; 624 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 625 // 0Eh. All processors are manufactured using the 65 nm process. 626 *Type = INTEL_CORE_DUO; 627 break; // yonah 628 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 629 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 630 // mobile processor, Intel Core 2 Extreme processor, Intel 631 // Pentium Dual-Core processor, Intel Xeon processor, model 632 // 0Fh. All processors are manufactured using the 65 nm process. 633 case 0x16: // Intel Celeron processor model 16h. All processors are 634 // manufactured using the 65 nm process 635 *Type = INTEL_CORE2; // "core2" 636 *Subtype = INTEL_CORE2_65; 637 break; 638 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 639 // 17h. All processors are manufactured using the 45 nm process. 640 // 641 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 642 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 643 // the 45 nm process. 644 *Type = INTEL_CORE2; // "penryn" 645 *Subtype = INTEL_CORE2_45; 646 break; 647 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 648 // processors are manufactured using the 45 nm process. 649 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 650 // As found in a Summer 2010 model iMac. 651 case 0x1f: 652 case 0x2e: // Nehalem EX 653 *Type = INTEL_COREI7; // "nehalem" 654 *Subtype = INTEL_COREI7_NEHALEM; 655 break; 656 case 0x25: // Intel Core i7, laptop version. 657 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 658 // processors are manufactured using the 32 nm process. 659 case 0x2f: // Westmere EX 660 *Type = INTEL_COREI7; // "westmere" 661 *Subtype = INTEL_COREI7_WESTMERE; 662 break; 663 case 0x2a: // Intel Core i7 processor. All processors are manufactured 664 // using the 32 nm process. 665 case 0x2d: 666 *Type = INTEL_COREI7; //"sandybridge" 667 *Subtype = INTEL_COREI7_SANDYBRIDGE; 668 break; 669 case 0x3a: 670 case 0x3e: // Ivy Bridge EP 671 *Type = INTEL_COREI7; // "ivybridge" 672 *Subtype = INTEL_COREI7_IVYBRIDGE; 673 break; 674 675 // Haswell: 676 case 0x3c: 677 case 0x3f: 678 case 0x45: 679 case 0x46: 680 *Type = INTEL_COREI7; // "haswell" 681 *Subtype = INTEL_COREI7_HASWELL; 682 break; 683 684 // Broadwell: 685 case 0x3d: 686 case 0x47: 687 case 0x4f: 688 case 0x56: 689 *Type = INTEL_COREI7; // "broadwell" 690 *Subtype = INTEL_COREI7_BROADWELL; 691 break; 692 693 // Skylake: 694 case 0x4e: // Skylake mobile 695 case 0x5e: // Skylake desktop 696 case 0x8e: // Kaby Lake mobile 697 case 0x9e: // Kaby Lake desktop 698 *Type = INTEL_COREI7; // "skylake" 699 *Subtype = INTEL_COREI7_SKYLAKE; 700 break; 701 702 // Skylake Xeon: 703 case 0x55: 704 *Type = INTEL_COREI7; 705 *Subtype = INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 706 break; 707 708 case 0x1c: // Most 45 nm Intel Atom processors 709 case 0x26: // 45 nm Atom Lincroft 710 case 0x27: // 32 nm Atom Medfield 711 case 0x35: // 32 nm Atom Midview 712 case 0x36: // 32 nm Atom Midview 713 *Type = INTEL_BONNELL; 714 break; // "bonnell" 715 716 // Atom Silvermont codes from the Intel software optimization guide. 717 case 0x37: 718 case 0x4a: 719 case 0x4d: 720 case 0x5a: 721 case 0x5d: 722 case 0x4c: // really airmont 723 *Type = INTEL_SILVERMONT; 724 break; // "silvermont" 725 // Goldmont: 726 case 0x5c: 727 case 0x5f: 728 *Type = INTEL_GOLDMONT; 729 break; // "goldmont" 730 case 0x57: 731 *Type = INTEL_KNL; // knl 732 break; 733 case 0x85: 734 *Type = INTEL_KNM; // knm 735 break; 736 737 default: // Unknown family 6 CPU, try to guess. 738 if (Features & (1 << FEATURE_AVX512F)) { 739 if (Features & (1 << FEATURE_AVX512VL)) { 740 *Type = INTEL_COREI7; 741 *Subtype = INTEL_COREI7_SKYLAKE_AVX512; 742 } else { 743 *Type = INTEL_KNL; // knl 744 } 745 break; 746 } 747 if (Features2 & (1 << (FEATURE_CLFLUSHOPT - 32))) { 748 if (Features2 & (1 << (FEATURE_SHA - 32))) { 749 *Type = INTEL_GOLDMONT; 750 } else { 751 *Type = INTEL_COREI7; 752 *Subtype = INTEL_COREI7_SKYLAKE; 753 } 754 break; 755 } 756 if (Features2 & (1 << (FEATURE_ADX - 32))) { 757 *Type = INTEL_COREI7; 758 *Subtype = INTEL_COREI7_BROADWELL; 759 break; 760 } 761 if (Features & (1 << FEATURE_AVX2)) { 762 *Type = INTEL_COREI7; 763 *Subtype = INTEL_COREI7_HASWELL; 764 break; 765 } 766 if (Features & (1 << FEATURE_AVX)) { 767 *Type = INTEL_COREI7; 768 *Subtype = INTEL_COREI7_SANDYBRIDGE; 769 break; 770 } 771 if (Features & (1 << FEATURE_SSE4_2)) { 772 if (Features2 & (1 << (FEATURE_MOVBE - 32))) { 773 *Type = INTEL_SILVERMONT; 774 } else { 775 *Type = INTEL_COREI7; 776 *Subtype = INTEL_COREI7_NEHALEM; 777 } 778 break; 779 } 780 if (Features & (1 << FEATURE_SSE4_1)) { 781 *Type = INTEL_CORE2; // "penryn" 782 *Subtype = INTEL_CORE2_45; 783 break; 784 } 785 if (Features & (1 << FEATURE_SSSE3)) { 786 if (Features2 & (1 << (FEATURE_MOVBE - 32))) { 787 *Type = INTEL_BONNELL; // "bonnell" 788 } else { 789 *Type = INTEL_CORE2; // "core2" 790 *Subtype = INTEL_CORE2_65; 791 } 792 break; 793 } 794 if (Features2 & (1 << (FEATURE_EM64T - 32))) { 795 *Type = INTEL_CORE2; // "core2" 796 *Subtype = INTEL_CORE2_65; 797 break; 798 } 799 if (Features & (1 << FEATURE_SSE3)) { 800 *Type = INTEL_CORE_DUO; 801 break; 802 } 803 if (Features & (1 << FEATURE_SSE2)) { 804 *Type = INTEL_PENTIUM_M; 805 break; 806 } 807 if (Features & (1 << FEATURE_SSE)) { 808 *Type = INTEL_PENTIUM_III; 809 break; 810 } 811 if (Features & (1 << FEATURE_MMX)) { 812 *Type = INTEL_PENTIUM_II; 813 break; 814 } 815 *Type = INTEL_PENTIUM_PRO; 816 break; 817 } 818 break; 819 case 15: { 820 if (Features2 & (1 << (FEATURE_EM64T - 32))) { 821 *Type = INTEL_NOCONA; 822 break; 823 } 824 if (Features & (1 << FEATURE_SSE3)) { 825 *Type = INTEL_PRESCOTT; 826 break; 827 } 828 *Type = INTEL_PENTIUM_IV; 829 break; 830 } 831 default: 832 break; /*"generic"*/ 833 } 834 } 835 836 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 837 unsigned Features, unsigned *Type, 838 unsigned *Subtype) { 839 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 840 // appears to be no way to generate the wide variety of AMD-specific targets 841 // from the information returned from CPUID. 842 switch (Family) { 843 case 4: 844 *Type = AMD_i486; 845 break; 846 case 5: 847 *Type = AMDPENTIUM; 848 switch (Model) { 849 case 6: 850 case 7: 851 *Subtype = AMDPENTIUM_K6; 852 break; // "k6" 853 case 8: 854 *Subtype = AMDPENTIUM_K62; 855 break; // "k6-2" 856 case 9: 857 case 13: 858 *Subtype = AMDPENTIUM_K63; 859 break; // "k6-3" 860 case 10: 861 *Subtype = AMDPENTIUM_GEODE; 862 break; // "geode" 863 } 864 break; 865 case 6: 866 if (Features & (1 << FEATURE_SSE)) { 867 *Type = AMD_ATHLON_XP; 868 break; // "athlon-xp" 869 } 870 *Type = AMD_ATHLON; 871 break; // "athlon" 872 case 15: 873 if (Features & (1 << FEATURE_SSE3)) { 874 *Type = AMD_K8SSE3; 875 break; // "k8-sse3" 876 } 877 *Type = AMD_K8; 878 break; // "k8" 879 case 16: 880 *Type = AMDFAM10H; // "amdfam10" 881 switch (Model) { 882 case 2: 883 *Subtype = AMDFAM10H_BARCELONA; 884 break; 885 case 4: 886 *Subtype = AMDFAM10H_SHANGHAI; 887 break; 888 case 8: 889 *Subtype = AMDFAM10H_ISTANBUL; 890 break; 891 } 892 break; 893 case 20: 894 *Type = AMD_BTVER1; 895 break; // "btver1"; 896 case 21: 897 *Type = AMDFAM15H; 898 if (Model >= 0x60 && Model <= 0x7f) { 899 *Subtype = AMDFAM15H_BDVER4; 900 break; // "bdver4"; 60h-7Fh: Excavator 901 } 902 if (Model >= 0x30 && Model <= 0x3f) { 903 *Subtype = AMDFAM15H_BDVER3; 904 break; // "bdver3"; 30h-3Fh: Steamroller 905 } 906 if (Model >= 0x10 && Model <= 0x1f) { 907 *Subtype = AMDFAM15H_BDVER2; 908 break; // "bdver2"; 10h-1Fh: Piledriver 909 } 910 if (Model <= 0x0f) { 911 *Subtype = AMDFAM15H_BDVER1; 912 break; // "bdver1"; 00h-0Fh: Bulldozer 913 } 914 break; 915 case 22: 916 *Type = AMD_BTVER2; 917 break; // "btver2" 918 case 23: 919 *Type = AMDFAM17H; 920 *Subtype = AMDFAM17H_ZNVER1; 921 break; 922 default: 923 break; // "generic" 924 } 925 } 926 927 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 928 unsigned *FeaturesOut, 929 unsigned *Features2Out) { 930 unsigned Features = 0; 931 unsigned Features2 = 0; 932 unsigned EAX, EBX; 933 934 if ((EDX >> 15) & 1) 935 Features |= 1 << FEATURE_CMOV; 936 if ((EDX >> 23) & 1) 937 Features |= 1 << FEATURE_MMX; 938 if ((EDX >> 25) & 1) 939 Features |= 1 << FEATURE_SSE; 940 if ((EDX >> 26) & 1) 941 Features |= 1 << FEATURE_SSE2; 942 943 if ((ECX >> 0) & 1) 944 Features |= 1 << FEATURE_SSE3; 945 if ((ECX >> 1) & 1) 946 Features |= 1 << FEATURE_PCLMUL; 947 if ((ECX >> 9) & 1) 948 Features |= 1 << FEATURE_SSSE3; 949 if ((ECX >> 12) & 1) 950 Features |= 1 << FEATURE_FMA; 951 if ((ECX >> 19) & 1) 952 Features |= 1 << FEATURE_SSE4_1; 953 if ((ECX >> 20) & 1) 954 Features |= 1 << FEATURE_SSE4_2; 955 if ((ECX >> 23) & 1) 956 Features |= 1 << FEATURE_POPCNT; 957 if ((ECX >> 25) & 1) 958 Features |= 1 << FEATURE_AES; 959 960 if ((ECX >> 22) & 1) 961 Features2 |= 1 << (FEATURE_MOVBE - 32); 962 963 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 964 // indicates that the AVX registers will be saved and restored on context 965 // switch, then we have full AVX support. 966 const unsigned AVXBits = (1 << 27) | (1 << 28); 967 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 968 ((EAX & 0x6) == 0x6); 969 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 970 971 if (HasAVX) 972 Features |= 1 << FEATURE_AVX; 973 974 bool HasLeaf7 = 975 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 976 977 if (HasLeaf7 && ((EBX >> 3) & 1)) 978 Features |= 1 << FEATURE_BMI; 979 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 980 Features |= 1 << FEATURE_AVX2; 981 if (HasLeaf7 && ((EBX >> 9) & 1)) 982 Features |= 1 << FEATURE_BMI2; 983 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 984 Features |= 1 << FEATURE_AVX512F; 985 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 986 Features |= 1 << FEATURE_AVX512DQ; 987 if (HasLeaf7 && ((EBX >> 19) & 1)) 988 Features2 |= 1 << (FEATURE_ADX - 32); 989 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 990 Features |= 1 << FEATURE_AVX512IFMA; 991 if (HasLeaf7 && ((EBX >> 23) & 1)) 992 Features2 |= 1 << (FEATURE_CLFLUSHOPT - 32); 993 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 994 Features |= 1 << FEATURE_AVX512PF; 995 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 996 Features |= 1 << FEATURE_AVX512ER; 997 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 998 Features |= 1 << FEATURE_AVX512CD; 999 if (HasLeaf7 && ((EBX >> 29) & 1)) 1000 Features2 |= 1 << (FEATURE_SHA - 32); 1001 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 1002 Features |= 1 << FEATURE_AVX512BW; 1003 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 1004 Features |= 1 << FEATURE_AVX512VL; 1005 1006 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 1007 Features |= 1 << FEATURE_AVX512VBMI; 1008 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1009 Features |= 1 << FEATURE_AVX512VPOPCNTDQ; 1010 1011 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1012 Features |= 1 << FEATURE_AVX5124VNNIW; 1013 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1014 Features |= 1 << FEATURE_AVX5124FMAPS; 1015 1016 unsigned MaxExtLevel; 1017 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1018 1019 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1020 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1021 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1022 Features |= 1 << FEATURE_SSE4_A; 1023 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1024 Features |= 1 << FEATURE_XOP; 1025 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1026 Features |= 1 << FEATURE_FMA4; 1027 1028 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1029 Features2 |= 1 << (FEATURE_EM64T - 32); 1030 1031 *FeaturesOut = Features; 1032 *Features2Out = Features2; 1033 } 1034 1035 StringRef sys::getHostCPUName() { 1036 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1037 unsigned MaxLeaf, Vendor; 1038 1039 #if defined(__GNUC__) || defined(__clang__) 1040 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here 1041 // and simplify it to not invoke __cpuid (like cpu_model.c in 1042 // compiler-rt/lib/builtins/cpu_model.c? 1043 // Opting for the second option. 1044 if(!isCpuIdSupported()) 1045 return "generic"; 1046 #endif 1047 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) 1048 return "generic"; 1049 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1050 1051 unsigned Brand_id = EBX & 0xff; 1052 unsigned Family = 0, Model = 0; 1053 unsigned Features = 0, Features2 = 0; 1054 detectX86FamilyModel(EAX, &Family, &Model); 1055 getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2); 1056 1057 unsigned Type = 0; 1058 unsigned Subtype = 0; 1059 1060 if (Vendor == SIG_INTEL) { 1061 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, 1062 Features2, &Type, &Subtype); 1063 switch (Type) { 1064 case INTEL_i386: 1065 return "i386"; 1066 case INTEL_i486: 1067 return "i486"; 1068 case INTEL_PENTIUM: 1069 return "pentium"; 1070 case INTEL_PENTIUM_MMX: 1071 return "pentium-mmx"; 1072 case INTEL_PENTIUM_PRO: 1073 return "pentiumpro"; 1074 case INTEL_PENTIUM_II: 1075 return "pentium2"; 1076 case INTEL_PENTIUM_III: 1077 return "pentium3"; 1078 case INTEL_PENTIUM_IV: 1079 return "pentium4"; 1080 case INTEL_PENTIUM_M: 1081 return "pentium-m"; 1082 case INTEL_CORE_DUO: 1083 return "yonah"; 1084 case INTEL_CORE2: 1085 switch (Subtype) { 1086 case INTEL_CORE2_65: 1087 return "core2"; 1088 case INTEL_CORE2_45: 1089 return "penryn"; 1090 default: 1091 llvm_unreachable("Unexpected subtype!"); 1092 } 1093 case INTEL_COREI7: 1094 switch (Subtype) { 1095 case INTEL_COREI7_NEHALEM: 1096 return "nehalem"; 1097 case INTEL_COREI7_WESTMERE: 1098 return "westmere"; 1099 case INTEL_COREI7_SANDYBRIDGE: 1100 return "sandybridge"; 1101 case INTEL_COREI7_IVYBRIDGE: 1102 return "ivybridge"; 1103 case INTEL_COREI7_HASWELL: 1104 return "haswell"; 1105 case INTEL_COREI7_BROADWELL: 1106 return "broadwell"; 1107 case INTEL_COREI7_SKYLAKE: 1108 return "skylake"; 1109 case INTEL_COREI7_SKYLAKE_AVX512: 1110 return "skylake-avx512"; 1111 default: 1112 llvm_unreachable("Unexpected subtype!"); 1113 } 1114 case INTEL_BONNELL: 1115 return "bonnell"; 1116 case INTEL_SILVERMONT: 1117 return "silvermont"; 1118 case INTEL_GOLDMONT: 1119 return "goldmont"; 1120 case INTEL_KNL: 1121 return "knl"; 1122 case INTEL_KNM: 1123 return "knm"; 1124 case INTEL_NOCONA: 1125 return "nocona"; 1126 case INTEL_PRESCOTT: 1127 return "prescott"; 1128 default: 1129 break; 1130 } 1131 } else if (Vendor == SIG_AMD) { 1132 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1133 switch (Type) { 1134 case AMD_i486: 1135 return "i486"; 1136 case AMDPENTIUM: 1137 switch (Subtype) { 1138 case AMDPENTIUM_K6: 1139 return "k6"; 1140 case AMDPENTIUM_K62: 1141 return "k6-2"; 1142 case AMDPENTIUM_K63: 1143 return "k6-3"; 1144 case AMDPENTIUM_GEODE: 1145 return "geode"; 1146 default: 1147 return "pentium"; 1148 } 1149 case AMD_ATHLON: 1150 return "athlon"; 1151 case AMD_ATHLON_XP: 1152 return "athlon-xp"; 1153 case AMD_K8: 1154 return "k8"; 1155 case AMD_K8SSE3: 1156 return "k8-sse3"; 1157 case AMDFAM10H: 1158 return "amdfam10"; 1159 case AMD_BTVER1: 1160 return "btver1"; 1161 case AMDFAM15H: 1162 switch (Subtype) { 1163 default: // There are gaps in the subtype detection. 1164 case AMDFAM15H_BDVER1: 1165 return "bdver1"; 1166 case AMDFAM15H_BDVER2: 1167 return "bdver2"; 1168 case AMDFAM15H_BDVER3: 1169 return "bdver3"; 1170 case AMDFAM15H_BDVER4: 1171 return "bdver4"; 1172 } 1173 case AMD_BTVER2: 1174 return "btver2"; 1175 case AMDFAM17H: 1176 return "znver1"; 1177 default: 1178 break; 1179 } 1180 } 1181 return "generic"; 1182 } 1183 1184 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1185 StringRef sys::getHostCPUName() { 1186 host_basic_info_data_t hostInfo; 1187 mach_msg_type_number_t infoCount; 1188 1189 infoCount = HOST_BASIC_INFO_COUNT; 1190 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo, 1191 &infoCount); 1192 1193 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1194 return "generic"; 1195 1196 switch (hostInfo.cpu_subtype) { 1197 case CPU_SUBTYPE_POWERPC_601: 1198 return "601"; 1199 case CPU_SUBTYPE_POWERPC_602: 1200 return "602"; 1201 case CPU_SUBTYPE_POWERPC_603: 1202 return "603"; 1203 case CPU_SUBTYPE_POWERPC_603e: 1204 return "603e"; 1205 case CPU_SUBTYPE_POWERPC_603ev: 1206 return "603ev"; 1207 case CPU_SUBTYPE_POWERPC_604: 1208 return "604"; 1209 case CPU_SUBTYPE_POWERPC_604e: 1210 return "604e"; 1211 case CPU_SUBTYPE_POWERPC_620: 1212 return "620"; 1213 case CPU_SUBTYPE_POWERPC_750: 1214 return "750"; 1215 case CPU_SUBTYPE_POWERPC_7400: 1216 return "7400"; 1217 case CPU_SUBTYPE_POWERPC_7450: 1218 return "7450"; 1219 case CPU_SUBTYPE_POWERPC_970: 1220 return "970"; 1221 default:; 1222 } 1223 1224 return "generic"; 1225 } 1226 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1227 StringRef sys::getHostCPUName() { 1228 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1229 const StringRef& Content = P ? P->getBuffer() : ""; 1230 return detail::getHostCPUNameForPowerPC(Content); 1231 } 1232 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1233 StringRef sys::getHostCPUName() { 1234 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1235 const StringRef& Content = P ? P->getBuffer() : ""; 1236 return detail::getHostCPUNameForARM(Content); 1237 } 1238 #elif defined(__linux__) && defined(__s390x__) 1239 StringRef sys::getHostCPUName() { 1240 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1241 const StringRef& Content = P ? P->getBuffer() : ""; 1242 return detail::getHostCPUNameForS390x(Content); 1243 } 1244 #else 1245 StringRef sys::getHostCPUName() { return "generic"; } 1246 #endif 1247 1248 #if defined(__linux__) && defined(__x86_64__) 1249 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1250 // using the number of unique physical/core id pairs. The following 1251 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1252 static int computeHostNumPhysicalCores() { 1253 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1254 // mmapped because it appears to have 0 size. 1255 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1256 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1257 if (std::error_code EC = Text.getError()) { 1258 llvm::errs() << "Can't read " 1259 << "/proc/cpuinfo: " << EC.message() << "\n"; 1260 return -1; 1261 } 1262 SmallVector<StringRef, 8> strs; 1263 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1264 /*KeepEmpty=*/false); 1265 int CurPhysicalId = -1; 1266 int CurCoreId = -1; 1267 SmallSet<std::pair<int, int>, 32> UniqueItems; 1268 for (auto &Line : strs) { 1269 Line = Line.trim(); 1270 if (!Line.startswith("physical id") && !Line.startswith("core id")) 1271 continue; 1272 std::pair<StringRef, StringRef> Data = Line.split(':'); 1273 auto Name = Data.first.trim(); 1274 auto Val = Data.second.trim(); 1275 if (Name == "physical id") { 1276 assert(CurPhysicalId == -1 && 1277 "Expected a core id before seeing another physical id"); 1278 Val.getAsInteger(10, CurPhysicalId); 1279 } 1280 if (Name == "core id") { 1281 assert(CurCoreId == -1 && 1282 "Expected a physical id before seeing another core id"); 1283 Val.getAsInteger(10, CurCoreId); 1284 } 1285 if (CurPhysicalId != -1 && CurCoreId != -1) { 1286 UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId)); 1287 CurPhysicalId = -1; 1288 CurCoreId = -1; 1289 } 1290 } 1291 return UniqueItems.size(); 1292 } 1293 #elif defined(__APPLE__) && defined(__x86_64__) 1294 #include <sys/param.h> 1295 #include <sys/sysctl.h> 1296 1297 // Gets the number of *physical cores* on the machine. 1298 static int computeHostNumPhysicalCores() { 1299 uint32_t count; 1300 size_t len = sizeof(count); 1301 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1302 if (count < 1) { 1303 int nm[2]; 1304 nm[0] = CTL_HW; 1305 nm[1] = HW_AVAILCPU; 1306 sysctl(nm, 2, &count, &len, NULL, 0); 1307 if (count < 1) 1308 return -1; 1309 } 1310 return count; 1311 } 1312 #else 1313 // On other systems, return -1 to indicate unknown. 1314 static int computeHostNumPhysicalCores() { return -1; } 1315 #endif 1316 1317 int sys::getHostNumPhysicalCores() { 1318 static int NumCores = computeHostNumPhysicalCores(); 1319 return NumCores; 1320 } 1321 1322 #if defined(__i386__) || defined(_M_IX86) || \ 1323 defined(__x86_64__) || defined(_M_X64) 1324 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1325 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1326 unsigned MaxLevel; 1327 union { 1328 unsigned u[3]; 1329 char c[12]; 1330 } text; 1331 1332 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1333 MaxLevel < 1) 1334 return false; 1335 1336 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1337 1338 Features["cmov"] = (EDX >> 15) & 1; 1339 Features["mmx"] = (EDX >> 23) & 1; 1340 Features["sse"] = (EDX >> 25) & 1; 1341 Features["sse2"] = (EDX >> 26) & 1; 1342 Features["sse3"] = (ECX >> 0) & 1; 1343 Features["ssse3"] = (ECX >> 9) & 1; 1344 Features["sse4.1"] = (ECX >> 19) & 1; 1345 Features["sse4.2"] = (ECX >> 20) & 1; 1346 1347 Features["pclmul"] = (ECX >> 1) & 1; 1348 Features["cx16"] = (ECX >> 13) & 1; 1349 Features["movbe"] = (ECX >> 22) & 1; 1350 Features["popcnt"] = (ECX >> 23) & 1; 1351 Features["aes"] = (ECX >> 25) & 1; 1352 Features["rdrnd"] = (ECX >> 30) & 1; 1353 1354 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1355 // indicates that the AVX registers will be saved and restored on context 1356 // switch, then we have full AVX support. 1357 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1358 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1359 Features["avx"] = HasAVXSave; 1360 Features["fma"] = HasAVXSave && (ECX >> 12) & 1; 1361 Features["f16c"] = HasAVXSave && (ECX >> 29) & 1; 1362 1363 // Only enable XSAVE if OS has enabled support for saving YMM state. 1364 Features["xsave"] = HasAVXSave && (ECX >> 26) & 1; 1365 1366 // AVX512 requires additional context to be saved by the OS. 1367 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1368 1369 unsigned MaxExtLevel; 1370 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1371 1372 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1373 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1374 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1375 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1376 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1377 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1378 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1379 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1380 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1381 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1382 1383 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1384 !getX86CpuIDAndInfoEx(0x80000008,0x0, &EAX, &EBX, &ECX, &EDX); 1385 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1386 1387 bool HasLeaf7 = 1388 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1389 1390 // AVX2 is only supported if we have the OS save support from AVX. 1391 Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1); 1392 1393 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1394 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1395 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1396 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1397 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1398 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1399 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1400 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1401 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1402 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1403 1404 // AVX512 is only supported if the OS supports the context save for it. 1405 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1406 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1407 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1408 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1409 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1410 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1411 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1412 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1413 1414 Features["prefetchwt1"] = HasLeaf7 && (ECX & 1); 1415 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1416 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1417 // Enable protection keys 1418 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1419 1420 bool HasLeafD = MaxLevel >= 0xd && 1421 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1422 1423 // Only enable XSAVE if OS has enabled support for saving YMM state. 1424 Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1); 1425 Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1); 1426 Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1); 1427 1428 return true; 1429 } 1430 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1431 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1432 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1433 if (!P) 1434 return false; 1435 1436 SmallVector<StringRef, 32> Lines; 1437 P->getBuffer().split(Lines, "\n"); 1438 1439 SmallVector<StringRef, 32> CPUFeatures; 1440 1441 // Look for the CPU features. 1442 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1443 if (Lines[I].startswith("Features")) { 1444 Lines[I].split(CPUFeatures, ' '); 1445 break; 1446 } 1447 1448 #if defined(__aarch64__) 1449 // Keep track of which crypto features we have seen 1450 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1451 uint32_t crypto = 0; 1452 #endif 1453 1454 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1455 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1456 #if defined(__aarch64__) 1457 .Case("asimd", "neon") 1458 .Case("fp", "fp-armv8") 1459 .Case("crc32", "crc") 1460 #else 1461 .Case("half", "fp16") 1462 .Case("neon", "neon") 1463 .Case("vfpv3", "vfp3") 1464 .Case("vfpv3d16", "d16") 1465 .Case("vfpv4", "vfp4") 1466 .Case("idiva", "hwdiv-arm") 1467 .Case("idivt", "hwdiv") 1468 #endif 1469 .Default(""); 1470 1471 #if defined(__aarch64__) 1472 // We need to check crypto separately since we need all of the crypto 1473 // extensions to enable the subtarget feature 1474 if (CPUFeatures[I] == "aes") 1475 crypto |= CAP_AES; 1476 else if (CPUFeatures[I] == "pmull") 1477 crypto |= CAP_PMULL; 1478 else if (CPUFeatures[I] == "sha1") 1479 crypto |= CAP_SHA1; 1480 else if (CPUFeatures[I] == "sha2") 1481 crypto |= CAP_SHA2; 1482 #endif 1483 1484 if (LLVMFeatureStr != "") 1485 Features[LLVMFeatureStr] = true; 1486 } 1487 1488 #if defined(__aarch64__) 1489 // If we have all crypto bits we can add the feature 1490 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1491 Features["crypto"] = true; 1492 #endif 1493 1494 return true; 1495 } 1496 #else 1497 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1498 #endif 1499 1500 std::string sys::getProcessTriple() { 1501 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1502 Triple PT(Triple::normalize(TargetTripleString)); 1503 1504 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1505 PT = PT.get64BitArchVariant(); 1506 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1507 PT = PT.get32BitArchVariant(); 1508 1509 return PT.str(); 1510 } 1511