1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the operating system Host concept. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Support/Host.h" 15 #include "llvm/ADT/SmallSet.h" 16 #include "llvm/ADT/SmallVector.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include <assert.h> 26 #include <string.h> 27 28 // Include the platform-specific parts of this class. 29 #ifdef LLVM_ON_UNIX 30 #include "Unix/Host.inc" 31 #endif 32 #ifdef LLVM_ON_WIN32 33 #include "Windows/Host.inc" 34 #endif 35 #ifdef _MSC_VER 36 #include <intrin.h> 37 #endif 38 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 39 #include <mach/host_info.h> 40 #include <mach/mach.h> 41 #include <mach/mach_host.h> 42 #include <mach/machine.h> 43 #endif 44 45 #define DEBUG_TYPE "host-detection" 46 47 //===----------------------------------------------------------------------===// 48 // 49 // Implementations of the CPU detection routines 50 // 51 //===----------------------------------------------------------------------===// 52 53 using namespace llvm; 54 55 static std::unique_ptr<llvm::MemoryBuffer> 56 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 57 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 58 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 59 if (std::error_code EC = Text.getError()) { 60 llvm::errs() << "Can't read " 61 << "/proc/cpuinfo: " << EC.message() << "\n"; 62 return nullptr; 63 } 64 return std::move(*Text); 65 } 66 67 StringRef sys::detail::getHostCPUNameForPowerPC( 68 const StringRef &ProcCpuinfoContent) { 69 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 70 // and so we must use an operating-system interface to determine the current 71 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 72 const char *generic = "generic"; 73 74 // The cpu line is second (after the 'processor: 0' line), so if this 75 // buffer is too small then something has changed (or is wrong). 76 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 77 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 78 79 StringRef::const_iterator CIP = CPUInfoStart; 80 81 StringRef::const_iterator CPUStart = 0; 82 size_t CPULen = 0; 83 84 // We need to find the first line which starts with cpu, spaces, and a colon. 85 // After the colon, there may be some additional spaces and then the cpu type. 86 while (CIP < CPUInfoEnd && CPUStart == 0) { 87 if (CIP < CPUInfoEnd && *CIP == '\n') 88 ++CIP; 89 90 if (CIP < CPUInfoEnd && *CIP == 'c') { 91 ++CIP; 92 if (CIP < CPUInfoEnd && *CIP == 'p') { 93 ++CIP; 94 if (CIP < CPUInfoEnd && *CIP == 'u') { 95 ++CIP; 96 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 97 ++CIP; 98 99 if (CIP < CPUInfoEnd && *CIP == ':') { 100 ++CIP; 101 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 102 ++CIP; 103 104 if (CIP < CPUInfoEnd) { 105 CPUStart = CIP; 106 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 107 *CIP != ',' && *CIP != '\n')) 108 ++CIP; 109 CPULen = CIP - CPUStart; 110 } 111 } 112 } 113 } 114 } 115 116 if (CPUStart == 0) 117 while (CIP < CPUInfoEnd && *CIP != '\n') 118 ++CIP; 119 } 120 121 if (CPUStart == 0) 122 return generic; 123 124 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 125 .Case("604e", "604e") 126 .Case("604", "604") 127 .Case("7400", "7400") 128 .Case("7410", "7400") 129 .Case("7447", "7400") 130 .Case("7455", "7450") 131 .Case("G4", "g4") 132 .Case("POWER4", "970") 133 .Case("PPC970FX", "970") 134 .Case("PPC970MP", "970") 135 .Case("G5", "g5") 136 .Case("POWER5", "g5") 137 .Case("A2", "a2") 138 .Case("POWER6", "pwr6") 139 .Case("POWER7", "pwr7") 140 .Case("POWER8", "pwr8") 141 .Case("POWER8E", "pwr8") 142 .Case("POWER8NVL", "pwr8") 143 .Case("POWER9", "pwr9") 144 .Default(generic); 145 } 146 147 StringRef sys::detail::getHostCPUNameForARM( 148 const StringRef &ProcCpuinfoContent) { 149 // The cpuid register on arm is not accessible from user space. On Linux, 150 // it is exposed through the /proc/cpuinfo file. 151 152 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 153 // in all cases. 154 SmallVector<StringRef, 32> Lines; 155 ProcCpuinfoContent.split(Lines, "\n"); 156 157 // Look for the CPU implementer line. 158 StringRef Implementer; 159 StringRef Hardware; 160 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 161 if (Lines[I].startswith("CPU implementer")) 162 Implementer = Lines[I].substr(15).ltrim("\t :"); 163 if (Lines[I].startswith("Hardware")) 164 Hardware = Lines[I].substr(8).ltrim("\t :"); 165 } 166 167 if (Implementer == "0x41") { // ARM Ltd. 168 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 169 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 170 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 171 return "cortex-a53"; 172 173 174 // Look for the CPU part line. 175 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 176 if (Lines[I].startswith("CPU part")) 177 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 178 // values correspond to the "Part number" in the CP15/c0 register. The 179 // contents are specified in the various processor manuals. 180 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 181 .Case("0x926", "arm926ej-s") 182 .Case("0xb02", "mpcore") 183 .Case("0xb36", "arm1136j-s") 184 .Case("0xb56", "arm1156t2-s") 185 .Case("0xb76", "arm1176jz-s") 186 .Case("0xc08", "cortex-a8") 187 .Case("0xc09", "cortex-a9") 188 .Case("0xc0f", "cortex-a15") 189 .Case("0xc20", "cortex-m0") 190 .Case("0xc23", "cortex-m3") 191 .Case("0xc24", "cortex-m4") 192 .Case("0xd04", "cortex-a35") 193 .Case("0xd03", "cortex-a53") 194 .Case("0xd07", "cortex-a57") 195 .Case("0xd08", "cortex-a72") 196 .Case("0xd09", "cortex-a73") 197 .Default("generic"); 198 } 199 200 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 201 // Look for the CPU part line. 202 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 203 if (Lines[I].startswith("CPU part")) 204 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 205 // values correspond to the "Part number" in the CP15/c0 register. The 206 // contents are specified in the various processor manuals. 207 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 208 .Case("0x06f", "krait") // APQ8064 209 .Case("0x201", "kryo") 210 .Case("0x205", "kryo") 211 .Case("0x211", "kryo") 212 .Case("0x800", "cortex-a73") 213 .Case("0x801", "cortex-a73") 214 .Default("generic"); 215 216 return "generic"; 217 } 218 219 StringRef sys::detail::getHostCPUNameForS390x( 220 const StringRef &ProcCpuinfoContent) { 221 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 222 223 // The "processor 0:" line comes after a fair amount of other information, 224 // including a cache breakdown, but this should be plenty. 225 SmallVector<StringRef, 32> Lines; 226 ProcCpuinfoContent.split(Lines, "\n"); 227 228 // Look for the CPU features. 229 SmallVector<StringRef, 32> CPUFeatures; 230 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 231 if (Lines[I].startswith("features")) { 232 size_t Pos = Lines[I].find(":"); 233 if (Pos != StringRef::npos) { 234 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 235 break; 236 } 237 } 238 239 // We need to check for the presence of vector support independently of 240 // the machine type, since we may only use the vector register set when 241 // supported by the kernel (and hypervisor). 242 bool HaveVectorSupport = false; 243 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 244 if (CPUFeatures[I] == "vx") 245 HaveVectorSupport = true; 246 } 247 248 // Now check the processor machine type. 249 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 250 if (Lines[I].startswith("processor ")) { 251 size_t Pos = Lines[I].find("machine = "); 252 if (Pos != StringRef::npos) { 253 Pos += sizeof("machine = ") - 1; 254 unsigned int Id; 255 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 256 if (Id >= 3906 && HaveVectorSupport) 257 return "z14"; 258 if (Id >= 2964 && HaveVectorSupport) 259 return "z13"; 260 if (Id >= 2827) 261 return "zEC12"; 262 if (Id >= 2817) 263 return "z196"; 264 } 265 } 266 break; 267 } 268 } 269 270 return "generic"; 271 } 272 273 StringRef sys::detail::getHostCPUNameForBPF() { 274 #if !defined(__linux__) || !defined(__x86_64__) 275 return "generic"; 276 #else 277 uint8_t insns[40] __attribute__ ((aligned (8))) = 278 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 279 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 280 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 281 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 282 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 283 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 284 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 285 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 286 /* BPF_EXIT_INSN() */ 287 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 288 289 struct bpf_prog_load_attr { 290 uint32_t prog_type; 291 uint32_t insn_cnt; 292 uint64_t insns; 293 uint64_t license; 294 uint32_t log_level; 295 uint32_t log_size; 296 uint64_t log_buf; 297 uint32_t kern_version; 298 uint32_t prog_flags; 299 } attr = {}; 300 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 301 attr.insn_cnt = 5; 302 attr.insns = (uint64_t)insns; 303 attr.license = (uint64_t)"DUMMY"; 304 305 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 306 if (fd >= 0) { 307 close(fd); 308 return "v2"; 309 } 310 return "v1"; 311 #endif 312 } 313 314 #if defined(__i386__) || defined(_M_IX86) || \ 315 defined(__x86_64__) || defined(_M_X64) 316 317 enum VendorSignatures { 318 SIG_INTEL = 0x756e6547 /* Genu */, 319 SIG_AMD = 0x68747541 /* Auth */ 320 }; 321 322 enum ProcessorVendors { 323 VENDOR_INTEL = 1, 324 VENDOR_AMD, 325 VENDOR_OTHER, 326 VENDOR_MAX 327 }; 328 329 enum ProcessorTypes { 330 INTEL_BONNELL = 1, 331 INTEL_CORE2, 332 INTEL_COREI7, 333 AMDFAM10H, 334 AMDFAM15H, 335 INTEL_SILVERMONT, 336 INTEL_KNL, 337 AMD_BTVER1, 338 AMD_BTVER2, 339 AMDFAM17H, 340 // Entries below this are not in libgcc/compiler-rt. 341 INTEL_i386, 342 INTEL_i486, 343 INTEL_PENTIUM, 344 INTEL_PENTIUM_PRO, 345 INTEL_PENTIUM_II, 346 INTEL_PENTIUM_III, 347 INTEL_PENTIUM_IV, 348 INTEL_PENTIUM_M, 349 INTEL_CORE_DUO, 350 INTEL_X86_64, 351 INTEL_NOCONA, 352 INTEL_PRESCOTT, 353 AMD_i486, 354 AMDPENTIUM, 355 AMDATHLON, 356 INTEL_GOLDMONT, 357 CPU_TYPE_MAX 358 }; 359 360 enum ProcessorSubtypes { 361 INTEL_COREI7_NEHALEM = 1, 362 INTEL_COREI7_WESTMERE, 363 INTEL_COREI7_SANDYBRIDGE, 364 AMDFAM10H_BARCELONA, 365 AMDFAM10H_SHANGHAI, 366 AMDFAM10H_ISTANBUL, 367 AMDFAM15H_BDVER1, 368 AMDFAM15H_BDVER2, 369 AMDFAM15H_BDVER3, 370 AMDFAM15H_BDVER4, 371 AMDFAM17H_ZNVER1, 372 INTEL_COREI7_IVYBRIDGE, 373 INTEL_COREI7_HASWELL, 374 INTEL_COREI7_BROADWELL, 375 INTEL_COREI7_SKYLAKE, 376 INTEL_COREI7_SKYLAKE_AVX512, 377 // Entries below this are not in libgcc/compiler-rt. 378 INTEL_PENTIUM_MMX, 379 INTEL_CORE2_65, 380 INTEL_CORE2_45, 381 AMDPENTIUM_K6, 382 AMDPENTIUM_K62, 383 AMDPENTIUM_K63, 384 AMDPENTIUM_GEODE, 385 AMDATHLON_CLASSIC, 386 AMDATHLON_XP, 387 AMDATHLON_K8, 388 AMDATHLON_K8SSE3, 389 CPU_SUBTYPE_MAX 390 }; 391 392 enum ProcessorFeatures { 393 FEATURE_CMOV = 0, 394 FEATURE_MMX, 395 FEATURE_POPCNT, 396 FEATURE_SSE, 397 FEATURE_SSE2, 398 FEATURE_SSE3, 399 FEATURE_SSSE3, 400 FEATURE_SSE4_1, 401 FEATURE_SSE4_2, 402 FEATURE_AVX, 403 FEATURE_AVX2, 404 FEATURE_SSE4_A, 405 FEATURE_FMA4, 406 FEATURE_XOP, 407 FEATURE_FMA, 408 FEATURE_AVX512F, 409 FEATURE_BMI, 410 FEATURE_BMI2, 411 FEATURE_AES, 412 FEATURE_PCLMUL, 413 FEATURE_AVX512VL, 414 FEATURE_AVX512BW, 415 FEATURE_AVX512DQ, 416 FEATURE_AVX512CD, 417 FEATURE_AVX512ER, 418 FEATURE_AVX512PF, 419 FEATURE_AVX512VBMI, 420 FEATURE_AVX512IFMA, 421 FEATURE_AVX5124VNNIW, 422 FEATURE_AVX5124FMAPS, 423 FEATURE_AVX512VPOPCNTDQ, 424 // Only one bit free left in the first 32 features. 425 FEATURE_MOVBE = 32, 426 FEATURE_ADX, 427 FEATURE_EM64T, 428 FEATURE_CLFLUSHOPT, 429 FEATURE_SHA, 430 }; 431 432 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 433 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 434 // support. Consequently, for i386, the presence of CPUID is checked first 435 // via the corresponding eflags bit. 436 // Removal of cpuid.h header motivated by PR30384 437 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 438 // or test-suite, but are used in external projects e.g. libstdcxx 439 static bool isCpuIdSupported() { 440 #if defined(__GNUC__) || defined(__clang__) 441 #if defined(__i386__) 442 int __cpuid_supported; 443 __asm__(" pushfl\n" 444 " popl %%eax\n" 445 " movl %%eax,%%ecx\n" 446 " xorl $0x00200000,%%eax\n" 447 " pushl %%eax\n" 448 " popfl\n" 449 " pushfl\n" 450 " popl %%eax\n" 451 " movl $0,%0\n" 452 " cmpl %%eax,%%ecx\n" 453 " je 1f\n" 454 " movl $1,%0\n" 455 "1:" 456 : "=r"(__cpuid_supported) 457 : 458 : "eax", "ecx"); 459 if (!__cpuid_supported) 460 return false; 461 #endif 462 return true; 463 #endif 464 return true; 465 } 466 467 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 468 /// the specified arguments. If we can't run cpuid on the host, return true. 469 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 470 unsigned *rECX, unsigned *rEDX) { 471 #if defined(__GNUC__) || defined(__clang__) 472 #if defined(__x86_64__) 473 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 474 // FIXME: should we save this for Clang? 475 __asm__("movq\t%%rbx, %%rsi\n\t" 476 "cpuid\n\t" 477 "xchgq\t%%rbx, %%rsi\n\t" 478 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 479 : "a"(value)); 480 return false; 481 #elif defined(__i386__) 482 __asm__("movl\t%%ebx, %%esi\n\t" 483 "cpuid\n\t" 484 "xchgl\t%%ebx, %%esi\n\t" 485 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 486 : "a"(value)); 487 return false; 488 #else 489 return true; 490 #endif 491 #elif defined(_MSC_VER) 492 // The MSVC intrinsic is portable across x86 and x64. 493 int registers[4]; 494 __cpuid(registers, value); 495 *rEAX = registers[0]; 496 *rEBX = registers[1]; 497 *rECX = registers[2]; 498 *rEDX = registers[3]; 499 return false; 500 #else 501 return true; 502 #endif 503 } 504 505 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 506 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 507 /// return true. 508 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 509 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 510 unsigned *rEDX) { 511 #if defined(__GNUC__) || defined(__clang__) 512 #if defined(__x86_64__) 513 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 514 // FIXME: should we save this for Clang? 515 __asm__("movq\t%%rbx, %%rsi\n\t" 516 "cpuid\n\t" 517 "xchgq\t%%rbx, %%rsi\n\t" 518 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 519 : "a"(value), "c"(subleaf)); 520 return false; 521 #elif defined(__i386__) 522 __asm__("movl\t%%ebx, %%esi\n\t" 523 "cpuid\n\t" 524 "xchgl\t%%ebx, %%esi\n\t" 525 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 526 : "a"(value), "c"(subleaf)); 527 return false; 528 #else 529 return true; 530 #endif 531 #elif defined(_MSC_VER) 532 int registers[4]; 533 __cpuidex(registers, value, subleaf); 534 *rEAX = registers[0]; 535 *rEBX = registers[1]; 536 *rECX = registers[2]; 537 *rEDX = registers[3]; 538 return false; 539 #else 540 return true; 541 #endif 542 } 543 544 // Read control register 0 (XCR0). Used to detect features such as AVX. 545 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 546 #if defined(__GNUC__) || defined(__clang__) 547 // Check xgetbv; this uses a .byte sequence instead of the instruction 548 // directly because older assemblers do not include support for xgetbv and 549 // there is no easy way to conditionally compile based on the assembler used. 550 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 551 return false; 552 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 553 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 554 *rEAX = Result; 555 *rEDX = Result >> 32; 556 return false; 557 #else 558 return true; 559 #endif 560 } 561 562 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 563 unsigned *Model) { 564 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 565 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 566 if (*Family == 6 || *Family == 0xf) { 567 if (*Family == 0xf) 568 // Examine extended family ID if family ID is F. 569 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 570 // Examine extended model ID if family ID is 6 or F. 571 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 572 } 573 } 574 575 static void 576 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 577 unsigned Brand_id, unsigned Features, 578 unsigned Features2, unsigned *Type, 579 unsigned *Subtype) { 580 if (Brand_id != 0) 581 return; 582 switch (Family) { 583 case 3: 584 *Type = INTEL_i386; 585 break; 586 case 4: 587 switch (Model) { 588 case 0: // Intel486 DX processors 589 case 1: // Intel486 DX processors 590 case 2: // Intel486 SX processors 591 case 3: // Intel487 processors, IntelDX2 OverDrive processors, 592 // IntelDX2 processors 593 case 4: // Intel486 SL processor 594 case 5: // IntelSX2 processors 595 case 7: // Write-Back Enhanced IntelDX2 processors 596 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors 597 default: 598 *Type = INTEL_i486; 599 break; 600 } 601 break; 602 case 5: 603 switch (Model) { 604 case 1: // Pentium OverDrive processor for Pentium processor (60, 66), 605 // Pentium processors (60, 66) 606 case 2: // Pentium OverDrive processor for Pentium processor (75, 90, 607 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133, 608 // 150, 166, 200) 609 case 3: // Pentium OverDrive processors for Intel486 processor-based 610 // systems 611 *Type = INTEL_PENTIUM; 612 break; 613 case 4: // Pentium OverDrive processor with MMX technology for Pentium 614 // processor (75, 90, 100, 120, 133), Pentium processor with 615 // MMX technology (166, 200) 616 *Type = INTEL_PENTIUM; 617 *Subtype = INTEL_PENTIUM_MMX; 618 break; 619 default: 620 *Type = INTEL_PENTIUM; 621 break; 622 } 623 break; 624 case 6: 625 switch (Model) { 626 case 0x01: // Pentium Pro processor 627 *Type = INTEL_PENTIUM_PRO; 628 break; 629 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 630 // model 03 631 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 632 // model 05, and Intel Celeron processor, model 05 633 case 0x06: // Celeron processor, model 06 634 *Type = INTEL_PENTIUM_II; 635 break; 636 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 637 // processor, model 07 638 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 639 // model 08, and Celeron processor, model 08 640 case 0x0a: // Pentium III Xeon processor, model 0Ah 641 case 0x0b: // Pentium III processor, model 0Bh 642 *Type = INTEL_PENTIUM_III; 643 break; 644 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 645 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 646 // 0Dh. All processors are manufactured using the 90 nm process. 647 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 648 // Integrated Processor with Intel QuickAssist Technology 649 *Type = INTEL_PENTIUM_M; 650 break; 651 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 652 // 0Eh. All processors are manufactured using the 65 nm process. 653 *Type = INTEL_CORE_DUO; 654 break; // yonah 655 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 656 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 657 // mobile processor, Intel Core 2 Extreme processor, Intel 658 // Pentium Dual-Core processor, Intel Xeon processor, model 659 // 0Fh. All processors are manufactured using the 65 nm process. 660 case 0x16: // Intel Celeron processor model 16h. All processors are 661 // manufactured using the 65 nm process 662 *Type = INTEL_CORE2; // "core2" 663 *Subtype = INTEL_CORE2_65; 664 break; 665 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 666 // 17h. All processors are manufactured using the 45 nm process. 667 // 668 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 669 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 670 // the 45 nm process. 671 *Type = INTEL_CORE2; // "penryn" 672 *Subtype = INTEL_CORE2_45; 673 break; 674 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 675 // processors are manufactured using the 45 nm process. 676 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 677 // As found in a Summer 2010 model iMac. 678 case 0x1f: 679 case 0x2e: // Nehalem EX 680 *Type = INTEL_COREI7; // "nehalem" 681 *Subtype = INTEL_COREI7_NEHALEM; 682 break; 683 case 0x25: // Intel Core i7, laptop version. 684 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 685 // processors are manufactured using the 32 nm process. 686 case 0x2f: // Westmere EX 687 *Type = INTEL_COREI7; // "westmere" 688 *Subtype = INTEL_COREI7_WESTMERE; 689 break; 690 case 0x2a: // Intel Core i7 processor. All processors are manufactured 691 // using the 32 nm process. 692 case 0x2d: 693 *Type = INTEL_COREI7; //"sandybridge" 694 *Subtype = INTEL_COREI7_SANDYBRIDGE; 695 break; 696 case 0x3a: 697 case 0x3e: // Ivy Bridge EP 698 *Type = INTEL_COREI7; // "ivybridge" 699 *Subtype = INTEL_COREI7_IVYBRIDGE; 700 break; 701 702 // Haswell: 703 case 0x3c: 704 case 0x3f: 705 case 0x45: 706 case 0x46: 707 *Type = INTEL_COREI7; // "haswell" 708 *Subtype = INTEL_COREI7_HASWELL; 709 break; 710 711 // Broadwell: 712 case 0x3d: 713 case 0x47: 714 case 0x4f: 715 case 0x56: 716 *Type = INTEL_COREI7; // "broadwell" 717 *Subtype = INTEL_COREI7_BROADWELL; 718 break; 719 720 // Skylake: 721 case 0x4e: // Skylake mobile 722 case 0x5e: // Skylake desktop 723 case 0x8e: // Kaby Lake mobile 724 case 0x9e: // Kaby Lake desktop 725 *Type = INTEL_COREI7; // "skylake" 726 *Subtype = INTEL_COREI7_SKYLAKE; 727 break; 728 729 // Skylake Xeon: 730 case 0x55: 731 *Type = INTEL_COREI7; 732 *Subtype = INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 733 break; 734 735 case 0x1c: // Most 45 nm Intel Atom processors 736 case 0x26: // 45 nm Atom Lincroft 737 case 0x27: // 32 nm Atom Medfield 738 case 0x35: // 32 nm Atom Midview 739 case 0x36: // 32 nm Atom Midview 740 *Type = INTEL_BONNELL; 741 break; // "bonnell" 742 743 // Atom Silvermont codes from the Intel software optimization guide. 744 case 0x37: 745 case 0x4a: 746 case 0x4d: 747 case 0x5a: 748 case 0x5d: 749 case 0x4c: // really airmont 750 *Type = INTEL_SILVERMONT; 751 break; // "silvermont" 752 // Goldmont: 753 case 0x5c: 754 case 0x5f: 755 *Type = INTEL_GOLDMONT; 756 break; // "goldmont" 757 case 0x57: 758 *Type = INTEL_KNL; // knl 759 break; 760 761 default: // Unknown family 6 CPU, try to guess. 762 if (Features & (1 << FEATURE_AVX512F)) { 763 if (Features & (1 << FEATURE_AVX512VL)) { 764 *Type = INTEL_COREI7; 765 *Subtype = INTEL_COREI7_SKYLAKE_AVX512; 766 } else { 767 *Type = INTEL_KNL; // knl 768 } 769 break; 770 } 771 if (Features2 & (1 << (FEATURE_CLFLUSHOPT - 32))) { 772 if (Features2 & (1 << (FEATURE_SHA - 32))) { 773 *Type = INTEL_GOLDMONT; 774 } else { 775 *Type = INTEL_COREI7; 776 *Subtype = INTEL_COREI7_SKYLAKE; 777 } 778 break; 779 } 780 if (Features2 & (1 << (FEATURE_ADX - 32))) { 781 *Type = INTEL_COREI7; 782 *Subtype = INTEL_COREI7_BROADWELL; 783 break; 784 } 785 if (Features & (1 << FEATURE_AVX2)) { 786 *Type = INTEL_COREI7; 787 *Subtype = INTEL_COREI7_HASWELL; 788 break; 789 } 790 if (Features & (1 << FEATURE_AVX)) { 791 *Type = INTEL_COREI7; 792 *Subtype = INTEL_COREI7_SANDYBRIDGE; 793 break; 794 } 795 if (Features & (1 << FEATURE_SSE4_2)) { 796 if (Features2 & (1 << (FEATURE_MOVBE - 32))) { 797 *Type = INTEL_SILVERMONT; 798 } else { 799 *Type = INTEL_COREI7; 800 *Subtype = INTEL_COREI7_NEHALEM; 801 } 802 break; 803 } 804 if (Features & (1 << FEATURE_SSE4_1)) { 805 *Type = INTEL_CORE2; // "penryn" 806 *Subtype = INTEL_CORE2_45; 807 break; 808 } 809 if (Features & (1 << FEATURE_SSSE3)) { 810 if (Features2 & (1 << (FEATURE_MOVBE - 32))) { 811 *Type = INTEL_BONNELL; // "bonnell" 812 } else { 813 *Type = INTEL_CORE2; // "core2" 814 *Subtype = INTEL_CORE2_65; 815 } 816 break; 817 } 818 if (Features2 & (1 << (FEATURE_EM64T - 32))) { 819 *Type = INTEL_X86_64; 820 break; // x86-64 821 } 822 if (Features & (1 << FEATURE_SSE2)) { 823 *Type = INTEL_PENTIUM_M; 824 break; 825 } 826 if (Features & (1 << FEATURE_SSE)) { 827 *Type = INTEL_PENTIUM_III; 828 break; 829 } 830 if (Features & (1 << FEATURE_MMX)) { 831 *Type = INTEL_PENTIUM_II; 832 break; 833 } 834 *Type = INTEL_PENTIUM_PRO; 835 break; 836 } 837 break; 838 case 15: { 839 switch (Model) { 840 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are 841 // model 00h and manufactured using the 0.18 micron process. 842 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon 843 // processor MP, and Intel Celeron processor. All processors are 844 // model 01h and manufactured using the 0.18 micron process. 845 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M, 846 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron 847 // processor, and Mobile Intel Celeron processor. All processors 848 // are model 02h and manufactured using the 0.13 micron process. 849 *Type = ((Features2 & (1 << (FEATURE_EM64T - 32))) ? INTEL_X86_64 850 : INTEL_PENTIUM_IV); 851 break; 852 853 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D 854 // processor. All processors are model 03h and manufactured using 855 // the 90 nm process. 856 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition, 857 // Pentium D processor, Intel Xeon processor, Intel Xeon 858 // processor MP, Intel Celeron D processor. All processors are 859 // model 04h and manufactured using the 90 nm process. 860 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor 861 // Extreme Edition, Intel Xeon processor, Intel Xeon processor 862 // MP, Intel Celeron D processor. All processors are model 06h 863 // and manufactured using the 65 nm process. 864 *Type = ((Features2 & (1 << (FEATURE_EM64T - 32))) ? INTEL_NOCONA 865 : INTEL_PRESCOTT); 866 break; 867 868 default: 869 *Type = ((Features2 & (1 << (FEATURE_EM64T - 32))) ? INTEL_X86_64 870 : INTEL_PENTIUM_IV); 871 break; 872 } 873 break; 874 } 875 default: 876 break; /*"generic"*/ 877 } 878 } 879 880 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 881 unsigned Features, unsigned *Type, 882 unsigned *Subtype) { 883 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 884 // appears to be no way to generate the wide variety of AMD-specific targets 885 // from the information returned from CPUID. 886 switch (Family) { 887 case 4: 888 *Type = AMD_i486; 889 break; 890 case 5: 891 *Type = AMDPENTIUM; 892 switch (Model) { 893 case 6: 894 case 7: 895 *Subtype = AMDPENTIUM_K6; 896 break; // "k6" 897 case 8: 898 *Subtype = AMDPENTIUM_K62; 899 break; // "k6-2" 900 case 9: 901 case 13: 902 *Subtype = AMDPENTIUM_K63; 903 break; // "k6-3" 904 case 10: 905 *Subtype = AMDPENTIUM_GEODE; 906 break; // "geode" 907 } 908 break; 909 case 6: 910 *Type = AMDATHLON; 911 if (Features & (1 << FEATURE_SSE)) { 912 *Subtype = AMDATHLON_XP; 913 break; // "athlon-xp" 914 } 915 *Subtype = AMDATHLON_CLASSIC; 916 break; // "athlon" 917 case 15: 918 *Type = AMDATHLON; 919 if (Features & (1 << FEATURE_SSE3)) { 920 *Subtype = AMDATHLON_K8SSE3; 921 break; // "k8-sse3" 922 } 923 *Subtype = AMDATHLON_K8; 924 break; // "k8" 925 case 16: 926 *Type = AMDFAM10H; // "amdfam10" 927 switch (Model) { 928 case 2: 929 *Subtype = AMDFAM10H_BARCELONA; 930 break; 931 case 4: 932 *Subtype = AMDFAM10H_SHANGHAI; 933 break; 934 case 8: 935 *Subtype = AMDFAM10H_ISTANBUL; 936 break; 937 } 938 break; 939 case 20: 940 *Type = AMD_BTVER1; 941 break; // "btver1"; 942 case 21: 943 *Type = AMDFAM15H; 944 if (Model >= 0x60 && Model <= 0x7f) { 945 *Subtype = AMDFAM15H_BDVER4; 946 break; // "bdver4"; 60h-7Fh: Excavator 947 } 948 if (Model >= 0x30 && Model <= 0x3f) { 949 *Subtype = AMDFAM15H_BDVER3; 950 break; // "bdver3"; 30h-3Fh: Steamroller 951 } 952 if (Model >= 0x10 && Model <= 0x1f) { 953 *Subtype = AMDFAM15H_BDVER2; 954 break; // "bdver2"; 10h-1Fh: Piledriver 955 } 956 if (Model <= 0x0f) { 957 *Subtype = AMDFAM15H_BDVER1; 958 break; // "bdver1"; 00h-0Fh: Bulldozer 959 } 960 break; 961 case 22: 962 *Type = AMD_BTVER2; 963 break; // "btver2" 964 case 23: 965 *Type = AMDFAM17H; 966 *Subtype = AMDFAM17H_ZNVER1; 967 break; 968 default: 969 break; // "generic" 970 } 971 } 972 973 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 974 unsigned *FeaturesOut, 975 unsigned *Features2Out) { 976 unsigned Features = 0; 977 unsigned Features2 = 0; 978 unsigned EAX, EBX; 979 980 if ((EDX >> 15) & 1) 981 Features |= 1 << FEATURE_CMOV; 982 if ((EDX >> 23) & 1) 983 Features |= 1 << FEATURE_MMX; 984 if ((EDX >> 25) & 1) 985 Features |= 1 << FEATURE_SSE; 986 if ((EDX >> 26) & 1) 987 Features |= 1 << FEATURE_SSE2; 988 989 if ((ECX >> 0) & 1) 990 Features |= 1 << FEATURE_SSE3; 991 if ((ECX >> 1) & 1) 992 Features |= 1 << FEATURE_PCLMUL; 993 if ((ECX >> 9) & 1) 994 Features |= 1 << FEATURE_SSSE3; 995 if ((ECX >> 12) & 1) 996 Features |= 1 << FEATURE_FMA; 997 if ((ECX >> 19) & 1) 998 Features |= 1 << FEATURE_SSE4_1; 999 if ((ECX >> 20) & 1) 1000 Features |= 1 << FEATURE_SSE4_2; 1001 if ((ECX >> 23) & 1) 1002 Features |= 1 << FEATURE_POPCNT; 1003 if ((ECX >> 25) & 1) 1004 Features |= 1 << FEATURE_AES; 1005 1006 if ((ECX >> 22) & 1) 1007 Features2 |= 1 << (FEATURE_MOVBE - 32); 1008 1009 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1010 // indicates that the AVX registers will be saved and restored on context 1011 // switch, then we have full AVX support. 1012 const unsigned AVXBits = (1 << 27) | (1 << 28); 1013 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 1014 ((EAX & 0x6) == 0x6); 1015 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 1016 1017 if (HasAVX) 1018 Features |= 1 << FEATURE_AVX; 1019 1020 bool HasLeaf7 = 1021 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1022 1023 if (HasLeaf7 && ((EBX >> 3) & 1)) 1024 Features |= 1 << FEATURE_BMI; 1025 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 1026 Features |= 1 << FEATURE_AVX2; 1027 if (HasLeaf7 && ((EBX >> 9) & 1)) 1028 Features |= 1 << FEATURE_BMI2; 1029 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 1030 Features |= 1 << FEATURE_AVX512F; 1031 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 1032 Features |= 1 << FEATURE_AVX512DQ; 1033 if (HasLeaf7 && ((EBX >> 19) & 1)) 1034 Features2 |= 1 << (FEATURE_ADX - 32); 1035 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 1036 Features |= 1 << FEATURE_AVX512IFMA; 1037 if (HasLeaf7 && ((EBX >> 23) & 1)) 1038 Features2 |= 1 << (FEATURE_CLFLUSHOPT - 32); 1039 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 1040 Features |= 1 << FEATURE_AVX512PF; 1041 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 1042 Features |= 1 << FEATURE_AVX512ER; 1043 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 1044 Features |= 1 << FEATURE_AVX512CD; 1045 if (HasLeaf7 && ((EBX >> 29) & 1)) 1046 Features2 |= 1 << (FEATURE_SHA - 32); 1047 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 1048 Features |= 1 << FEATURE_AVX512BW; 1049 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 1050 Features |= 1 << FEATURE_AVX512VL; 1051 1052 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 1053 Features |= 1 << FEATURE_AVX512VBMI; 1054 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1055 Features |= 1 << FEATURE_AVX512VPOPCNTDQ; 1056 1057 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1058 Features |= 1 << FEATURE_AVX5124VNNIW; 1059 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1060 Features |= 1 << FEATURE_AVX5124FMAPS; 1061 1062 unsigned MaxExtLevel; 1063 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1064 1065 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1066 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1067 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1068 Features |= 1 << FEATURE_SSE4_A; 1069 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1070 Features |= 1 << FEATURE_XOP; 1071 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1072 Features |= 1 << FEATURE_FMA4; 1073 1074 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1075 Features2 |= 1 << (FEATURE_EM64T - 32); 1076 1077 *FeaturesOut = Features; 1078 *Features2Out = Features2; 1079 } 1080 1081 StringRef sys::getHostCPUName() { 1082 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1083 unsigned MaxLeaf, Vendor; 1084 1085 #if defined(__GNUC__) || defined(__clang__) 1086 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here 1087 // and simplify it to not invoke __cpuid (like cpu_model.c in 1088 // compiler-rt/lib/builtins/cpu_model.c? 1089 // Opting for the second option. 1090 if(!isCpuIdSupported()) 1091 return "generic"; 1092 #endif 1093 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) 1094 return "generic"; 1095 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1096 1097 unsigned Brand_id = EBX & 0xff; 1098 unsigned Family = 0, Model = 0; 1099 unsigned Features = 0, Features2 = 0; 1100 detectX86FamilyModel(EAX, &Family, &Model); 1101 getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2); 1102 1103 unsigned Type; 1104 unsigned Subtype; 1105 1106 if (Vendor == SIG_INTEL) { 1107 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, 1108 Features2, &Type, &Subtype); 1109 switch (Type) { 1110 case INTEL_i386: 1111 return "i386"; 1112 case INTEL_i486: 1113 return "i486"; 1114 case INTEL_PENTIUM: 1115 if (Subtype == INTEL_PENTIUM_MMX) 1116 return "pentium-mmx"; 1117 return "pentium"; 1118 case INTEL_PENTIUM_PRO: 1119 return "pentiumpro"; 1120 case INTEL_PENTIUM_II: 1121 return "pentium2"; 1122 case INTEL_PENTIUM_III: 1123 return "pentium3"; 1124 case INTEL_PENTIUM_IV: 1125 return "pentium4"; 1126 case INTEL_PENTIUM_M: 1127 return "pentium-m"; 1128 case INTEL_CORE_DUO: 1129 return "yonah"; 1130 case INTEL_CORE2: 1131 switch (Subtype) { 1132 case INTEL_CORE2_65: 1133 return "core2"; 1134 case INTEL_CORE2_45: 1135 return "penryn"; 1136 default: 1137 llvm_unreachable("Unexpected subtype!"); 1138 } 1139 case INTEL_COREI7: 1140 switch (Subtype) { 1141 case INTEL_COREI7_NEHALEM: 1142 return "nehalem"; 1143 case INTEL_COREI7_WESTMERE: 1144 return "westmere"; 1145 case INTEL_COREI7_SANDYBRIDGE: 1146 return "sandybridge"; 1147 case INTEL_COREI7_IVYBRIDGE: 1148 return "ivybridge"; 1149 case INTEL_COREI7_HASWELL: 1150 return "haswell"; 1151 case INTEL_COREI7_BROADWELL: 1152 return "broadwell"; 1153 case INTEL_COREI7_SKYLAKE: 1154 return "skylake"; 1155 case INTEL_COREI7_SKYLAKE_AVX512: 1156 return "skylake-avx512"; 1157 default: 1158 llvm_unreachable("Unexpected subtype!"); 1159 } 1160 case INTEL_BONNELL: 1161 return "bonnell"; 1162 case INTEL_SILVERMONT: 1163 return "silvermont"; 1164 case INTEL_GOLDMONT: 1165 return "goldmont"; 1166 case INTEL_KNL: 1167 return "knl"; 1168 case INTEL_X86_64: 1169 return "x86-64"; 1170 case INTEL_NOCONA: 1171 return "nocona"; 1172 case INTEL_PRESCOTT: 1173 return "prescott"; 1174 default: 1175 break; 1176 } 1177 } else if (Vendor == SIG_AMD) { 1178 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1179 switch (Type) { 1180 case AMD_i486: 1181 return "i486"; 1182 case AMDPENTIUM: 1183 switch (Subtype) { 1184 case AMDPENTIUM_K6: 1185 return "k6"; 1186 case AMDPENTIUM_K62: 1187 return "k6-2"; 1188 case AMDPENTIUM_K63: 1189 return "k6-3"; 1190 case AMDPENTIUM_GEODE: 1191 return "geode"; 1192 default: 1193 return "pentium"; 1194 } 1195 case AMDATHLON: 1196 switch (Subtype) { 1197 case AMDATHLON_CLASSIC: 1198 return "athlon"; 1199 case AMDATHLON_XP: 1200 return "athlon-xp"; 1201 case AMDATHLON_K8: 1202 return "k8"; 1203 case AMDATHLON_K8SSE3: 1204 return "k8-sse3"; 1205 default: 1206 llvm_unreachable("Unexpected subtype!"); 1207 } 1208 case AMDFAM10H: 1209 return "amdfam10"; 1210 case AMD_BTVER1: 1211 return "btver1"; 1212 case AMDFAM15H: 1213 switch (Subtype) { 1214 default: // There are gaps in the subtype detection. 1215 case AMDFAM15H_BDVER1: 1216 return "bdver1"; 1217 case AMDFAM15H_BDVER2: 1218 return "bdver2"; 1219 case AMDFAM15H_BDVER3: 1220 return "bdver3"; 1221 case AMDFAM15H_BDVER4: 1222 return "bdver4"; 1223 } 1224 case AMD_BTVER2: 1225 return "btver2"; 1226 case AMDFAM17H: 1227 return "znver1"; 1228 default: 1229 break; 1230 } 1231 } 1232 return "generic"; 1233 } 1234 1235 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1236 StringRef sys::getHostCPUName() { 1237 host_basic_info_data_t hostInfo; 1238 mach_msg_type_number_t infoCount; 1239 1240 infoCount = HOST_BASIC_INFO_COUNT; 1241 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo, 1242 &infoCount); 1243 1244 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1245 return "generic"; 1246 1247 switch (hostInfo.cpu_subtype) { 1248 case CPU_SUBTYPE_POWERPC_601: 1249 return "601"; 1250 case CPU_SUBTYPE_POWERPC_602: 1251 return "602"; 1252 case CPU_SUBTYPE_POWERPC_603: 1253 return "603"; 1254 case CPU_SUBTYPE_POWERPC_603e: 1255 return "603e"; 1256 case CPU_SUBTYPE_POWERPC_603ev: 1257 return "603ev"; 1258 case CPU_SUBTYPE_POWERPC_604: 1259 return "604"; 1260 case CPU_SUBTYPE_POWERPC_604e: 1261 return "604e"; 1262 case CPU_SUBTYPE_POWERPC_620: 1263 return "620"; 1264 case CPU_SUBTYPE_POWERPC_750: 1265 return "750"; 1266 case CPU_SUBTYPE_POWERPC_7400: 1267 return "7400"; 1268 case CPU_SUBTYPE_POWERPC_7450: 1269 return "7450"; 1270 case CPU_SUBTYPE_POWERPC_970: 1271 return "970"; 1272 default:; 1273 } 1274 1275 return "generic"; 1276 } 1277 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1278 StringRef sys::getHostCPUName() { 1279 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1280 const StringRef& Content = P ? P->getBuffer() : ""; 1281 return detail::getHostCPUNameForPowerPC(Content); 1282 } 1283 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1284 StringRef sys::getHostCPUName() { 1285 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1286 const StringRef& Content = P ? P->getBuffer() : ""; 1287 return detail::getHostCPUNameForARM(Content); 1288 } 1289 #elif defined(__linux__) && defined(__s390x__) 1290 StringRef sys::getHostCPUName() { 1291 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1292 const StringRef& Content = P ? P->getBuffer() : ""; 1293 return detail::getHostCPUNameForS390x(Content); 1294 } 1295 #else 1296 StringRef sys::getHostCPUName() { return "generic"; } 1297 #endif 1298 1299 #if defined(__linux__) && defined(__x86_64__) 1300 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1301 // using the number of unique physical/core id pairs. The following 1302 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1303 static int computeHostNumPhysicalCores() { 1304 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1305 // mmapped because it appears to have 0 size. 1306 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1307 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1308 if (std::error_code EC = Text.getError()) { 1309 llvm::errs() << "Can't read " 1310 << "/proc/cpuinfo: " << EC.message() << "\n"; 1311 return -1; 1312 } 1313 SmallVector<StringRef, 8> strs; 1314 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1315 /*KeepEmpty=*/false); 1316 int CurPhysicalId = -1; 1317 int CurCoreId = -1; 1318 SmallSet<std::pair<int, int>, 32> UniqueItems; 1319 for (auto &Line : strs) { 1320 Line = Line.trim(); 1321 if (!Line.startswith("physical id") && !Line.startswith("core id")) 1322 continue; 1323 std::pair<StringRef, StringRef> Data = Line.split(':'); 1324 auto Name = Data.first.trim(); 1325 auto Val = Data.second.trim(); 1326 if (Name == "physical id") { 1327 assert(CurPhysicalId == -1 && 1328 "Expected a core id before seeing another physical id"); 1329 Val.getAsInteger(10, CurPhysicalId); 1330 } 1331 if (Name == "core id") { 1332 assert(CurCoreId == -1 && 1333 "Expected a physical id before seeing another core id"); 1334 Val.getAsInteger(10, CurCoreId); 1335 } 1336 if (CurPhysicalId != -1 && CurCoreId != -1) { 1337 UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId)); 1338 CurPhysicalId = -1; 1339 CurCoreId = -1; 1340 } 1341 } 1342 return UniqueItems.size(); 1343 } 1344 #elif defined(__APPLE__) && defined(__x86_64__) 1345 #include <sys/param.h> 1346 #include <sys/sysctl.h> 1347 1348 // Gets the number of *physical cores* on the machine. 1349 static int computeHostNumPhysicalCores() { 1350 uint32_t count; 1351 size_t len = sizeof(count); 1352 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1353 if (count < 1) { 1354 int nm[2]; 1355 nm[0] = CTL_HW; 1356 nm[1] = HW_AVAILCPU; 1357 sysctl(nm, 2, &count, &len, NULL, 0); 1358 if (count < 1) 1359 return -1; 1360 } 1361 return count; 1362 } 1363 #else 1364 // On other systems, return -1 to indicate unknown. 1365 static int computeHostNumPhysicalCores() { return -1; } 1366 #endif 1367 1368 int sys::getHostNumPhysicalCores() { 1369 static int NumCores = computeHostNumPhysicalCores(); 1370 return NumCores; 1371 } 1372 1373 #if defined(__i386__) || defined(_M_IX86) || \ 1374 defined(__x86_64__) || defined(_M_X64) 1375 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1376 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1377 unsigned MaxLevel; 1378 union { 1379 unsigned u[3]; 1380 char c[12]; 1381 } text; 1382 1383 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1384 MaxLevel < 1) 1385 return false; 1386 1387 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1388 1389 Features["cmov"] = (EDX >> 15) & 1; 1390 Features["mmx"] = (EDX >> 23) & 1; 1391 Features["sse"] = (EDX >> 25) & 1; 1392 Features["sse2"] = (EDX >> 26) & 1; 1393 Features["sse3"] = (ECX >> 0) & 1; 1394 Features["ssse3"] = (ECX >> 9) & 1; 1395 Features["sse4.1"] = (ECX >> 19) & 1; 1396 Features["sse4.2"] = (ECX >> 20) & 1; 1397 1398 Features["pclmul"] = (ECX >> 1) & 1; 1399 Features["cx16"] = (ECX >> 13) & 1; 1400 Features["movbe"] = (ECX >> 22) & 1; 1401 Features["popcnt"] = (ECX >> 23) & 1; 1402 Features["aes"] = (ECX >> 25) & 1; 1403 Features["rdrnd"] = (ECX >> 30) & 1; 1404 1405 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1406 // indicates that the AVX registers will be saved and restored on context 1407 // switch, then we have full AVX support. 1408 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1409 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1410 Features["avx"] = HasAVXSave; 1411 Features["fma"] = HasAVXSave && (ECX >> 12) & 1; 1412 Features["f16c"] = HasAVXSave && (ECX >> 29) & 1; 1413 1414 // Only enable XSAVE if OS has enabled support for saving YMM state. 1415 Features["xsave"] = HasAVXSave && (ECX >> 26) & 1; 1416 1417 // AVX512 requires additional context to be saved by the OS. 1418 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1419 1420 unsigned MaxExtLevel; 1421 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1422 1423 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1424 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1425 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1426 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1427 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1428 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1429 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1430 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1431 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1432 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1433 1434 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1435 !getX86CpuIDAndInfoEx(0x80000008,0x0, &EAX, &EBX, &ECX, &EDX); 1436 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1437 1438 bool HasLeaf7 = 1439 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1440 1441 // AVX2 is only supported if we have the OS save support from AVX. 1442 Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1); 1443 1444 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1445 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1446 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1447 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1448 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1449 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1450 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1451 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1452 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1453 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1454 1455 // AVX512 is only supported if the OS supports the context save for it. 1456 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1457 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1458 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1459 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1460 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1461 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1462 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1463 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1464 1465 Features["prefetchwt1"] = HasLeaf7 && (ECX & 1); 1466 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1467 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1468 // Enable protection keys 1469 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1470 1471 bool HasLeafD = MaxLevel >= 0xd && 1472 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1473 1474 // Only enable XSAVE if OS has enabled support for saving YMM state. 1475 Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1); 1476 Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1); 1477 Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1); 1478 1479 return true; 1480 } 1481 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1482 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1483 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1484 if (!P) 1485 return false; 1486 1487 SmallVector<StringRef, 32> Lines; 1488 P->getBuffer().split(Lines, "\n"); 1489 1490 SmallVector<StringRef, 32> CPUFeatures; 1491 1492 // Look for the CPU features. 1493 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1494 if (Lines[I].startswith("Features")) { 1495 Lines[I].split(CPUFeatures, ' '); 1496 break; 1497 } 1498 1499 #if defined(__aarch64__) 1500 // Keep track of which crypto features we have seen 1501 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1502 uint32_t crypto = 0; 1503 #endif 1504 1505 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1506 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1507 #if defined(__aarch64__) 1508 .Case("asimd", "neon") 1509 .Case("fp", "fp-armv8") 1510 .Case("crc32", "crc") 1511 #else 1512 .Case("half", "fp16") 1513 .Case("neon", "neon") 1514 .Case("vfpv3", "vfp3") 1515 .Case("vfpv3d16", "d16") 1516 .Case("vfpv4", "vfp4") 1517 .Case("idiva", "hwdiv-arm") 1518 .Case("idivt", "hwdiv") 1519 #endif 1520 .Default(""); 1521 1522 #if defined(__aarch64__) 1523 // We need to check crypto separately since we need all of the crypto 1524 // extensions to enable the subtarget feature 1525 if (CPUFeatures[I] == "aes") 1526 crypto |= CAP_AES; 1527 else if (CPUFeatures[I] == "pmull") 1528 crypto |= CAP_PMULL; 1529 else if (CPUFeatures[I] == "sha1") 1530 crypto |= CAP_SHA1; 1531 else if (CPUFeatures[I] == "sha2") 1532 crypto |= CAP_SHA2; 1533 #endif 1534 1535 if (LLVMFeatureStr != "") 1536 Features[LLVMFeatureStr] = true; 1537 } 1538 1539 #if defined(__aarch64__) 1540 // If we have all crypto bits we can add the feature 1541 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1542 Features["crypto"] = true; 1543 #endif 1544 1545 return true; 1546 } 1547 #else 1548 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1549 #endif 1550 1551 std::string sys::getProcessTriple() { 1552 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1553 Triple PT(Triple::normalize(TargetTripleString)); 1554 1555 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1556 PT = PT.get64BitArchVariant(); 1557 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1558 PT = PT.get32BitArchVariant(); 1559 1560 return PT.str(); 1561 } 1562