1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the operating system Host concept. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Support/Host.h" 15 #include "llvm/ADT/SmallSet.h" 16 #include "llvm/ADT/SmallVector.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include <assert.h> 26 #include <string.h> 27 28 // Include the platform-specific parts of this class. 29 #ifdef LLVM_ON_UNIX 30 #include "Unix/Host.inc" 31 #endif 32 #ifdef LLVM_ON_WIN32 33 #include "Windows/Host.inc" 34 #endif 35 #ifdef _MSC_VER 36 #include <intrin.h> 37 #endif 38 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 39 #include <mach/host_info.h> 40 #include <mach/mach.h> 41 #include <mach/mach_host.h> 42 #include <mach/machine.h> 43 #endif 44 45 #define DEBUG_TYPE "host-detection" 46 47 //===----------------------------------------------------------------------===// 48 // 49 // Implementations of the CPU detection routines 50 // 51 //===----------------------------------------------------------------------===// 52 53 using namespace llvm; 54 55 static std::unique_ptr<llvm::MemoryBuffer> 56 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 57 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 58 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 59 if (std::error_code EC = Text.getError()) { 60 llvm::errs() << "Can't read " 61 << "/proc/cpuinfo: " << EC.message() << "\n"; 62 return nullptr; 63 } 64 return std::move(*Text); 65 } 66 67 StringRef sys::detail::getHostCPUNameForPowerPC( 68 const StringRef &ProcCpuinfoContent) { 69 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 70 // and so we must use an operating-system interface to determine the current 71 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 72 const char *generic = "generic"; 73 74 // The cpu line is second (after the 'processor: 0' line), so if this 75 // buffer is too small then something has changed (or is wrong). 76 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 77 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 78 79 StringRef::const_iterator CIP = CPUInfoStart; 80 81 StringRef::const_iterator CPUStart = 0; 82 size_t CPULen = 0; 83 84 // We need to find the first line which starts with cpu, spaces, and a colon. 85 // After the colon, there may be some additional spaces and then the cpu type. 86 while (CIP < CPUInfoEnd && CPUStart == 0) { 87 if (CIP < CPUInfoEnd && *CIP == '\n') 88 ++CIP; 89 90 if (CIP < CPUInfoEnd && *CIP == 'c') { 91 ++CIP; 92 if (CIP < CPUInfoEnd && *CIP == 'p') { 93 ++CIP; 94 if (CIP < CPUInfoEnd && *CIP == 'u') { 95 ++CIP; 96 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 97 ++CIP; 98 99 if (CIP < CPUInfoEnd && *CIP == ':') { 100 ++CIP; 101 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 102 ++CIP; 103 104 if (CIP < CPUInfoEnd) { 105 CPUStart = CIP; 106 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 107 *CIP != ',' && *CIP != '\n')) 108 ++CIP; 109 CPULen = CIP - CPUStart; 110 } 111 } 112 } 113 } 114 } 115 116 if (CPUStart == 0) 117 while (CIP < CPUInfoEnd && *CIP != '\n') 118 ++CIP; 119 } 120 121 if (CPUStart == 0) 122 return generic; 123 124 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 125 .Case("604e", "604e") 126 .Case("604", "604") 127 .Case("7400", "7400") 128 .Case("7410", "7400") 129 .Case("7447", "7400") 130 .Case("7455", "7450") 131 .Case("G4", "g4") 132 .Case("POWER4", "970") 133 .Case("PPC970FX", "970") 134 .Case("PPC970MP", "970") 135 .Case("G5", "g5") 136 .Case("POWER5", "g5") 137 .Case("A2", "a2") 138 .Case("POWER6", "pwr6") 139 .Case("POWER7", "pwr7") 140 .Case("POWER8", "pwr8") 141 .Case("POWER8E", "pwr8") 142 .Case("POWER8NVL", "pwr8") 143 .Case("POWER9", "pwr9") 144 .Default(generic); 145 } 146 147 StringRef sys::detail::getHostCPUNameForARM( 148 const StringRef &ProcCpuinfoContent) { 149 // The cpuid register on arm is not accessible from user space. On Linux, 150 // it is exposed through the /proc/cpuinfo file. 151 152 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 153 // in all cases. 154 SmallVector<StringRef, 32> Lines; 155 ProcCpuinfoContent.split(Lines, "\n"); 156 157 // Look for the CPU implementer line. 158 StringRef Implementer; 159 StringRef Hardware; 160 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 161 if (Lines[I].startswith("CPU implementer")) 162 Implementer = Lines[I].substr(15).ltrim("\t :"); 163 if (Lines[I].startswith("Hardware")) 164 Hardware = Lines[I].substr(8).ltrim("\t :"); 165 } 166 167 if (Implementer == "0x41") { // ARM Ltd. 168 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 169 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 170 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 171 return "cortex-a53"; 172 173 174 // Look for the CPU part line. 175 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 176 if (Lines[I].startswith("CPU part")) 177 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 178 // values correspond to the "Part number" in the CP15/c0 register. The 179 // contents are specified in the various processor manuals. 180 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 181 .Case("0x926", "arm926ej-s") 182 .Case("0xb02", "mpcore") 183 .Case("0xb36", "arm1136j-s") 184 .Case("0xb56", "arm1156t2-s") 185 .Case("0xb76", "arm1176jz-s") 186 .Case("0xc08", "cortex-a8") 187 .Case("0xc09", "cortex-a9") 188 .Case("0xc0f", "cortex-a15") 189 .Case("0xc20", "cortex-m0") 190 .Case("0xc23", "cortex-m3") 191 .Case("0xc24", "cortex-m4") 192 .Case("0xd03", "cortex-a53") 193 .Case("0xd07", "cortex-a57") 194 .Case("0xd08", "cortex-a72") 195 .Case("0xd09", "cortex-a73") 196 .Default("generic"); 197 } 198 199 if (Implementer == "0x50") // Applied Micro Circuits Corporation (APM). 200 // Look for the CPU part line. 201 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 202 if (Lines[I].startswith("CPU part")) 203 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 204 // values correspond to the "Part number" in the CP15/c0 register. The 205 // contents are specified in the various processor manuals. 206 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 207 .Case("0x000", "xgene1") 208 .Default("generic"); 209 210 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 211 // Look for the CPU part line. 212 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 213 if (Lines[I].startswith("CPU part")) 214 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 215 // values correspond to the "Part number" in the CP15/c0 register. The 216 // contents are specified in the various processor manuals. 217 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 218 .Case("0x06f", "krait") // APQ8064 219 .Case("0x201", "kryo") 220 .Case("0x205", "kryo") 221 .Default("generic"); 222 223 return "generic"; 224 } 225 226 StringRef sys::detail::getHostCPUNameForS390x( 227 const StringRef &ProcCpuinfoContent) { 228 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 229 230 // The "processor 0:" line comes after a fair amount of other information, 231 // including a cache breakdown, but this should be plenty. 232 SmallVector<StringRef, 32> Lines; 233 ProcCpuinfoContent.split(Lines, "\n"); 234 235 // Look for the CPU features. 236 SmallVector<StringRef, 32> CPUFeatures; 237 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 238 if (Lines[I].startswith("features")) { 239 size_t Pos = Lines[I].find(":"); 240 if (Pos != StringRef::npos) { 241 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 242 break; 243 } 244 } 245 246 // We need to check for the presence of vector support independently of 247 // the machine type, since we may only use the vector register set when 248 // supported by the kernel (and hypervisor). 249 bool HaveVectorSupport = false; 250 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 251 if (CPUFeatures[I] == "vx") 252 HaveVectorSupport = true; 253 } 254 255 // Now check the processor machine type. 256 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 257 if (Lines[I].startswith("processor ")) { 258 size_t Pos = Lines[I].find("machine = "); 259 if (Pos != StringRef::npos) { 260 Pos += sizeof("machine = ") - 1; 261 unsigned int Id; 262 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 263 if (Id >= 2964 && HaveVectorSupport) 264 return "z13"; 265 if (Id >= 2827) 266 return "zEC12"; 267 if (Id >= 2817) 268 return "z196"; 269 } 270 } 271 break; 272 } 273 } 274 275 return "generic"; 276 } 277 278 #if defined(__i386__) || defined(_M_IX86) || \ 279 defined(__x86_64__) || defined(_M_X64) 280 281 enum VendorSignatures { 282 SIG_INTEL = 0x756e6547 /* Genu */, 283 SIG_AMD = 0x68747541 /* Auth */ 284 }; 285 286 enum ProcessorVendors { 287 VENDOR_INTEL = 1, 288 VENDOR_AMD, 289 VENDOR_OTHER, 290 VENDOR_MAX 291 }; 292 293 enum ProcessorTypes { 294 INTEL_ATOM = 1, 295 INTEL_CORE2, 296 INTEL_COREI7, 297 AMDFAM10H, 298 AMDFAM15H, 299 INTEL_i386, 300 INTEL_i486, 301 INTEL_PENTIUM, 302 INTEL_PENTIUM_PRO, 303 INTEL_PENTIUM_II, 304 INTEL_PENTIUM_III, 305 INTEL_PENTIUM_IV, 306 INTEL_PENTIUM_M, 307 INTEL_CORE_DUO, 308 INTEL_XEONPHI, 309 INTEL_X86_64, 310 INTEL_NOCONA, 311 INTEL_PRESCOTT, 312 AMD_i486, 313 AMDPENTIUM, 314 AMDATHLON, 315 AMDFAM14H, 316 AMDFAM16H, 317 AMDFAM17H, 318 CPU_TYPE_MAX 319 }; 320 321 enum ProcessorSubtypes { 322 INTEL_COREI7_NEHALEM = 1, 323 INTEL_COREI7_WESTMERE, 324 INTEL_COREI7_SANDYBRIDGE, 325 AMDFAM10H_BARCELONA, 326 AMDFAM10H_SHANGHAI, 327 AMDFAM10H_ISTANBUL, 328 AMDFAM15H_BDVER1, 329 AMDFAM15H_BDVER2, 330 INTEL_PENTIUM_MMX, 331 INTEL_CORE2_65, 332 INTEL_CORE2_45, 333 INTEL_COREI7_IVYBRIDGE, 334 INTEL_COREI7_HASWELL, 335 INTEL_COREI7_BROADWELL, 336 INTEL_COREI7_SKYLAKE, 337 INTEL_COREI7_SKYLAKE_AVX512, 338 INTEL_ATOM_BONNELL, 339 INTEL_ATOM_SILVERMONT, 340 INTEL_KNIGHTS_LANDING, 341 AMDPENTIUM_K6, 342 AMDPENTIUM_K62, 343 AMDPENTIUM_K63, 344 AMDPENTIUM_GEODE, 345 AMDATHLON_TBIRD, 346 AMDATHLON_MP, 347 AMDATHLON_XP, 348 AMDATHLON_K8SSE3, 349 AMDATHLON_OPTERON, 350 AMDATHLON_FX, 351 AMDATHLON_64, 352 AMD_BTVER1, 353 AMD_BTVER2, 354 AMDFAM15H_BDVER3, 355 AMDFAM15H_BDVER4, 356 AMDFAM17H_ZNVER1, 357 CPU_SUBTYPE_MAX 358 }; 359 360 enum ProcessorFeatures { 361 FEATURE_CMOV = 0, 362 FEATURE_MMX, 363 FEATURE_POPCNT, 364 FEATURE_SSE, 365 FEATURE_SSE2, 366 FEATURE_SSE3, 367 FEATURE_SSSE3, 368 FEATURE_SSE4_1, 369 FEATURE_SSE4_2, 370 FEATURE_AVX, 371 FEATURE_AVX2, 372 FEATURE_AVX512, 373 FEATURE_AVX512SAVE, 374 FEATURE_MOVBE, 375 FEATURE_ADX, 376 FEATURE_EM64T 377 }; 378 379 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 380 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 381 // support. Consequently, for i386, the presence of CPUID is checked first 382 // via the corresponding eflags bit. 383 // Removal of cpuid.h header motivated by PR30384 384 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 385 // or test-suite, but are used in external projects e.g. libstdcxx 386 static bool isCpuIdSupported() { 387 #if defined(__GNUC__) || defined(__clang__) 388 #if defined(__i386__) 389 int __cpuid_supported; 390 __asm__(" pushfl\n" 391 " popl %%eax\n" 392 " movl %%eax,%%ecx\n" 393 " xorl $0x00200000,%%eax\n" 394 " pushl %%eax\n" 395 " popfl\n" 396 " pushfl\n" 397 " popl %%eax\n" 398 " movl $0,%0\n" 399 " cmpl %%eax,%%ecx\n" 400 " je 1f\n" 401 " movl $1,%0\n" 402 "1:" 403 : "=r"(__cpuid_supported) 404 : 405 : "eax", "ecx"); 406 if (!__cpuid_supported) 407 return false; 408 #endif 409 return true; 410 #endif 411 return true; 412 } 413 414 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 415 /// the specified arguments. If we can't run cpuid on the host, return true. 416 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 417 unsigned *rECX, unsigned *rEDX) { 418 #if defined(__GNUC__) || defined(__clang__) || defined(_MSC_VER) 419 #if defined(__GNUC__) || defined(__clang__) 420 #if defined(__x86_64__) 421 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 422 // FIXME: should we save this for Clang? 423 __asm__("movq\t%%rbx, %%rsi\n\t" 424 "cpuid\n\t" 425 "xchgq\t%%rbx, %%rsi\n\t" 426 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 427 : "a"(value)); 428 #elif defined(__i386__) 429 __asm__("movl\t%%ebx, %%esi\n\t" 430 "cpuid\n\t" 431 "xchgl\t%%ebx, %%esi\n\t" 432 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 433 : "a"(value)); 434 #else 435 assert(0 && "This method is defined only for x86."); 436 #endif 437 #elif defined(_MSC_VER) 438 // The MSVC intrinsic is portable across x86 and x64. 439 int registers[4]; 440 __cpuid(registers, value); 441 *rEAX = registers[0]; 442 *rEBX = registers[1]; 443 *rECX = registers[2]; 444 *rEDX = registers[3]; 445 #endif 446 return false; 447 #else 448 return true; 449 #endif 450 } 451 452 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 453 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 454 /// return true. 455 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 456 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 457 unsigned *rEDX) { 458 #if defined(__GNUC__) || defined(__clang__) || defined(_MSC_VER) 459 #if defined(__x86_64__) || defined(_M_X64) 460 #if defined(__GNUC__) || defined(__clang__) 461 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. 462 // FIXME: should we save this for Clang? 463 __asm__("movq\t%%rbx, %%rsi\n\t" 464 "cpuid\n\t" 465 "xchgq\t%%rbx, %%rsi\n\t" 466 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 467 : "a"(value), "c"(subleaf)); 468 #elif defined(_MSC_VER) 469 int registers[4]; 470 __cpuidex(registers, value, subleaf); 471 *rEAX = registers[0]; 472 *rEBX = registers[1]; 473 *rECX = registers[2]; 474 *rEDX = registers[3]; 475 #endif 476 #elif defined(__i386__) || defined(_M_IX86) 477 #if defined(__GNUC__) || defined(__clang__) 478 __asm__("movl\t%%ebx, %%esi\n\t" 479 "cpuid\n\t" 480 "xchgl\t%%ebx, %%esi\n\t" 481 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 482 : "a"(value), "c"(subleaf)); 483 #elif defined(_MSC_VER) 484 __asm { 485 mov eax,value 486 mov ecx,subleaf 487 cpuid 488 mov esi,rEAX 489 mov dword ptr [esi],eax 490 mov esi,rEBX 491 mov dword ptr [esi],ebx 492 mov esi,rECX 493 mov dword ptr [esi],ecx 494 mov esi,rEDX 495 mov dword ptr [esi],edx 496 } 497 #endif 498 #else 499 assert(0 && "This method is defined only for x86."); 500 #endif 501 return false; 502 #else 503 return true; 504 #endif 505 } 506 507 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 508 #if defined(__GNUC__) || defined(__clang__) 509 // Check xgetbv; this uses a .byte sequence instead of the instruction 510 // directly because older assemblers do not include support for xgetbv and 511 // there is no easy way to conditionally compile based on the assembler used. 512 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 513 return false; 514 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 515 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 516 *rEAX = Result; 517 *rEDX = Result >> 32; 518 return false; 519 #else 520 return true; 521 #endif 522 } 523 524 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 525 unsigned *Model) { 526 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 527 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 528 if (*Family == 6 || *Family == 0xf) { 529 if (*Family == 0xf) 530 // Examine extended family ID if family ID is F. 531 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 532 // Examine extended model ID if family ID is 6 or F. 533 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 534 } 535 } 536 537 static void 538 getIntelProcessorTypeAndSubtype(unsigned int Family, unsigned int Model, 539 unsigned int Brand_id, unsigned int Features, 540 unsigned *Type, unsigned *Subtype) { 541 if (Brand_id != 0) 542 return; 543 switch (Family) { 544 case 3: 545 *Type = INTEL_i386; 546 break; 547 case 4: 548 switch (Model) { 549 case 0: // Intel486 DX processors 550 case 1: // Intel486 DX processors 551 case 2: // Intel486 SX processors 552 case 3: // Intel487 processors, IntelDX2 OverDrive processors, 553 // IntelDX2 processors 554 case 4: // Intel486 SL processor 555 case 5: // IntelSX2 processors 556 case 7: // Write-Back Enhanced IntelDX2 processors 557 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors 558 default: 559 *Type = INTEL_i486; 560 break; 561 } 562 break; 563 case 5: 564 switch (Model) { 565 case 1: // Pentium OverDrive processor for Pentium processor (60, 66), 566 // Pentium processors (60, 66) 567 case 2: // Pentium OverDrive processor for Pentium processor (75, 90, 568 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133, 569 // 150, 166, 200) 570 case 3: // Pentium OverDrive processors for Intel486 processor-based 571 // systems 572 *Type = INTEL_PENTIUM; 573 break; 574 case 4: // Pentium OverDrive processor with MMX technology for Pentium 575 // processor (75, 90, 100, 120, 133), Pentium processor with 576 // MMX technology (166, 200) 577 *Type = INTEL_PENTIUM; 578 *Subtype = INTEL_PENTIUM_MMX; 579 break; 580 default: 581 *Type = INTEL_PENTIUM; 582 break; 583 } 584 break; 585 case 6: 586 switch (Model) { 587 case 0x01: // Pentium Pro processor 588 *Type = INTEL_PENTIUM_PRO; 589 break; 590 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 591 // model 03 592 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 593 // model 05, and Intel Celeron processor, model 05 594 case 0x06: // Celeron processor, model 06 595 *Type = INTEL_PENTIUM_II; 596 break; 597 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 598 // processor, model 07 599 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 600 // model 08, and Celeron processor, model 08 601 case 0x0a: // Pentium III Xeon processor, model 0Ah 602 case 0x0b: // Pentium III processor, model 0Bh 603 *Type = INTEL_PENTIUM_III; 604 break; 605 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 606 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 607 // 0Dh. All processors are manufactured using the 90 nm process. 608 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 609 // Integrated Processor with Intel QuickAssist Technology 610 *Type = INTEL_PENTIUM_M; 611 break; 612 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 613 // 0Eh. All processors are manufactured using the 65 nm process. 614 *Type = INTEL_CORE_DUO; 615 break; // yonah 616 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 617 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 618 // mobile processor, Intel Core 2 Extreme processor, Intel 619 // Pentium Dual-Core processor, Intel Xeon processor, model 620 // 0Fh. All processors are manufactured using the 65 nm process. 621 case 0x16: // Intel Celeron processor model 16h. All processors are 622 // manufactured using the 65 nm process 623 *Type = INTEL_CORE2; // "core2" 624 *Subtype = INTEL_CORE2_65; 625 break; 626 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 627 // 17h. All processors are manufactured using the 45 nm process. 628 // 629 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 630 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 631 // the 45 nm process. 632 *Type = INTEL_CORE2; // "penryn" 633 *Subtype = INTEL_CORE2_45; 634 break; 635 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 636 // processors are manufactured using the 45 nm process. 637 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 638 // As found in a Summer 2010 model iMac. 639 case 0x1f: 640 case 0x2e: // Nehalem EX 641 *Type = INTEL_COREI7; // "nehalem" 642 *Subtype = INTEL_COREI7_NEHALEM; 643 break; 644 case 0x25: // Intel Core i7, laptop version. 645 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 646 // processors are manufactured using the 32 nm process. 647 case 0x2f: // Westmere EX 648 *Type = INTEL_COREI7; // "westmere" 649 *Subtype = INTEL_COREI7_WESTMERE; 650 break; 651 case 0x2a: // Intel Core i7 processor. All processors are manufactured 652 // using the 32 nm process. 653 case 0x2d: 654 *Type = INTEL_COREI7; //"sandybridge" 655 *Subtype = INTEL_COREI7_SANDYBRIDGE; 656 break; 657 case 0x3a: 658 case 0x3e: // Ivy Bridge EP 659 *Type = INTEL_COREI7; // "ivybridge" 660 *Subtype = INTEL_COREI7_IVYBRIDGE; 661 break; 662 663 // Haswell: 664 case 0x3c: 665 case 0x3f: 666 case 0x45: 667 case 0x46: 668 *Type = INTEL_COREI7; // "haswell" 669 *Subtype = INTEL_COREI7_HASWELL; 670 break; 671 672 // Broadwell: 673 case 0x3d: 674 case 0x47: 675 case 0x4f: 676 case 0x56: 677 *Type = INTEL_COREI7; // "broadwell" 678 *Subtype = INTEL_COREI7_BROADWELL; 679 break; 680 681 // Skylake: 682 case 0x4e: // Skylake mobile 683 case 0x5e: // Skylake desktop 684 case 0x8e: // Kaby Lake mobile 685 case 0x9e: // Kaby Lake desktop 686 *Type = INTEL_COREI7; // "skylake" 687 *Subtype = INTEL_COREI7_SKYLAKE; 688 break; 689 690 // Skylake Xeon: 691 case 0x55: 692 *Type = INTEL_COREI7; 693 // Check that we really have AVX512 694 if (Features & (1 << FEATURE_AVX512)) { 695 *Subtype = INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 696 } else { 697 *Subtype = INTEL_COREI7_SKYLAKE; // "skylake" 698 } 699 break; 700 701 case 0x1c: // Most 45 nm Intel Atom processors 702 case 0x26: // 45 nm Atom Lincroft 703 case 0x27: // 32 nm Atom Medfield 704 case 0x35: // 32 nm Atom Midview 705 case 0x36: // 32 nm Atom Midview 706 *Type = INTEL_ATOM; 707 *Subtype = INTEL_ATOM_BONNELL; 708 break; // "bonnell" 709 710 // Atom Silvermont codes from the Intel software optimization guide. 711 case 0x37: 712 case 0x4a: 713 case 0x4d: 714 case 0x5a: 715 case 0x5d: 716 case 0x4c: // really airmont 717 *Type = INTEL_ATOM; 718 *Subtype = INTEL_ATOM_SILVERMONT; 719 break; // "silvermont" 720 721 case 0x57: 722 *Type = INTEL_XEONPHI; // knl 723 *Subtype = INTEL_KNIGHTS_LANDING; 724 break; 725 726 default: // Unknown family 6 CPU, try to guess. 727 if (Features & (1 << FEATURE_AVX512)) { 728 *Type = INTEL_XEONPHI; // knl 729 *Subtype = INTEL_KNIGHTS_LANDING; 730 break; 731 } 732 if (Features & (1 << FEATURE_ADX)) { 733 *Type = INTEL_COREI7; 734 *Subtype = INTEL_COREI7_BROADWELL; 735 break; 736 } 737 if (Features & (1 << FEATURE_AVX2)) { 738 *Type = INTEL_COREI7; 739 *Subtype = INTEL_COREI7_HASWELL; 740 break; 741 } 742 if (Features & (1 << FEATURE_AVX)) { 743 *Type = INTEL_COREI7; 744 *Subtype = INTEL_COREI7_SANDYBRIDGE; 745 break; 746 } 747 if (Features & (1 << FEATURE_SSE4_2)) { 748 if (Features & (1 << FEATURE_MOVBE)) { 749 *Type = INTEL_ATOM; 750 *Subtype = INTEL_ATOM_SILVERMONT; 751 } else { 752 *Type = INTEL_COREI7; 753 *Subtype = INTEL_COREI7_NEHALEM; 754 } 755 break; 756 } 757 if (Features & (1 << FEATURE_SSE4_1)) { 758 *Type = INTEL_CORE2; // "penryn" 759 *Subtype = INTEL_CORE2_45; 760 break; 761 } 762 if (Features & (1 << FEATURE_SSSE3)) { 763 if (Features & (1 << FEATURE_MOVBE)) { 764 *Type = INTEL_ATOM; 765 *Subtype = INTEL_ATOM_BONNELL; // "bonnell" 766 } else { 767 *Type = INTEL_CORE2; // "core2" 768 *Subtype = INTEL_CORE2_65; 769 } 770 break; 771 } 772 if (Features & (1 << FEATURE_EM64T)) { 773 *Type = INTEL_X86_64; 774 break; // x86-64 775 } 776 if (Features & (1 << FEATURE_SSE2)) { 777 *Type = INTEL_PENTIUM_M; 778 break; 779 } 780 if (Features & (1 << FEATURE_SSE)) { 781 *Type = INTEL_PENTIUM_III; 782 break; 783 } 784 if (Features & (1 << FEATURE_MMX)) { 785 *Type = INTEL_PENTIUM_II; 786 break; 787 } 788 *Type = INTEL_PENTIUM_PRO; 789 break; 790 } 791 break; 792 case 15: { 793 switch (Model) { 794 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are 795 // model 00h and manufactured using the 0.18 micron process. 796 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon 797 // processor MP, and Intel Celeron processor. All processors are 798 // model 01h and manufactured using the 0.18 micron process. 799 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M, 800 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron 801 // processor, and Mobile Intel Celeron processor. All processors 802 // are model 02h and manufactured using the 0.13 micron process. 803 *Type = 804 ((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV); 805 break; 806 807 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D 808 // processor. All processors are model 03h and manufactured using 809 // the 90 nm process. 810 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition, 811 // Pentium D processor, Intel Xeon processor, Intel Xeon 812 // processor MP, Intel Celeron D processor. All processors are 813 // model 04h and manufactured using the 90 nm process. 814 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor 815 // Extreme Edition, Intel Xeon processor, Intel Xeon processor 816 // MP, Intel Celeron D processor. All processors are model 06h 817 // and manufactured using the 65 nm process. 818 *Type = 819 ((Features & (1 << FEATURE_EM64T)) ? INTEL_NOCONA : INTEL_PRESCOTT); 820 break; 821 822 default: 823 *Type = 824 ((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV); 825 break; 826 } 827 break; 828 } 829 default: 830 break; /*"generic"*/ 831 } 832 } 833 834 static void getAMDProcessorTypeAndSubtype(unsigned int Family, 835 unsigned int Model, 836 unsigned int Features, 837 unsigned *Type, 838 unsigned *Subtype) { 839 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 840 // appears to be no way to generate the wide variety of AMD-specific targets 841 // from the information returned from CPUID. 842 switch (Family) { 843 case 4: 844 *Type = AMD_i486; 845 break; 846 case 5: 847 *Type = AMDPENTIUM; 848 switch (Model) { 849 case 6: 850 case 7: 851 *Subtype = AMDPENTIUM_K6; 852 break; // "k6" 853 case 8: 854 *Subtype = AMDPENTIUM_K62; 855 break; // "k6-2" 856 case 9: 857 case 13: 858 *Subtype = AMDPENTIUM_K63; 859 break; // "k6-3" 860 case 10: 861 *Subtype = AMDPENTIUM_GEODE; 862 break; // "geode" 863 } 864 break; 865 case 6: 866 *Type = AMDATHLON; 867 switch (Model) { 868 case 4: 869 *Subtype = AMDATHLON_TBIRD; 870 break; // "athlon-tbird" 871 case 6: 872 case 7: 873 case 8: 874 *Subtype = AMDATHLON_MP; 875 break; // "athlon-mp" 876 case 10: 877 *Subtype = AMDATHLON_XP; 878 break; // "athlon-xp" 879 } 880 break; 881 case 15: 882 *Type = AMDATHLON; 883 if (Features & (1 << FEATURE_SSE3)) { 884 *Subtype = AMDATHLON_K8SSE3; 885 break; // "k8-sse3" 886 } 887 switch (Model) { 888 case 1: 889 *Subtype = AMDATHLON_OPTERON; 890 break; // "opteron" 891 case 5: 892 *Subtype = AMDATHLON_FX; 893 break; // "athlon-fx"; also opteron 894 default: 895 *Subtype = AMDATHLON_64; 896 break; // "athlon64" 897 } 898 break; 899 case 16: 900 *Type = AMDFAM10H; // "amdfam10" 901 switch (Model) { 902 case 2: 903 *Subtype = AMDFAM10H_BARCELONA; 904 break; 905 case 4: 906 *Subtype = AMDFAM10H_SHANGHAI; 907 break; 908 case 8: 909 *Subtype = AMDFAM10H_ISTANBUL; 910 break; 911 } 912 break; 913 case 20: 914 *Type = AMDFAM14H; 915 *Subtype = AMD_BTVER1; 916 break; // "btver1"; 917 case 21: 918 *Type = AMDFAM15H; 919 if (!(Features & 920 (1 << FEATURE_AVX))) { // If no AVX support, provide a sane fallback. 921 *Subtype = AMD_BTVER1; 922 break; // "btver1" 923 } 924 if (Model >= 0x50 && Model <= 0x6f) { 925 *Subtype = AMDFAM15H_BDVER4; 926 break; // "bdver4"; 50h-6Fh: Excavator 927 } 928 if (Model >= 0x30 && Model <= 0x3f) { 929 *Subtype = AMDFAM15H_BDVER3; 930 break; // "bdver3"; 30h-3Fh: Steamroller 931 } 932 if (Model >= 0x10 && Model <= 0x1f) { 933 *Subtype = AMDFAM15H_BDVER2; 934 break; // "bdver2"; 10h-1Fh: Piledriver 935 } 936 if (Model <= 0x0f) { 937 *Subtype = AMDFAM15H_BDVER1; 938 break; // "bdver1"; 00h-0Fh: Bulldozer 939 } 940 break; 941 case 22: 942 *Type = AMDFAM16H; 943 if (!(Features & 944 (1 << FEATURE_AVX))) { // If no AVX support provide a sane fallback. 945 *Subtype = AMD_BTVER1; 946 break; // "btver1"; 947 } 948 *Subtype = AMD_BTVER2; 949 break; // "btver2" 950 case 23: 951 *Type = AMDFAM17H; 952 if (Features & (1 << FEATURE_ADX)) { 953 *Subtype = AMDFAM17H_ZNVER1; 954 break; // "znver1" 955 } 956 *Subtype = AMD_BTVER1; 957 break; 958 default: 959 break; // "generic" 960 } 961 } 962 963 static unsigned getAvailableFeatures(unsigned int ECX, unsigned int EDX, 964 unsigned MaxLeaf) { 965 unsigned Features = 0; 966 unsigned int EAX, EBX; 967 Features |= (((EDX >> 23) & 1) << FEATURE_MMX); 968 Features |= (((EDX >> 25) & 1) << FEATURE_SSE); 969 Features |= (((EDX >> 26) & 1) << FEATURE_SSE2); 970 Features |= (((ECX >> 0) & 1) << FEATURE_SSE3); 971 Features |= (((ECX >> 9) & 1) << FEATURE_SSSE3); 972 Features |= (((ECX >> 19) & 1) << FEATURE_SSE4_1); 973 Features |= (((ECX >> 20) & 1) << FEATURE_SSE4_2); 974 Features |= (((ECX >> 22) & 1) << FEATURE_MOVBE); 975 976 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 977 // indicates that the AVX registers will be saved and restored on context 978 // switch, then we have full AVX support. 979 const unsigned AVXBits = (1 << 27) | (1 << 28); 980 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 981 ((EAX & 0x6) == 0x6); 982 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 983 bool HasLeaf7 = 984 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 985 bool HasADX = HasLeaf7 && ((EBX >> 19) & 1); 986 bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20); 987 bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1); 988 Features |= (HasAVX << FEATURE_AVX); 989 Features |= (HasAVX2 << FEATURE_AVX2); 990 Features |= (HasAVX512 << FEATURE_AVX512); 991 Features |= (HasAVX512Save << FEATURE_AVX512SAVE); 992 Features |= (HasADX << FEATURE_ADX); 993 994 getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 995 Features |= (((EDX >> 29) & 0x1) << FEATURE_EM64T); 996 return Features; 997 } 998 999 StringRef sys::getHostCPUName() { 1000 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1001 unsigned MaxLeaf, Vendor; 1002 1003 #if defined(__GNUC__) || defined(__clang__) 1004 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here 1005 // and simplify it to not invoke __cpuid (like cpu_model.c in 1006 // compiler-rt/lib/builtins/cpu_model.c? 1007 // Opting for the second option. 1008 if(!isCpuIdSupported()) 1009 return "generic"; 1010 #endif 1011 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX)) 1012 return "generic"; 1013 if (getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX)) 1014 return "generic"; 1015 1016 unsigned Brand_id = EBX & 0xff; 1017 unsigned Family = 0, Model = 0; 1018 unsigned Features = 0; 1019 detectX86FamilyModel(EAX, &Family, &Model); 1020 Features = getAvailableFeatures(ECX, EDX, MaxLeaf); 1021 1022 unsigned Type; 1023 unsigned Subtype; 1024 1025 if (Vendor == SIG_INTEL) { 1026 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, &Type, 1027 &Subtype); 1028 switch (Type) { 1029 case INTEL_i386: 1030 return "i386"; 1031 case INTEL_i486: 1032 return "i486"; 1033 case INTEL_PENTIUM: 1034 if (Subtype == INTEL_PENTIUM_MMX) 1035 return "pentium-mmx"; 1036 return "pentium"; 1037 case INTEL_PENTIUM_PRO: 1038 return "pentiumpro"; 1039 case INTEL_PENTIUM_II: 1040 return "pentium2"; 1041 case INTEL_PENTIUM_III: 1042 return "pentium3"; 1043 case INTEL_PENTIUM_IV: 1044 return "pentium4"; 1045 case INTEL_PENTIUM_M: 1046 return "pentium-m"; 1047 case INTEL_CORE_DUO: 1048 return "yonah"; 1049 case INTEL_CORE2: 1050 switch (Subtype) { 1051 case INTEL_CORE2_65: 1052 return "core2"; 1053 case INTEL_CORE2_45: 1054 return "penryn"; 1055 default: 1056 return "core2"; 1057 } 1058 case INTEL_COREI7: 1059 switch (Subtype) { 1060 case INTEL_COREI7_NEHALEM: 1061 return "nehalem"; 1062 case INTEL_COREI7_WESTMERE: 1063 return "westmere"; 1064 case INTEL_COREI7_SANDYBRIDGE: 1065 return "sandybridge"; 1066 case INTEL_COREI7_IVYBRIDGE: 1067 return "ivybridge"; 1068 case INTEL_COREI7_HASWELL: 1069 return "haswell"; 1070 case INTEL_COREI7_BROADWELL: 1071 return "broadwell"; 1072 case INTEL_COREI7_SKYLAKE: 1073 return "skylake"; 1074 case INTEL_COREI7_SKYLAKE_AVX512: 1075 return "skylake-avx512"; 1076 default: 1077 return "corei7"; 1078 } 1079 case INTEL_ATOM: 1080 switch (Subtype) { 1081 case INTEL_ATOM_BONNELL: 1082 return "bonnell"; 1083 case INTEL_ATOM_SILVERMONT: 1084 return "silvermont"; 1085 default: 1086 return "atom"; 1087 } 1088 case INTEL_XEONPHI: 1089 return "knl"; /*update for more variants added*/ 1090 case INTEL_X86_64: 1091 return "x86-64"; 1092 case INTEL_NOCONA: 1093 return "nocona"; 1094 case INTEL_PRESCOTT: 1095 return "prescott"; 1096 default: 1097 return "generic"; 1098 } 1099 } else if (Vendor == SIG_AMD) { 1100 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1101 switch (Type) { 1102 case AMD_i486: 1103 return "i486"; 1104 case AMDPENTIUM: 1105 switch (Subtype) { 1106 case AMDPENTIUM_K6: 1107 return "k6"; 1108 case AMDPENTIUM_K62: 1109 return "k6-2"; 1110 case AMDPENTIUM_K63: 1111 return "k6-3"; 1112 case AMDPENTIUM_GEODE: 1113 return "geode"; 1114 default: 1115 return "pentium"; 1116 } 1117 case AMDATHLON: 1118 switch (Subtype) { 1119 case AMDATHLON_TBIRD: 1120 return "athlon-tbird"; 1121 case AMDATHLON_MP: 1122 return "athlon-mp"; 1123 case AMDATHLON_XP: 1124 return "athlon-xp"; 1125 case AMDATHLON_K8SSE3: 1126 return "k8-sse3"; 1127 case AMDATHLON_OPTERON: 1128 return "opteron"; 1129 case AMDATHLON_FX: 1130 return "athlon-fx"; 1131 case AMDATHLON_64: 1132 return "athlon64"; 1133 default: 1134 return "athlon"; 1135 } 1136 case AMDFAM10H: 1137 if(Subtype == AMDFAM10H_BARCELONA) 1138 return "barcelona"; 1139 return "amdfam10"; 1140 case AMDFAM14H: 1141 return "btver1"; 1142 case AMDFAM15H: 1143 switch (Subtype) { 1144 case AMDFAM15H_BDVER1: 1145 return "bdver1"; 1146 case AMDFAM15H_BDVER2: 1147 return "bdver2"; 1148 case AMDFAM15H_BDVER3: 1149 return "bdver3"; 1150 case AMDFAM15H_BDVER4: 1151 return "bdver4"; 1152 case AMD_BTVER1: 1153 return "btver1"; 1154 default: 1155 return "amdfam15"; 1156 } 1157 case AMDFAM16H: 1158 switch (Subtype) { 1159 case AMD_BTVER1: 1160 return "btver1"; 1161 case AMD_BTVER2: 1162 return "btver2"; 1163 default: 1164 return "amdfam16"; 1165 } 1166 case AMDFAM17H: 1167 switch (Subtype) { 1168 case AMD_BTVER1: 1169 return "btver1"; 1170 case AMDFAM17H_ZNVER1: 1171 return "znver1"; 1172 default: 1173 return "amdfam17"; 1174 } 1175 default: 1176 return "generic"; 1177 } 1178 } 1179 return "generic"; 1180 } 1181 1182 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1183 StringRef sys::getHostCPUName() { 1184 host_basic_info_data_t hostInfo; 1185 mach_msg_type_number_t infoCount; 1186 1187 infoCount = HOST_BASIC_INFO_COUNT; 1188 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo, 1189 &infoCount); 1190 1191 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1192 return "generic"; 1193 1194 switch (hostInfo.cpu_subtype) { 1195 case CPU_SUBTYPE_POWERPC_601: 1196 return "601"; 1197 case CPU_SUBTYPE_POWERPC_602: 1198 return "602"; 1199 case CPU_SUBTYPE_POWERPC_603: 1200 return "603"; 1201 case CPU_SUBTYPE_POWERPC_603e: 1202 return "603e"; 1203 case CPU_SUBTYPE_POWERPC_603ev: 1204 return "603ev"; 1205 case CPU_SUBTYPE_POWERPC_604: 1206 return "604"; 1207 case CPU_SUBTYPE_POWERPC_604e: 1208 return "604e"; 1209 case CPU_SUBTYPE_POWERPC_620: 1210 return "620"; 1211 case CPU_SUBTYPE_POWERPC_750: 1212 return "750"; 1213 case CPU_SUBTYPE_POWERPC_7400: 1214 return "7400"; 1215 case CPU_SUBTYPE_POWERPC_7450: 1216 return "7450"; 1217 case CPU_SUBTYPE_POWERPC_970: 1218 return "970"; 1219 default:; 1220 } 1221 1222 return "generic"; 1223 } 1224 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1225 StringRef sys::getHostCPUName() { 1226 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1227 const StringRef& Content = P ? P->getBuffer() : ""; 1228 return detail::getHostCPUNameForPowerPC(Content); 1229 } 1230 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1231 StringRef sys::getHostCPUName() { 1232 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1233 const StringRef& Content = P ? P->getBuffer() : ""; 1234 return detail::getHostCPUNameForARM(Content); 1235 } 1236 #elif defined(__linux__) && defined(__s390x__) 1237 StringRef sys::getHostCPUName() { 1238 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1239 const StringRef& Content = P ? P->getBuffer() : ""; 1240 return detail::getHostCPUNameForS390x(Content); 1241 } 1242 #else 1243 StringRef sys::getHostCPUName() { return "generic"; } 1244 #endif 1245 1246 #if defined(__linux__) && defined(__x86_64__) 1247 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1248 // using the number of unique physical/core id pairs. The following 1249 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1250 static int computeHostNumPhysicalCores() { 1251 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1252 // mmapped because it appears to have 0 size. 1253 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1254 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1255 if (std::error_code EC = Text.getError()) { 1256 llvm::errs() << "Can't read " 1257 << "/proc/cpuinfo: " << EC.message() << "\n"; 1258 } 1259 SmallVector<StringRef, 8> strs; 1260 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1261 /*KeepEmpty=*/false); 1262 int CurPhysicalId = -1; 1263 int CurCoreId = -1; 1264 SmallSet<std::pair<int, int>, 32> UniqueItems; 1265 for (auto &Line : strs) { 1266 Line = Line.trim(); 1267 if (!Line.startswith("physical id") && !Line.startswith("core id")) 1268 continue; 1269 std::pair<StringRef, StringRef> Data = Line.split(':'); 1270 auto Name = Data.first.trim(); 1271 auto Val = Data.second.trim(); 1272 if (Name == "physical id") { 1273 assert(CurPhysicalId == -1 && 1274 "Expected a core id before seeing another physical id"); 1275 Val.getAsInteger(10, CurPhysicalId); 1276 } 1277 if (Name == "core id") { 1278 assert(CurCoreId == -1 && 1279 "Expected a physical id before seeing another core id"); 1280 Val.getAsInteger(10, CurCoreId); 1281 } 1282 if (CurPhysicalId != -1 && CurCoreId != -1) { 1283 UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId)); 1284 CurPhysicalId = -1; 1285 CurCoreId = -1; 1286 } 1287 } 1288 return UniqueItems.size(); 1289 } 1290 #elif defined(__APPLE__) && defined(__x86_64__) 1291 #include <sys/param.h> 1292 #include <sys/sysctl.h> 1293 1294 // Gets the number of *physical cores* on the machine. 1295 static int computeHostNumPhysicalCores() { 1296 uint32_t count; 1297 size_t len = sizeof(count); 1298 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1299 if (count < 1) { 1300 int nm[2]; 1301 nm[0] = CTL_HW; 1302 nm[1] = HW_AVAILCPU; 1303 sysctl(nm, 2, &count, &len, NULL, 0); 1304 if (count < 1) 1305 return -1; 1306 } 1307 return count; 1308 } 1309 #else 1310 // On other systems, return -1 to indicate unknown. 1311 static int computeHostNumPhysicalCores() { return -1; } 1312 #endif 1313 1314 int sys::getHostNumPhysicalCores() { 1315 static int NumCores = computeHostNumPhysicalCores(); 1316 return NumCores; 1317 } 1318 1319 #if defined(__i386__) || defined(_M_IX86) || \ 1320 defined(__x86_64__) || defined(_M_X64) 1321 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1322 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1323 unsigned MaxLevel; 1324 union { 1325 unsigned u[3]; 1326 char c[12]; 1327 } text; 1328 1329 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1330 MaxLevel < 1) 1331 return false; 1332 1333 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1334 1335 Features["cmov"] = (EDX >> 15) & 1; 1336 Features["mmx"] = (EDX >> 23) & 1; 1337 Features["sse"] = (EDX >> 25) & 1; 1338 Features["sse2"] = (EDX >> 26) & 1; 1339 Features["sse3"] = (ECX >> 0) & 1; 1340 Features["ssse3"] = (ECX >> 9) & 1; 1341 Features["sse4.1"] = (ECX >> 19) & 1; 1342 Features["sse4.2"] = (ECX >> 20) & 1; 1343 1344 Features["pclmul"] = (ECX >> 1) & 1; 1345 Features["cx16"] = (ECX >> 13) & 1; 1346 Features["movbe"] = (ECX >> 22) & 1; 1347 Features["popcnt"] = (ECX >> 23) & 1; 1348 Features["aes"] = (ECX >> 25) & 1; 1349 Features["rdrnd"] = (ECX >> 30) & 1; 1350 1351 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1352 // indicates that the AVX registers will be saved and restored on context 1353 // switch, then we have full AVX support. 1354 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1355 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1356 Features["avx"] = HasAVXSave; 1357 Features["fma"] = HasAVXSave && (ECX >> 12) & 1; 1358 Features["f16c"] = HasAVXSave && (ECX >> 29) & 1; 1359 1360 // Only enable XSAVE if OS has enabled support for saving YMM state. 1361 Features["xsave"] = HasAVXSave && (ECX >> 26) & 1; 1362 1363 // AVX512 requires additional context to be saved by the OS. 1364 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1365 1366 unsigned MaxExtLevel; 1367 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1368 1369 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1370 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1371 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1372 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1373 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1374 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1375 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1376 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1377 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1378 1379 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1380 !getX86CpuIDAndInfoEx(0x80000008,0x0, &EAX, &EBX, &ECX, &EDX); 1381 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1382 1383 bool HasLeaf7 = 1384 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1385 1386 // AVX2 is only supported if we have the OS save support from AVX. 1387 Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1); 1388 1389 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1390 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1391 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1392 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1393 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1394 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1395 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1396 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1397 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1398 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1399 1400 // AVX512 is only supported if the OS supports the context save for it. 1401 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1402 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1403 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1404 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1405 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1406 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1407 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1408 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1409 1410 Features["prefetchwt1"] = HasLeaf7 && (ECX & 1); 1411 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1412 // Enable protection keys 1413 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1414 1415 bool HasLeafD = MaxLevel >= 0xd && 1416 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1417 1418 // Only enable XSAVE if OS has enabled support for saving YMM state. 1419 Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1); 1420 Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1); 1421 Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1); 1422 1423 return true; 1424 } 1425 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1426 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1427 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1428 if (!P) 1429 return false; 1430 1431 SmallVector<StringRef, 32> Lines; 1432 P->getBuffer().split(Lines, "\n"); 1433 1434 SmallVector<StringRef, 32> CPUFeatures; 1435 1436 // Look for the CPU features. 1437 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1438 if (Lines[I].startswith("Features")) { 1439 Lines[I].split(CPUFeatures, ' '); 1440 break; 1441 } 1442 1443 #if defined(__aarch64__) 1444 // Keep track of which crypto features we have seen 1445 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1446 uint32_t crypto = 0; 1447 #endif 1448 1449 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1450 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1451 #if defined(__aarch64__) 1452 .Case("asimd", "neon") 1453 .Case("fp", "fp-armv8") 1454 .Case("crc32", "crc") 1455 #else 1456 .Case("half", "fp16") 1457 .Case("neon", "neon") 1458 .Case("vfpv3", "vfp3") 1459 .Case("vfpv3d16", "d16") 1460 .Case("vfpv4", "vfp4") 1461 .Case("idiva", "hwdiv-arm") 1462 .Case("idivt", "hwdiv") 1463 #endif 1464 .Default(""); 1465 1466 #if defined(__aarch64__) 1467 // We need to check crypto separately since we need all of the crypto 1468 // extensions to enable the subtarget feature 1469 if (CPUFeatures[I] == "aes") 1470 crypto |= CAP_AES; 1471 else if (CPUFeatures[I] == "pmull") 1472 crypto |= CAP_PMULL; 1473 else if (CPUFeatures[I] == "sha1") 1474 crypto |= CAP_SHA1; 1475 else if (CPUFeatures[I] == "sha2") 1476 crypto |= CAP_SHA2; 1477 #endif 1478 1479 if (LLVMFeatureStr != "") 1480 Features[LLVMFeatureStr] = true; 1481 } 1482 1483 #if defined(__aarch64__) 1484 // If we have all crypto bits we can add the feature 1485 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1486 Features["crypto"] = true; 1487 #endif 1488 1489 return true; 1490 } 1491 #else 1492 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1493 #endif 1494 1495 std::string sys::getProcessTriple() { 1496 Triple PT(Triple::normalize(LLVM_HOST_TRIPLE)); 1497 1498 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1499 PT = PT.get64BitArchVariant(); 1500 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1501 PT = PT.get32BitArchVariant(); 1502 1503 return PT.str(); 1504 } 1505