1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //  This file implements the operating system Host concept.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/Support/Host.h"
14 #include "llvm/ADT/SmallSet.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringMap.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/Config/llvm-config.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/FileSystem.h"
23 #include "llvm/Support/MemoryBuffer.h"
24 #include "llvm/Support/X86TargetParser.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include <assert.h>
27 #include <string.h>
28 
29 // Include the platform-specific parts of this class.
30 #ifdef LLVM_ON_UNIX
31 #include "Unix/Host.inc"
32 #include <sched.h>
33 #endif
34 #ifdef _WIN32
35 #include "Windows/Host.inc"
36 #endif
37 #ifdef _MSC_VER
38 #include <intrin.h>
39 #endif
40 #if defined(__APPLE__) && (!defined(__x86_64__))
41 #include <mach/host_info.h>
42 #include <mach/mach.h>
43 #include <mach/mach_host.h>
44 #include <mach/machine.h>
45 #endif
46 
47 #define DEBUG_TYPE "host-detection"
48 
49 //===----------------------------------------------------------------------===//
50 //
51 //  Implementations of the CPU detection routines
52 //
53 //===----------------------------------------------------------------------===//
54 
55 using namespace llvm;
56 
57 static std::unique_ptr<llvm::MemoryBuffer>
58     LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() {
59   llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text =
60       llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
61   if (std::error_code EC = Text.getError()) {
62     llvm::errs() << "Can't read "
63                  << "/proc/cpuinfo: " << EC.message() << "\n";
64     return nullptr;
65   }
66   return std::move(*Text);
67 }
68 
69 StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) {
70   // Access to the Processor Version Register (PVR) on PowerPC is privileged,
71   // and so we must use an operating-system interface to determine the current
72   // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
73   const char *generic = "generic";
74 
75   // The cpu line is second (after the 'processor: 0' line), so if this
76   // buffer is too small then something has changed (or is wrong).
77   StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin();
78   StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end();
79 
80   StringRef::const_iterator CIP = CPUInfoStart;
81 
82   StringRef::const_iterator CPUStart = 0;
83   size_t CPULen = 0;
84 
85   // We need to find the first line which starts with cpu, spaces, and a colon.
86   // After the colon, there may be some additional spaces and then the cpu type.
87   while (CIP < CPUInfoEnd && CPUStart == 0) {
88     if (CIP < CPUInfoEnd && *CIP == '\n')
89       ++CIP;
90 
91     if (CIP < CPUInfoEnd && *CIP == 'c') {
92       ++CIP;
93       if (CIP < CPUInfoEnd && *CIP == 'p') {
94         ++CIP;
95         if (CIP < CPUInfoEnd && *CIP == 'u') {
96           ++CIP;
97           while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
98             ++CIP;
99 
100           if (CIP < CPUInfoEnd && *CIP == ':') {
101             ++CIP;
102             while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
103               ++CIP;
104 
105             if (CIP < CPUInfoEnd) {
106               CPUStart = CIP;
107               while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
108                                           *CIP != ',' && *CIP != '\n'))
109                 ++CIP;
110               CPULen = CIP - CPUStart;
111             }
112           }
113         }
114       }
115     }
116 
117     if (CPUStart == 0)
118       while (CIP < CPUInfoEnd && *CIP != '\n')
119         ++CIP;
120   }
121 
122   if (CPUStart == 0)
123     return generic;
124 
125   return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
126       .Case("604e", "604e")
127       .Case("604", "604")
128       .Case("7400", "7400")
129       .Case("7410", "7400")
130       .Case("7447", "7400")
131       .Case("7455", "7450")
132       .Case("G4", "g4")
133       .Case("POWER4", "970")
134       .Case("PPC970FX", "970")
135       .Case("PPC970MP", "970")
136       .Case("G5", "g5")
137       .Case("POWER5", "g5")
138       .Case("A2", "a2")
139       .Case("POWER6", "pwr6")
140       .Case("POWER7", "pwr7")
141       .Case("POWER8", "pwr8")
142       .Case("POWER8E", "pwr8")
143       .Case("POWER8NVL", "pwr8")
144       .Case("POWER9", "pwr9")
145       .Case("POWER10", "pwr10")
146       // FIXME: If we get a simulator or machine with the capabilities of
147       // mcpu=future, we should revisit this and add the name reported by the
148       // simulator/machine.
149       .Default(generic);
150 }
151 
152 StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) {
153   // The cpuid register on arm is not accessible from user space. On Linux,
154   // it is exposed through the /proc/cpuinfo file.
155 
156   // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line
157   // in all cases.
158   SmallVector<StringRef, 32> Lines;
159   ProcCpuinfoContent.split(Lines, "\n");
160 
161   // Look for the CPU implementer line.
162   StringRef Implementer;
163   StringRef Hardware;
164   for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
165     if (Lines[I].startswith("CPU implementer"))
166       Implementer = Lines[I].substr(15).ltrim("\t :");
167     if (Lines[I].startswith("Hardware"))
168       Hardware = Lines[I].substr(8).ltrim("\t :");
169   }
170 
171   if (Implementer == "0x41") { // ARM Ltd.
172     // MSM8992/8994 may give cpu part for the core that the kernel is running on,
173     // which is undeterministic and wrong. Always return cortex-a53 for these SoC.
174     if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996"))
175       return "cortex-a53";
176 
177 
178     // Look for the CPU part line.
179     for (unsigned I = 0, E = Lines.size(); I != E; ++I)
180       if (Lines[I].startswith("CPU part"))
181         // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
182         // values correspond to the "Part number" in the CP15/c0 register. The
183         // contents are specified in the various processor manuals.
184         // This corresponds to the Main ID Register in Technical Reference Manuals.
185         // and is used in programs like sys-utils
186         return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
187             .Case("0x926", "arm926ej-s")
188             .Case("0xb02", "mpcore")
189             .Case("0xb36", "arm1136j-s")
190             .Case("0xb56", "arm1156t2-s")
191             .Case("0xb76", "arm1176jz-s")
192             .Case("0xc08", "cortex-a8")
193             .Case("0xc09", "cortex-a9")
194             .Case("0xc0f", "cortex-a15")
195             .Case("0xc20", "cortex-m0")
196             .Case("0xc23", "cortex-m3")
197             .Case("0xc24", "cortex-m4")
198             .Case("0xd22", "cortex-m55")
199             .Case("0xd02", "cortex-a34")
200             .Case("0xd04", "cortex-a35")
201             .Case("0xd03", "cortex-a53")
202             .Case("0xd07", "cortex-a57")
203             .Case("0xd08", "cortex-a72")
204             .Case("0xd09", "cortex-a73")
205             .Case("0xd0a", "cortex-a75")
206             .Case("0xd0b", "cortex-a76")
207             .Case("0xd0d", "cortex-a77")
208             .Case("0xd41", "cortex-a78")
209             .Case("0xd44", "cortex-x1")
210             .Case("0xd0c", "neoverse-n1")
211             .Case("0xd49", "neoverse-n2")
212             .Default("generic");
213   }
214 
215   if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium.
216     for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
217       if (Lines[I].startswith("CPU part")) {
218         return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
219           .Case("0x516", "thunderx2t99")
220           .Case("0x0516", "thunderx2t99")
221           .Case("0xaf", "thunderx2t99")
222           .Case("0x0af", "thunderx2t99")
223           .Case("0xa1", "thunderxt88")
224           .Case("0x0a1", "thunderxt88")
225           .Default("generic");
226       }
227     }
228   }
229 
230   if (Implementer == "0x46") { // Fujitsu Ltd.
231     for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
232       if (Lines[I].startswith("CPU part")) {
233         return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
234           .Case("0x001", "a64fx")
235           .Default("generic");
236       }
237     }
238   }
239 
240   if (Implementer == "0x4e") { // NVIDIA Corporation
241     for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
242       if (Lines[I].startswith("CPU part")) {
243         return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
244             .Case("0x004", "carmel")
245             .Default("generic");
246       }
247     }
248   }
249 
250   if (Implementer == "0x48") // HiSilicon Technologies, Inc.
251     // Look for the CPU part line.
252     for (unsigned I = 0, E = Lines.size(); I != E; ++I)
253       if (Lines[I].startswith("CPU part"))
254         // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
255         // values correspond to the "Part number" in the CP15/c0 register. The
256         // contents are specified in the various processor manuals.
257         return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
258           .Case("0xd01", "tsv110")
259           .Default("generic");
260 
261   if (Implementer == "0x51") // Qualcomm Technologies, Inc.
262     // Look for the CPU part line.
263     for (unsigned I = 0, E = Lines.size(); I != E; ++I)
264       if (Lines[I].startswith("CPU part"))
265         // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
266         // values correspond to the "Part number" in the CP15/c0 register. The
267         // contents are specified in the various processor manuals.
268         return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
269             .Case("0x06f", "krait") // APQ8064
270             .Case("0x201", "kryo")
271             .Case("0x205", "kryo")
272             .Case("0x211", "kryo")
273             .Case("0x800", "cortex-a73")
274             .Case("0x801", "cortex-a73")
275             .Case("0x802", "cortex-a73")
276             .Case("0x803", "cortex-a73")
277             .Case("0x804", "cortex-a73")
278             .Case("0x805", "cortex-a73")
279             .Case("0xc00", "falkor")
280             .Case("0xc01", "saphira")
281             .Default("generic");
282 
283   if (Implementer == "0x53") { // Samsung Electronics Co., Ltd.
284     // The Exynos chips have a convoluted ID scheme that doesn't seem to follow
285     // any predictive pattern across variants and parts.
286     unsigned Variant = 0, Part = 0;
287 
288     // Look for the CPU variant line, whose value is a 1 digit hexadecimal
289     // number, corresponding to the Variant bits in the CP15/C0 register.
290     for (auto I : Lines)
291       if (I.consume_front("CPU variant"))
292         I.ltrim("\t :").getAsInteger(0, Variant);
293 
294     // Look for the CPU part line, whose value is a 3 digit hexadecimal
295     // number, corresponding to the PartNum bits in the CP15/C0 register.
296     for (auto I : Lines)
297       if (I.consume_front("CPU part"))
298         I.ltrim("\t :").getAsInteger(0, Part);
299 
300     unsigned Exynos = (Variant << 12) | Part;
301     switch (Exynos) {
302     default:
303       // Default by falling through to Exynos M3.
304       LLVM_FALLTHROUGH;
305     case 0x1002:
306       return "exynos-m3";
307     case 0x1003:
308       return "exynos-m4";
309     }
310   }
311 
312   return "generic";
313 }
314 
315 StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) {
316   // STIDP is a privileged operation, so use /proc/cpuinfo instead.
317 
318   // The "processor 0:" line comes after a fair amount of other information,
319   // including a cache breakdown, but this should be plenty.
320   SmallVector<StringRef, 32> Lines;
321   ProcCpuinfoContent.split(Lines, "\n");
322 
323   // Look for the CPU features.
324   SmallVector<StringRef, 32> CPUFeatures;
325   for (unsigned I = 0, E = Lines.size(); I != E; ++I)
326     if (Lines[I].startswith("features")) {
327       size_t Pos = Lines[I].find(":");
328       if (Pos != StringRef::npos) {
329         Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' ');
330         break;
331       }
332     }
333 
334   // We need to check for the presence of vector support independently of
335   // the machine type, since we may only use the vector register set when
336   // supported by the kernel (and hypervisor).
337   bool HaveVectorSupport = false;
338   for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
339     if (CPUFeatures[I] == "vx")
340       HaveVectorSupport = true;
341   }
342 
343   // Now check the processor machine type.
344   for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
345     if (Lines[I].startswith("processor ")) {
346       size_t Pos = Lines[I].find("machine = ");
347       if (Pos != StringRef::npos) {
348         Pos += sizeof("machine = ") - 1;
349         unsigned int Id;
350         if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
351           if (Id >= 8561 && HaveVectorSupport)
352             return "z15";
353           if (Id >= 3906 && HaveVectorSupport)
354             return "z14";
355           if (Id >= 2964 && HaveVectorSupport)
356             return "z13";
357           if (Id >= 2827)
358             return "zEC12";
359           if (Id >= 2817)
360             return "z196";
361         }
362       }
363       break;
364     }
365   }
366 
367   return "generic";
368 }
369 
370 StringRef sys::detail::getHostCPUNameForBPF() {
371 #if !defined(__linux__) || !defined(__x86_64__)
372   return "generic";
373 #else
374   uint8_t v3_insns[40] __attribute__ ((aligned (8))) =
375       /* BPF_MOV64_IMM(BPF_REG_0, 0) */
376     { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
377       /* BPF_MOV64_IMM(BPF_REG_2, 1) */
378       0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
379       /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
380       0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
381       /* BPF_MOV64_IMM(BPF_REG_0, 1) */
382       0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
383       /* BPF_EXIT_INSN() */
384       0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
385 
386   uint8_t v2_insns[40] __attribute__ ((aligned (8))) =
387       /* BPF_MOV64_IMM(BPF_REG_0, 0) */
388     { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
389       /* BPF_MOV64_IMM(BPF_REG_2, 1) */
390       0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
391       /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
392       0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
393       /* BPF_MOV64_IMM(BPF_REG_0, 1) */
394       0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
395       /* BPF_EXIT_INSN() */
396       0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
397 
398   struct bpf_prog_load_attr {
399     uint32_t prog_type;
400     uint32_t insn_cnt;
401     uint64_t insns;
402     uint64_t license;
403     uint32_t log_level;
404     uint32_t log_size;
405     uint64_t log_buf;
406     uint32_t kern_version;
407     uint32_t prog_flags;
408   } attr = {};
409   attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
410   attr.insn_cnt = 5;
411   attr.insns = (uint64_t)v3_insns;
412   attr.license = (uint64_t)"DUMMY";
413 
414   int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr,
415                    sizeof(attr));
416   if (fd >= 0) {
417     close(fd);
418     return "v3";
419   }
420 
421   /* Clear the whole attr in case its content changed by syscall. */
422   memset(&attr, 0, sizeof(attr));
423   attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
424   attr.insn_cnt = 5;
425   attr.insns = (uint64_t)v2_insns;
426   attr.license = (uint64_t)"DUMMY";
427   fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr));
428   if (fd >= 0) {
429     close(fd);
430     return "v2";
431   }
432   return "v1";
433 #endif
434 }
435 
436 #if defined(__i386__) || defined(_M_IX86) || \
437     defined(__x86_64__) || defined(_M_X64)
438 
439 enum VendorSignatures {
440   SIG_INTEL = 0x756e6547 /* Genu */,
441   SIG_AMD = 0x68747541 /* Auth */
442 };
443 
444 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max).
445 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID
446 // support. Consequently, for i386, the presence of CPUID is checked first
447 // via the corresponding eflags bit.
448 // Removal of cpuid.h header motivated by PR30384
449 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp
450 // or test-suite, but are used in external projects e.g. libstdcxx
451 static bool isCpuIdSupported() {
452 #if defined(__GNUC__) || defined(__clang__)
453 #if defined(__i386__)
454   int __cpuid_supported;
455   __asm__("  pushfl\n"
456           "  popl   %%eax\n"
457           "  movl   %%eax,%%ecx\n"
458           "  xorl   $0x00200000,%%eax\n"
459           "  pushl  %%eax\n"
460           "  popfl\n"
461           "  pushfl\n"
462           "  popl   %%eax\n"
463           "  movl   $0,%0\n"
464           "  cmpl   %%eax,%%ecx\n"
465           "  je     1f\n"
466           "  movl   $1,%0\n"
467           "1:"
468           : "=r"(__cpuid_supported)
469           :
470           : "eax", "ecx");
471   if (!__cpuid_supported)
472     return false;
473 #endif
474   return true;
475 #endif
476   return true;
477 }
478 
479 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
480 /// the specified arguments.  If we can't run cpuid on the host, return true.
481 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
482                                unsigned *rECX, unsigned *rEDX) {
483 #if defined(__GNUC__) || defined(__clang__)
484 #if defined(__x86_64__)
485   // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
486   // FIXME: should we save this for Clang?
487   __asm__("movq\t%%rbx, %%rsi\n\t"
488           "cpuid\n\t"
489           "xchgq\t%%rbx, %%rsi\n\t"
490           : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
491           : "a"(value));
492   return false;
493 #elif defined(__i386__)
494   __asm__("movl\t%%ebx, %%esi\n\t"
495           "cpuid\n\t"
496           "xchgl\t%%ebx, %%esi\n\t"
497           : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
498           : "a"(value));
499   return false;
500 #else
501   return true;
502 #endif
503 #elif defined(_MSC_VER)
504   // The MSVC intrinsic is portable across x86 and x64.
505   int registers[4];
506   __cpuid(registers, value);
507   *rEAX = registers[0];
508   *rEBX = registers[1];
509   *rECX = registers[2];
510   *rEDX = registers[3];
511   return false;
512 #else
513   return true;
514 #endif
515 }
516 
517 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
518 /// the 4 values in the specified arguments.  If we can't run cpuid on the host,
519 /// return true.
520 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
521                                  unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
522                                  unsigned *rEDX) {
523 #if defined(__GNUC__) || defined(__clang__)
524 #if defined(__x86_64__)
525   // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
526   // FIXME: should we save this for Clang?
527   __asm__("movq\t%%rbx, %%rsi\n\t"
528           "cpuid\n\t"
529           "xchgq\t%%rbx, %%rsi\n\t"
530           : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
531           : "a"(value), "c"(subleaf));
532   return false;
533 #elif defined(__i386__)
534   __asm__("movl\t%%ebx, %%esi\n\t"
535           "cpuid\n\t"
536           "xchgl\t%%ebx, %%esi\n\t"
537           : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
538           : "a"(value), "c"(subleaf));
539   return false;
540 #else
541   return true;
542 #endif
543 #elif defined(_MSC_VER)
544   int registers[4];
545   __cpuidex(registers, value, subleaf);
546   *rEAX = registers[0];
547   *rEBX = registers[1];
548   *rECX = registers[2];
549   *rEDX = registers[3];
550   return false;
551 #else
552   return true;
553 #endif
554 }
555 
556 // Read control register 0 (XCR0). Used to detect features such as AVX.
557 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {
558 #if defined(__GNUC__) || defined(__clang__)
559   // Check xgetbv; this uses a .byte sequence instead of the instruction
560   // directly because older assemblers do not include support for xgetbv and
561   // there is no easy way to conditionally compile based on the assembler used.
562   __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
563   return false;
564 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
565   unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
566   *rEAX = Result;
567   *rEDX = Result >> 32;
568   return false;
569 #else
570   return true;
571 #endif
572 }
573 
574 static void detectX86FamilyModel(unsigned EAX, unsigned *Family,
575                                  unsigned *Model) {
576   *Family = (EAX >> 8) & 0xf; // Bits 8 - 11
577   *Model = (EAX >> 4) & 0xf;  // Bits 4 - 7
578   if (*Family == 6 || *Family == 0xf) {
579     if (*Family == 0xf)
580       // Examine extended family ID if family ID is F.
581       *Family += (EAX >> 20) & 0xff; // Bits 20 - 27
582     // Examine extended model ID if family ID is 6 or F.
583     *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
584   }
585 }
586 
587 static StringRef
588 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
589                                 const unsigned *Features,
590                                 unsigned *Type, unsigned *Subtype) {
591   auto testFeature = [&](unsigned F) {
592     return (Features[F / 32] & (1U << (F % 32))) != 0;
593   };
594 
595   StringRef CPU;
596 
597   switch (Family) {
598   case 3:
599     CPU = "i386";
600     break;
601   case 4:
602     CPU = "i486";
603     break;
604   case 5:
605     if (testFeature(X86::FEATURE_MMX)) {
606       CPU = "pentium-mmx";
607       break;
608     }
609     CPU = "pentium";
610     break;
611   case 6:
612     switch (Model) {
613     case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
614                // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
615                // mobile processor, Intel Core 2 Extreme processor, Intel
616                // Pentium Dual-Core processor, Intel Xeon processor, model
617                // 0Fh. All processors are manufactured using the 65 nm process.
618     case 0x16: // Intel Celeron processor model 16h. All processors are
619                // manufactured using the 65 nm process
620       CPU = "core2";
621       *Type = X86::INTEL_CORE2;
622       break;
623     case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
624                // 17h. All processors are manufactured using the 45 nm process.
625                //
626                // 45nm: Penryn , Wolfdale, Yorkfield (XE)
627     case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
628                // the 45 nm process.
629       CPU = "penryn";
630       *Type = X86::INTEL_CORE2;
631       break;
632     case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
633                // processors are manufactured using the 45 nm process.
634     case 0x1e: // Intel(R) Core(TM) i7 CPU         870  @ 2.93GHz.
635                // As found in a Summer 2010 model iMac.
636     case 0x1f:
637     case 0x2e:              // Nehalem EX
638       CPU = "nehalem";
639       *Type = X86::INTEL_COREI7;
640       *Subtype = X86::INTEL_COREI7_NEHALEM;
641       break;
642     case 0x25: // Intel Core i7, laptop version.
643     case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
644                // processors are manufactured using the 32 nm process.
645     case 0x2f: // Westmere EX
646       CPU = "westmere";
647       *Type = X86::INTEL_COREI7;
648       *Subtype = X86::INTEL_COREI7_WESTMERE;
649       break;
650     case 0x2a: // Intel Core i7 processor. All processors are manufactured
651                // using the 32 nm process.
652     case 0x2d:
653       CPU = "sandybridge";
654       *Type = X86::INTEL_COREI7;
655       *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
656       break;
657     case 0x3a:
658     case 0x3e:              // Ivy Bridge EP
659       CPU = "ivybridge";
660       *Type = X86::INTEL_COREI7;
661       *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
662       break;
663 
664     // Haswell:
665     case 0x3c:
666     case 0x3f:
667     case 0x45:
668     case 0x46:
669       CPU = "haswell";
670       *Type = X86::INTEL_COREI7;
671       *Subtype = X86::INTEL_COREI7_HASWELL;
672       break;
673 
674     // Broadwell:
675     case 0x3d:
676     case 0x47:
677     case 0x4f:
678     case 0x56:
679       CPU = "broadwell";
680       *Type = X86::INTEL_COREI7;
681       *Subtype = X86::INTEL_COREI7_BROADWELL;
682       break;
683 
684     // Skylake:
685     case 0x4e:              // Skylake mobile
686     case 0x5e:              // Skylake desktop
687     case 0x8e:              // Kaby Lake mobile
688     case 0x9e:              // Kaby Lake desktop
689     case 0xa5:              // Comet Lake-H/S
690     case 0xa6:              // Comet Lake-U
691       CPU = "skylake";
692       *Type = X86::INTEL_COREI7;
693       *Subtype = X86::INTEL_COREI7_SKYLAKE;
694       break;
695 
696     // Skylake Xeon:
697     case 0x55:
698       *Type = X86::INTEL_COREI7;
699       if (testFeature(X86::FEATURE_AVX512BF16)) {
700         CPU = "cooperlake";
701         *Subtype = X86::INTEL_COREI7_COOPERLAKE;
702       } else if (testFeature(X86::FEATURE_AVX512VNNI)) {
703         CPU = "cascadelake";
704         *Subtype = X86::INTEL_COREI7_CASCADELAKE;
705       } else {
706         CPU = "skylake-avx512";
707         *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
708       }
709       break;
710 
711     // Cannonlake:
712     case 0x66:
713       CPU = "cannonlake";
714       *Type = X86::INTEL_COREI7;
715       *Subtype = X86::INTEL_COREI7_CANNONLAKE;
716       break;
717 
718     // Icelake:
719     case 0x7d:
720     case 0x7e:
721       CPU = "icelake-client";
722       *Type = X86::INTEL_COREI7;
723       *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
724       break;
725 
726     // Icelake Xeon:
727     case 0x6a:
728     case 0x6c:
729       CPU = "icelake-server";
730       *Type = X86::INTEL_COREI7;
731       *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER;
732       break;
733 
734     // Sapphire Rapids:
735     case 0x8f:
736       CPU = "sapphirerapids";
737       *Type = X86::INTEL_COREI7;
738       *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;
739       break;
740 
741     case 0x1c: // Most 45 nm Intel Atom processors
742     case 0x26: // 45 nm Atom Lincroft
743     case 0x27: // 32 nm Atom Medfield
744     case 0x35: // 32 nm Atom Midview
745     case 0x36: // 32 nm Atom Midview
746       CPU = "bonnell";
747       *Type = X86::INTEL_BONNELL;
748       break;
749 
750     // Atom Silvermont codes from the Intel software optimization guide.
751     case 0x37:
752     case 0x4a:
753     case 0x4d:
754     case 0x5a:
755     case 0x5d:
756     case 0x4c: // really airmont
757       CPU = "silvermont";
758       *Type = X86::INTEL_SILVERMONT;
759       break;
760     // Goldmont:
761     case 0x5c: // Apollo Lake
762     case 0x5f: // Denverton
763       CPU = "goldmont";
764       *Type = X86::INTEL_GOLDMONT;
765       break;
766     case 0x7a:
767       CPU = "goldmont-plus";
768       *Type = X86::INTEL_GOLDMONT_PLUS;
769       break;
770     case 0x86:
771       CPU = "tremont";
772       *Type = X86::INTEL_TREMONT;
773       break;
774 
775     // Xeon Phi (Knights Landing + Knights Mill):
776     case 0x57:
777       CPU = "knl";
778       *Type = X86::INTEL_KNL;
779       break;
780     case 0x85:
781       CPU = "knm";
782       *Type = X86::INTEL_KNM;
783       break;
784 
785     default: // Unknown family 6 CPU, try to guess.
786       // Don't both with Type/Subtype here, they aren't used by the caller.
787       // They're used above to keep the code in sync with compiler-rt.
788       // TODO detect tigerlake host from model
789       if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) {
790         CPU = "tigerlake";
791       } else if (testFeature(X86::FEATURE_AVX512VBMI2)) {
792         CPU = "icelake-client";
793       } else if (testFeature(X86::FEATURE_AVX512VBMI)) {
794         CPU = "cannonlake";
795       } else if (testFeature(X86::FEATURE_AVX512BF16)) {
796         CPU = "cooperlake";
797       } else if (testFeature(X86::FEATURE_AVX512VNNI)) {
798         CPU = "cascadelake";
799       } else if (testFeature(X86::FEATURE_AVX512VL)) {
800         CPU = "skylake-avx512";
801       } else if (testFeature(X86::FEATURE_AVX512ER)) {
802         CPU = "knl";
803       } else if (testFeature(X86::FEATURE_CLFLUSHOPT)) {
804         if (testFeature(X86::FEATURE_SHA))
805           CPU = "goldmont";
806         else
807           CPU = "skylake";
808       } else if (testFeature(X86::FEATURE_ADX)) {
809         CPU = "broadwell";
810       } else if (testFeature(X86::FEATURE_AVX2)) {
811         CPU = "haswell";
812       } else if (testFeature(X86::FEATURE_AVX)) {
813         CPU = "sandybridge";
814       } else if (testFeature(X86::FEATURE_SSE4_2)) {
815         if (testFeature(X86::FEATURE_MOVBE))
816           CPU = "silvermont";
817         else
818           CPU = "nehalem";
819       } else if (testFeature(X86::FEATURE_SSE4_1)) {
820         CPU = "penryn";
821       } else if (testFeature(X86::FEATURE_SSSE3)) {
822         if (testFeature(X86::FEATURE_MOVBE))
823           CPU = "bonnell";
824         else
825           CPU = "core2";
826       } else if (testFeature(X86::FEATURE_64BIT)) {
827         CPU = "core2";
828       } else if (testFeature(X86::FEATURE_SSE3)) {
829         CPU = "yonah";
830       } else if (testFeature(X86::FEATURE_SSE2)) {
831         CPU = "pentium-m";
832       } else if (testFeature(X86::FEATURE_SSE)) {
833         CPU = "pentium3";
834       } else if (testFeature(X86::FEATURE_MMX)) {
835         CPU = "pentium2";
836       } else {
837         CPU = "pentiumpro";
838       }
839       break;
840     }
841     break;
842   case 15: {
843     if (testFeature(X86::FEATURE_64BIT)) {
844       CPU = "nocona";
845       break;
846     }
847     if (testFeature(X86::FEATURE_SSE3)) {
848       CPU = "prescott";
849       break;
850     }
851     CPU = "pentium4";
852     break;
853   }
854   default:
855     break; // Unknown.
856   }
857 
858   return CPU;
859 }
860 
861 static StringRef
862 getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
863                               const unsigned *Features,
864                               unsigned *Type, unsigned *Subtype) {
865   auto testFeature = [&](unsigned F) {
866     return (Features[F / 32] & (1U << (F % 32))) != 0;
867   };
868 
869   StringRef CPU;
870 
871   switch (Family) {
872   case 4:
873     CPU = "i486";
874     break;
875   case 5:
876     CPU = "pentium";
877     switch (Model) {
878     case 6:
879     case 7:
880       CPU = "k6";
881       break;
882     case 8:
883       CPU = "k6-2";
884       break;
885     case 9:
886     case 13:
887       CPU = "k6-3";
888       break;
889     case 10:
890       CPU = "geode";
891       break;
892     }
893     break;
894   case 6:
895     if (testFeature(X86::FEATURE_SSE)) {
896       CPU = "athlon-xp";
897       break;
898     }
899     CPU = "athlon";
900     break;
901   case 15:
902     if (testFeature(X86::FEATURE_SSE3)) {
903       CPU = "k8-sse3";
904       break;
905     }
906     CPU = "k8";
907     break;
908   case 16:
909     CPU = "amdfam10";
910     *Type = X86::AMDFAM10H; // "amdfam10"
911     switch (Model) {
912     case 2:
913       *Subtype = X86::AMDFAM10H_BARCELONA;
914       break;
915     case 4:
916       *Subtype = X86::AMDFAM10H_SHANGHAI;
917       break;
918     case 8:
919       *Subtype = X86::AMDFAM10H_ISTANBUL;
920       break;
921     }
922     break;
923   case 20:
924     CPU = "btver1";
925     *Type = X86::AMD_BTVER1;
926     break;
927   case 21:
928     CPU = "bdver1";
929     *Type = X86::AMDFAM15H;
930     if (Model >= 0x60 && Model <= 0x7f) {
931       CPU = "bdver4";
932       *Subtype = X86::AMDFAM15H_BDVER4;
933       break; // 60h-7Fh: Excavator
934     }
935     if (Model >= 0x30 && Model <= 0x3f) {
936       CPU = "bdver3";
937       *Subtype = X86::AMDFAM15H_BDVER3;
938       break; // 30h-3Fh: Steamroller
939     }
940     if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) {
941       CPU = "bdver2";
942       *Subtype = X86::AMDFAM15H_BDVER2;
943       break; // 02h, 10h-1Fh: Piledriver
944     }
945     if (Model <= 0x0f) {
946       *Subtype = X86::AMDFAM15H_BDVER1;
947       break; // 00h-0Fh: Bulldozer
948     }
949     break;
950   case 22:
951     CPU = "btver2";
952     *Type = X86::AMD_BTVER2;
953     break;
954   case 23:
955     CPU = "znver1";
956     *Type = X86::AMDFAM17H;
957     if ((Model >= 0x30 && Model <= 0x3f) || Model == 0x71) {
958       CPU = "znver2";
959       *Subtype = X86::AMDFAM17H_ZNVER2;
960       break; // 30h-3fh, 71h: Zen2
961     }
962     if (Model <= 0x0f) {
963       *Subtype = X86::AMDFAM17H_ZNVER1;
964       break; // 00h-0Fh: Zen1
965     }
966     break;
967   default:
968     break; // Unknown AMD CPU.
969   }
970 
971   return CPU;
972 }
973 
974 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
975                                  unsigned *Features) {
976   unsigned EAX, EBX;
977 
978   auto setFeature = [&](unsigned F) {
979     Features[F / 32] |= 1U << (F % 32);
980   };
981 
982   if ((EDX >> 15) & 1)
983     setFeature(X86::FEATURE_CMOV);
984   if ((EDX >> 23) & 1)
985     setFeature(X86::FEATURE_MMX);
986   if ((EDX >> 25) & 1)
987     setFeature(X86::FEATURE_SSE);
988   if ((EDX >> 26) & 1)
989     setFeature(X86::FEATURE_SSE2);
990 
991   if ((ECX >> 0) & 1)
992     setFeature(X86::FEATURE_SSE3);
993   if ((ECX >> 1) & 1)
994     setFeature(X86::FEATURE_PCLMUL);
995   if ((ECX >> 9) & 1)
996     setFeature(X86::FEATURE_SSSE3);
997   if ((ECX >> 12) & 1)
998     setFeature(X86::FEATURE_FMA);
999   if ((ECX >> 19) & 1)
1000     setFeature(X86::FEATURE_SSE4_1);
1001   if ((ECX >> 20) & 1)
1002     setFeature(X86::FEATURE_SSE4_2);
1003   if ((ECX >> 23) & 1)
1004     setFeature(X86::FEATURE_POPCNT);
1005   if ((ECX >> 25) & 1)
1006     setFeature(X86::FEATURE_AES);
1007 
1008   if ((ECX >> 22) & 1)
1009     setFeature(X86::FEATURE_MOVBE);
1010 
1011   // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1012   // indicates that the AVX registers will be saved and restored on context
1013   // switch, then we have full AVX support.
1014   const unsigned AVXBits = (1 << 27) | (1 << 28);
1015   bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
1016                 ((EAX & 0x6) == 0x6);
1017 #if defined(__APPLE__)
1018   // Darwin lazily saves the AVX512 context on first use: trust that the OS will
1019   // save the AVX512 context if we use AVX512 instructions, even the bit is not
1020   // set right now.
1021   bool HasAVX512Save = true;
1022 #else
1023   // AVX512 requires additional context to be saved by the OS.
1024   bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
1025 #endif
1026 
1027   if (HasAVX)
1028     setFeature(X86::FEATURE_AVX);
1029 
1030   bool HasLeaf7 =
1031       MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1032 
1033   if (HasLeaf7 && ((EBX >> 3) & 1))
1034     setFeature(X86::FEATURE_BMI);
1035   if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
1036     setFeature(X86::FEATURE_AVX2);
1037   if (HasLeaf7 && ((EBX >> 8) & 1))
1038     setFeature(X86::FEATURE_BMI2);
1039   if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save)
1040     setFeature(X86::FEATURE_AVX512F);
1041   if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
1042     setFeature(X86::FEATURE_AVX512DQ);
1043   if (HasLeaf7 && ((EBX >> 19) & 1))
1044     setFeature(X86::FEATURE_ADX);
1045   if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
1046     setFeature(X86::FEATURE_AVX512IFMA);
1047   if (HasLeaf7 && ((EBX >> 23) & 1))
1048     setFeature(X86::FEATURE_CLFLUSHOPT);
1049   if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save)
1050     setFeature(X86::FEATURE_AVX512PF);
1051   if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save)
1052     setFeature(X86::FEATURE_AVX512ER);
1053   if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
1054     setFeature(X86::FEATURE_AVX512CD);
1055   if (HasLeaf7 && ((EBX >> 29) & 1))
1056     setFeature(X86::FEATURE_SHA);
1057   if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
1058     setFeature(X86::FEATURE_AVX512BW);
1059   if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
1060     setFeature(X86::FEATURE_AVX512VL);
1061 
1062   if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
1063     setFeature(X86::FEATURE_AVX512VBMI);
1064   if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)
1065     setFeature(X86::FEATURE_AVX512VBMI2);
1066   if (HasLeaf7 && ((ECX >> 8) & 1))
1067     setFeature(X86::FEATURE_GFNI);
1068   if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX)
1069     setFeature(X86::FEATURE_VPCLMULQDQ);
1070   if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)
1071     setFeature(X86::FEATURE_AVX512VNNI);
1072   if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)
1073     setFeature(X86::FEATURE_AVX512BITALG);
1074   if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
1075     setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
1076 
1077   if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
1078     setFeature(X86::FEATURE_AVX5124VNNIW);
1079   if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
1080     setFeature(X86::FEATURE_AVX5124FMAPS);
1081   if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save)
1082     setFeature(X86::FEATURE_AVX512VP2INTERSECT);
1083 
1084   bool HasLeaf7Subleaf1 =
1085       MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1086   if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save)
1087     setFeature(X86::FEATURE_AVX512BF16);
1088 
1089   unsigned MaxExtLevel;
1090   getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1091 
1092   bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1093                      !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1094   if (HasExtLeaf1 && ((ECX >> 6) & 1))
1095     setFeature(X86::FEATURE_SSE4_A);
1096   if (HasExtLeaf1 && ((ECX >> 11) & 1))
1097     setFeature(X86::FEATURE_XOP);
1098   if (HasExtLeaf1 && ((ECX >> 16) & 1))
1099     setFeature(X86::FEATURE_FMA4);
1100 
1101   if (HasExtLeaf1 && ((EDX >> 29) & 1))
1102     setFeature(X86::FEATURE_64BIT);
1103 }
1104 
1105 StringRef sys::getHostCPUName() {
1106   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1107   unsigned MaxLeaf, Vendor;
1108 
1109   if (!isCpuIdSupported())
1110     return "generic";
1111 
1112   if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1)
1113     return "generic";
1114   getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1115 
1116   unsigned Family = 0, Model = 0;
1117   unsigned Features[(X86::CPU_FEATURE_MAX + 31) / 32] = {0};
1118   detectX86FamilyModel(EAX, &Family, &Model);
1119   getAvailableFeatures(ECX, EDX, MaxLeaf, Features);
1120 
1121   // These aren't consumed in this file, but we try to keep some source code the
1122   // same or similar to compiler-rt.
1123   unsigned Type = 0;
1124   unsigned Subtype = 0;
1125 
1126   StringRef CPU;
1127 
1128   if (Vendor == SIG_INTEL) {
1129     CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &Type,
1130                                           &Subtype);
1131   } else if (Vendor == SIG_AMD) {
1132     CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type,
1133                                         &Subtype);
1134   }
1135 
1136   if (!CPU.empty())
1137     return CPU;
1138 
1139   return "generic";
1140 }
1141 
1142 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
1143 StringRef sys::getHostCPUName() {
1144   host_basic_info_data_t hostInfo;
1145   mach_msg_type_number_t infoCount;
1146 
1147   infoCount = HOST_BASIC_INFO_COUNT;
1148   mach_port_t hostPort = mach_host_self();
1149   host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1150             &infoCount);
1151   mach_port_deallocate(mach_task_self(), hostPort);
1152 
1153   if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1154     return "generic";
1155 
1156   switch (hostInfo.cpu_subtype) {
1157   case CPU_SUBTYPE_POWERPC_601:
1158     return "601";
1159   case CPU_SUBTYPE_POWERPC_602:
1160     return "602";
1161   case CPU_SUBTYPE_POWERPC_603:
1162     return "603";
1163   case CPU_SUBTYPE_POWERPC_603e:
1164     return "603e";
1165   case CPU_SUBTYPE_POWERPC_603ev:
1166     return "603ev";
1167   case CPU_SUBTYPE_POWERPC_604:
1168     return "604";
1169   case CPU_SUBTYPE_POWERPC_604e:
1170     return "604e";
1171   case CPU_SUBTYPE_POWERPC_620:
1172     return "620";
1173   case CPU_SUBTYPE_POWERPC_750:
1174     return "750";
1175   case CPU_SUBTYPE_POWERPC_7400:
1176     return "7400";
1177   case CPU_SUBTYPE_POWERPC_7450:
1178     return "7450";
1179   case CPU_SUBTYPE_POWERPC_970:
1180     return "970";
1181   default:;
1182   }
1183 
1184   return "generic";
1185 }
1186 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
1187 StringRef sys::getHostCPUName() {
1188   std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1189   StringRef Content = P ? P->getBuffer() : "";
1190   return detail::getHostCPUNameForPowerPC(Content);
1191 }
1192 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1193 StringRef sys::getHostCPUName() {
1194   std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1195   StringRef Content = P ? P->getBuffer() : "";
1196   return detail::getHostCPUNameForARM(Content);
1197 }
1198 #elif defined(__linux__) && defined(__s390x__)
1199 StringRef sys::getHostCPUName() {
1200   std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1201   StringRef Content = P ? P->getBuffer() : "";
1202   return detail::getHostCPUNameForS390x(Content);
1203 }
1204 #elif defined(__APPLE__) && defined(__aarch64__)
1205 StringRef sys::getHostCPUName() {
1206   return "cyclone";
1207 }
1208 #elif defined(__APPLE__) && defined(__arm__)
1209 StringRef sys::getHostCPUName() {
1210   host_basic_info_data_t hostInfo;
1211   mach_msg_type_number_t infoCount;
1212 
1213   infoCount = HOST_BASIC_INFO_COUNT;
1214   mach_port_t hostPort = mach_host_self();
1215   host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1216             &infoCount);
1217   mach_port_deallocate(mach_task_self(), hostPort);
1218 
1219   if (hostInfo.cpu_type != CPU_TYPE_ARM) {
1220     assert(false && "CPUType not equal to ARM should not be possible on ARM");
1221     return "generic";
1222   }
1223   switch (hostInfo.cpu_subtype) {
1224     case CPU_SUBTYPE_ARM_V7S:
1225       return "swift";
1226     default:;
1227     }
1228 
1229   return "generic";
1230 }
1231 #else
1232 StringRef sys::getHostCPUName() { return "generic"; }
1233 #endif
1234 
1235 #if defined(__linux__) && (defined(__i386__) || defined(__x86_64__))
1236 // On Linux, the number of physical cores can be computed from /proc/cpuinfo,
1237 // using the number of unique physical/core id pairs. The following
1238 // implementation reads the /proc/cpuinfo format on an x86_64 system.
1239 int computeHostNumPhysicalCores() {
1240   // Enabled represents the number of physical id/core id pairs with at least
1241   // one processor id enabled by the CPU affinity mask.
1242   cpu_set_t Affinity, Enabled;
1243   if (sched_getaffinity(0, sizeof(Affinity), &Affinity) != 0)
1244     return -1;
1245   CPU_ZERO(&Enabled);
1246 
1247   // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be
1248   // mmapped because it appears to have 0 size.
1249   llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text =
1250       llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
1251   if (std::error_code EC = Text.getError()) {
1252     llvm::errs() << "Can't read "
1253                  << "/proc/cpuinfo: " << EC.message() << "\n";
1254     return -1;
1255   }
1256   SmallVector<StringRef, 8> strs;
1257   (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1,
1258                              /*KeepEmpty=*/false);
1259   int CurProcessor = -1;
1260   int CurPhysicalId = -1;
1261   int CurSiblings = -1;
1262   int CurCoreId = -1;
1263   for (StringRef Line : strs) {
1264     std::pair<StringRef, StringRef> Data = Line.split(':');
1265     auto Name = Data.first.trim();
1266     auto Val = Data.second.trim();
1267     // These fields are available if the kernel is configured with CONFIG_SMP.
1268     if (Name == "processor")
1269       Val.getAsInteger(10, CurProcessor);
1270     else if (Name == "physical id")
1271       Val.getAsInteger(10, CurPhysicalId);
1272     else if (Name == "siblings")
1273       Val.getAsInteger(10, CurSiblings);
1274     else if (Name == "core id") {
1275       Val.getAsInteger(10, CurCoreId);
1276       // The processor id corresponds to an index into cpu_set_t.
1277       if (CPU_ISSET(CurProcessor, &Affinity))
1278         CPU_SET(CurPhysicalId * CurSiblings + CurCoreId, &Enabled);
1279     }
1280   }
1281   return CPU_COUNT(&Enabled);
1282 }
1283 #elif defined(__linux__) && defined(__powerpc__)
1284 int computeHostNumPhysicalCores() {
1285   cpu_set_t Affinity;
1286   if (sched_getaffinity(0, sizeof(Affinity), &Affinity) == 0)
1287     return CPU_COUNT(&Affinity);
1288 
1289   // The call to sched_getaffinity() may have failed because the Affinity
1290   // mask is too small for the number of CPU's on the system (i.e. the
1291   // system has more than 1024 CPUs). Allocate a mask large enough for
1292   // twice as many CPUs.
1293   cpu_set_t *DynAffinity;
1294   DynAffinity = CPU_ALLOC(2048);
1295   if (sched_getaffinity(0, CPU_ALLOC_SIZE(2048), DynAffinity) == 0) {
1296     int NumCPUs = CPU_COUNT(DynAffinity);
1297     CPU_FREE(DynAffinity);
1298     return NumCPUs;
1299   }
1300   return -1;
1301 }
1302 #elif defined(__linux__) && defined(__s390x__)
1303 int computeHostNumPhysicalCores() { return sysconf(_SC_NPROCESSORS_ONLN); }
1304 #elif defined(__APPLE__) && defined(__x86_64__)
1305 #include <sys/param.h>
1306 #include <sys/sysctl.h>
1307 
1308 // Gets the number of *physical cores* on the machine.
1309 int computeHostNumPhysicalCores() {
1310   uint32_t count;
1311   size_t len = sizeof(count);
1312   sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0);
1313   if (count < 1) {
1314     int nm[2];
1315     nm[0] = CTL_HW;
1316     nm[1] = HW_AVAILCPU;
1317     sysctl(nm, 2, &count, &len, NULL, 0);
1318     if (count < 1)
1319       return -1;
1320   }
1321   return count;
1322 }
1323 #elif defined(__MVS__)
1324 int computeHostNumPhysicalCores() {
1325   enum {
1326     // Byte offset of the pointer to the Communications Vector Table (CVT) in
1327     // the Prefixed Save Area (PSA). The table entry is a 31-bit pointer and
1328     // will be zero-extended to uintptr_t.
1329     FLCCVT = 16,
1330     // Byte offset of the pointer to the Common System Data Area (CSD) in the
1331     // CVT. The table entry is a 31-bit pointer and will be zero-extended to
1332     // uintptr_t.
1333     CVTCSD = 660,
1334     // Byte offset to the number of live CPs in the LPAR, stored as a signed
1335     // 32-bit value in the table.
1336     CSD_NUMBER_ONLINE_STANDARD_CPS = 264,
1337   };
1338   char *PSA = 0;
1339   char *CVT = reinterpret_cast<char *>(
1340       static_cast<uintptr_t>(reinterpret_cast<unsigned int &>(PSA[FLCCVT])));
1341   char *CSD = reinterpret_cast<char *>(
1342       static_cast<uintptr_t>(reinterpret_cast<unsigned int &>(CVT[CVTCSD])));
1343   return reinterpret_cast<int &>(CSD[CSD_NUMBER_ONLINE_STANDARD_CPS]);
1344 }
1345 #elif defined(_WIN32) && LLVM_ENABLE_THREADS != 0
1346 // Defined in llvm/lib/Support/Windows/Threading.inc
1347 int computeHostNumPhysicalCores();
1348 #else
1349 // On other systems, return -1 to indicate unknown.
1350 static int computeHostNumPhysicalCores() { return -1; }
1351 #endif
1352 
1353 int sys::getHostNumPhysicalCores() {
1354   static int NumCores = computeHostNumPhysicalCores();
1355   return NumCores;
1356 }
1357 
1358 #if defined(__i386__) || defined(_M_IX86) || \
1359     defined(__x86_64__) || defined(_M_X64)
1360 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1361   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1362   unsigned MaxLevel;
1363 
1364   if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1)
1365     return false;
1366 
1367   getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1368 
1369   Features["cx8"]    = (EDX >>  8) & 1;
1370   Features["cmov"]   = (EDX >> 15) & 1;
1371   Features["mmx"]    = (EDX >> 23) & 1;
1372   Features["fxsr"]   = (EDX >> 24) & 1;
1373   Features["sse"]    = (EDX >> 25) & 1;
1374   Features["sse2"]   = (EDX >> 26) & 1;
1375 
1376   Features["sse3"]   = (ECX >>  0) & 1;
1377   Features["pclmul"] = (ECX >>  1) & 1;
1378   Features["ssse3"]  = (ECX >>  9) & 1;
1379   Features["cx16"]   = (ECX >> 13) & 1;
1380   Features["sse4.1"] = (ECX >> 19) & 1;
1381   Features["sse4.2"] = (ECX >> 20) & 1;
1382   Features["movbe"]  = (ECX >> 22) & 1;
1383   Features["popcnt"] = (ECX >> 23) & 1;
1384   Features["aes"]    = (ECX >> 25) & 1;
1385   Features["rdrnd"]  = (ECX >> 30) & 1;
1386 
1387   // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1388   // indicates that the AVX registers will be saved and restored on context
1389   // switch, then we have full AVX support.
1390   bool HasXSave = ((ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX);
1391   bool HasAVXSave = HasXSave && ((ECX >> 28) & 1) && ((EAX & 0x6) == 0x6);
1392 #if defined(__APPLE__)
1393   // Darwin lazily saves the AVX512 context on first use: trust that the OS will
1394   // save the AVX512 context if we use AVX512 instructions, even the bit is not
1395   // set right now.
1396   bool HasAVX512Save = true;
1397 #else
1398   // AVX512 requires additional context to be saved by the OS.
1399   bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
1400 #endif
1401   // AMX requires additional context to be saved by the OS.
1402   const unsigned AMXBits = (1 << 17) | (1 << 18);
1403   bool HasAMXSave = HasXSave && ((EAX & AMXBits) == AMXBits);
1404 
1405   Features["avx"]   = HasAVXSave;
1406   Features["fma"]   = ((ECX >> 12) & 1) && HasAVXSave;
1407   // Only enable XSAVE if OS has enabled support for saving YMM state.
1408   Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave;
1409   Features["f16c"]  = ((ECX >> 29) & 1) && HasAVXSave;
1410 
1411   unsigned MaxExtLevel;
1412   getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1413 
1414   bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1415                      !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1416   Features["sahf"]   = HasExtLeaf1 && ((ECX >>  0) & 1);
1417   Features["lzcnt"]  = HasExtLeaf1 && ((ECX >>  5) & 1);
1418   Features["sse4a"]  = HasExtLeaf1 && ((ECX >>  6) & 1);
1419   Features["prfchw"] = HasExtLeaf1 && ((ECX >>  8) & 1);
1420   Features["xop"]    = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
1421   Features["lwp"]    = HasExtLeaf1 && ((ECX >> 15) & 1);
1422   Features["fma4"]   = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
1423   Features["tbm"]    = HasExtLeaf1 && ((ECX >> 21) & 1);
1424   Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
1425 
1426   Features["64bit"]  = HasExtLeaf1 && ((EDX >> 29) & 1);
1427 
1428   // Miscellaneous memory related features, detected by
1429   // using the 0x80000008 leaf of the CPUID instruction
1430   bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1431                      !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
1432   Features["clzero"]   = HasExtLeaf8 && ((EBX >> 0) & 1);
1433   Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1);
1434 
1435   bool HasLeaf7 =
1436       MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1437 
1438   Features["fsgsbase"]   = HasLeaf7 && ((EBX >>  0) & 1);
1439   Features["sgx"]        = HasLeaf7 && ((EBX >>  2) & 1);
1440   Features["bmi"]        = HasLeaf7 && ((EBX >>  3) & 1);
1441   // AVX2 is only supported if we have the OS save support from AVX.
1442   Features["avx2"]       = HasLeaf7 && ((EBX >>  5) & 1) && HasAVXSave;
1443   Features["bmi2"]       = HasLeaf7 && ((EBX >>  8) & 1);
1444   Features["invpcid"]    = HasLeaf7 && ((EBX >> 10) & 1);
1445   Features["rtm"]        = HasLeaf7 && ((EBX >> 11) & 1);
1446   // AVX512 is only supported if the OS supports the context save for it.
1447   Features["avx512f"]    = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
1448   Features["avx512dq"]   = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
1449   Features["rdseed"]     = HasLeaf7 && ((EBX >> 18) & 1);
1450   Features["adx"]        = HasLeaf7 && ((EBX >> 19) & 1);
1451   Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
1452   Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
1453   Features["clwb"]       = HasLeaf7 && ((EBX >> 24) & 1);
1454   Features["avx512pf"]   = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
1455   Features["avx512er"]   = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save;
1456   Features["avx512cd"]   = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
1457   Features["sha"]        = HasLeaf7 && ((EBX >> 29) & 1);
1458   Features["avx512bw"]   = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
1459   Features["avx512vl"]   = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
1460 
1461   Features["prefetchwt1"]     = HasLeaf7 && ((ECX >>  0) & 1);
1462   Features["avx512vbmi"]      = HasLeaf7 && ((ECX >>  1) & 1) && HasAVX512Save;
1463   Features["pku"]             = HasLeaf7 && ((ECX >>  4) & 1);
1464   Features["waitpkg"]         = HasLeaf7 && ((ECX >>  5) & 1);
1465   Features["avx512vbmi2"]     = HasLeaf7 && ((ECX >>  6) & 1) && HasAVX512Save;
1466   Features["shstk"]           = HasLeaf7 && ((ECX >>  7) & 1);
1467   Features["gfni"]            = HasLeaf7 && ((ECX >>  8) & 1);
1468   Features["vaes"]            = HasLeaf7 && ((ECX >>  9) & 1) && HasAVXSave;
1469   Features["vpclmulqdq"]      = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave;
1470   Features["avx512vnni"]      = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save;
1471   Features["avx512bitalg"]    = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save;
1472   Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;
1473   Features["rdpid"]           = HasLeaf7 && ((ECX >> 22) & 1);
1474   Features["kl"]              = HasLeaf7 && ((ECX >> 23) & 1); // key locker
1475   Features["cldemote"]        = HasLeaf7 && ((ECX >> 25) & 1);
1476   Features["movdiri"]         = HasLeaf7 && ((ECX >> 27) & 1);
1477   Features["movdir64b"]       = HasLeaf7 && ((ECX >> 28) & 1);
1478   Features["enqcmd"]          = HasLeaf7 && ((ECX >> 29) & 1);
1479 
1480   Features["uintr"]           = HasLeaf7 && ((EDX >> 5) & 1);
1481   Features["avx512vp2intersect"] =
1482       HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save;
1483   Features["serialize"]       = HasLeaf7 && ((EDX >> 14) & 1);
1484   Features["tsxldtrk"]        = HasLeaf7 && ((EDX >> 16) & 1);
1485   // There are two CPUID leafs which information associated with the pconfig
1486   // instruction:
1487   // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th
1488   // bit of EDX), while the EAX=0x1b leaf returns information on the
1489   // availability of specific pconfig leafs.
1490   // The target feature here only refers to the the first of these two.
1491   // Users might need to check for the availability of specific pconfig
1492   // leaves using cpuid, since that information is ignored while
1493   // detecting features using the "-march=native" flag.
1494   // For more info, see X86 ISA docs.
1495   Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1);
1496   Features["amx-bf16"]   = HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave;
1497   Features["amx-tile"]   = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave;
1498   Features["amx-int8"]   = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave;
1499   bool HasLeaf7Subleaf1 =
1500       MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1501   Features["avxvnni"]    = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave;
1502   Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;
1503   Features["hreset"]     = HasLeaf7Subleaf1 && ((EAX >> 22) & 1);
1504 
1505   bool HasLeafD = MaxLevel >= 0xd &&
1506                   !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1507 
1508   // Only enable XSAVE if OS has enabled support for saving YMM state.
1509   Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave;
1510   Features["xsavec"]   = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave;
1511   Features["xsaves"]   = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave;
1512 
1513   bool HasLeaf14 = MaxLevel >= 0x14 &&
1514                   !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
1515 
1516   Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1);
1517 
1518   bool HasLeaf19 =
1519       MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX);
1520   Features["widekl"] = HasLeaf7 && HasLeaf19 && ((EBX >> 2) & 1);
1521 
1522   return true;
1523 }
1524 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1525 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1526   std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1527   if (!P)
1528     return false;
1529 
1530   SmallVector<StringRef, 32> Lines;
1531   P->getBuffer().split(Lines, "\n");
1532 
1533   SmallVector<StringRef, 32> CPUFeatures;
1534 
1535   // Look for the CPU features.
1536   for (unsigned I = 0, E = Lines.size(); I != E; ++I)
1537     if (Lines[I].startswith("Features")) {
1538       Lines[I].split(CPUFeatures, ' ');
1539       break;
1540     }
1541 
1542 #if defined(__aarch64__)
1543   // Keep track of which crypto features we have seen
1544   enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1545   uint32_t crypto = 0;
1546 #endif
1547 
1548   for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
1549     StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
1550 #if defined(__aarch64__)
1551                                    .Case("asimd", "neon")
1552                                    .Case("fp", "fp-armv8")
1553                                    .Case("crc32", "crc")
1554 #else
1555                                    .Case("half", "fp16")
1556                                    .Case("neon", "neon")
1557                                    .Case("vfpv3", "vfp3")
1558                                    .Case("vfpv3d16", "d16")
1559                                    .Case("vfpv4", "vfp4")
1560                                    .Case("idiva", "hwdiv-arm")
1561                                    .Case("idivt", "hwdiv")
1562 #endif
1563                                    .Default("");
1564 
1565 #if defined(__aarch64__)
1566     // We need to check crypto separately since we need all of the crypto
1567     // extensions to enable the subtarget feature
1568     if (CPUFeatures[I] == "aes")
1569       crypto |= CAP_AES;
1570     else if (CPUFeatures[I] == "pmull")
1571       crypto |= CAP_PMULL;
1572     else if (CPUFeatures[I] == "sha1")
1573       crypto |= CAP_SHA1;
1574     else if (CPUFeatures[I] == "sha2")
1575       crypto |= CAP_SHA2;
1576 #endif
1577 
1578     if (LLVMFeatureStr != "")
1579       Features[LLVMFeatureStr] = true;
1580   }
1581 
1582 #if defined(__aarch64__)
1583   // If we have all crypto bits we can add the feature
1584   if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1585     Features["crypto"] = true;
1586 #endif
1587 
1588   return true;
1589 }
1590 #elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64))
1591 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1592   if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE))
1593     Features["neon"] = true;
1594   if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE))
1595     Features["crc"] = true;
1596   if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE))
1597     Features["crypto"] = true;
1598 
1599   return true;
1600 }
1601 #else
1602 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; }
1603 #endif
1604 
1605 std::string sys::getProcessTriple() {
1606   std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
1607   Triple PT(Triple::normalize(TargetTripleString));
1608 
1609   if (sizeof(void *) == 8 && PT.isArch32Bit())
1610     PT = PT.get64BitArchVariant();
1611   if (sizeof(void *) == 4 && PT.isArch64Bit())
1612     PT = PT.get32BitArchVariant();
1613 
1614   return PT.str();
1615 }
1616