1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the operating system Host concept. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Support/Host.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringRef.h" 17 #include "llvm/ADT/StringSwitch.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/Config/config.h" 20 #include "llvm/Support/Debug.h" 21 #include "llvm/Support/FileSystem.h" 22 #include "llvm/Support/raw_ostream.h" 23 #include <string.h> 24 25 // Include the platform-specific parts of this class. 26 #ifdef LLVM_ON_UNIX 27 #include "Unix/Host.inc" 28 #endif 29 #ifdef LLVM_ON_WIN32 30 #include "Windows/Host.inc" 31 #endif 32 #ifdef _MSC_VER 33 #include <intrin.h> 34 #endif 35 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 36 #include <mach/host_info.h> 37 #include <mach/mach.h> 38 #include <mach/mach_host.h> 39 #include <mach/machine.h> 40 #endif 41 42 #define DEBUG_TYPE "host-detection" 43 44 //===----------------------------------------------------------------------===// 45 // 46 // Implementations of the CPU detection routines 47 // 48 //===----------------------------------------------------------------------===// 49 50 using namespace llvm; 51 52 #if defined(__linux__) 53 static ssize_t LLVM_ATTRIBUTE_UNUSED readCpuInfo(void *Buf, size_t Size) { 54 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting 55 // memory buffer because the 'file' has 0 size (it can be read from only 56 // as a stream). 57 58 int FD; 59 std::error_code EC = sys::fs::openFileForRead("/proc/cpuinfo", FD); 60 if (EC) { 61 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << EC.message() << "\n"); 62 return -1; 63 } 64 int Ret = read(FD, Buf, Size); 65 int CloseStatus = close(FD); 66 if (CloseStatus) 67 return -1; 68 return Ret; 69 } 70 #endif 71 72 #if defined(i386) || defined(__i386__) || defined(__x86__) || \ 73 defined(_M_IX86) || defined(__x86_64__) || defined(_M_AMD64) || \ 74 defined(_M_X64) 75 76 enum VendorSignatures { 77 SIG_INTEL = 0x756e6547 /* Genu */, 78 SIG_AMD = 0x68747541 /* Auth */ 79 }; 80 81 enum ProcessorVendors { 82 VENDOR_INTEL = 1, 83 VENDOR_AMD, 84 VENDOR_OTHER, 85 VENDOR_MAX 86 }; 87 88 enum ProcessorTypes { 89 INTEL_ATOM = 1, 90 INTEL_CORE2, 91 INTEL_COREI7, 92 AMDFAM10H, 93 AMDFAM15H, 94 INTEL_i386, 95 INTEL_i486, 96 INTEL_PENTIUM, 97 INTEL_PENTIUM_PRO, 98 INTEL_PENTIUM_II, 99 INTEL_PENTIUM_III, 100 INTEL_PENTIUM_IV, 101 INTEL_PENTIUM_M, 102 INTEL_CORE_DUO, 103 INTEL_XEONPHI, 104 INTEL_X86_64, 105 INTEL_NOCONA, 106 INTEL_PRESCOTT, 107 AMD_i486, 108 AMDPENTIUM, 109 AMDATHLON, 110 AMDFAM14H, 111 AMDFAM16H, 112 CPU_TYPE_MAX 113 }; 114 115 enum ProcessorSubtypes { 116 INTEL_COREI7_NEHALEM = 1, 117 INTEL_COREI7_WESTMERE, 118 INTEL_COREI7_SANDYBRIDGE, 119 AMDFAM10H_BARCELONA, 120 AMDFAM10H_SHANGHAI, 121 AMDFAM10H_ISTANBUL, 122 AMDFAM15H_BDVER1, 123 AMDFAM15H_BDVER2, 124 INTEL_PENTIUM_MMX, 125 INTEL_CORE2_65, 126 INTEL_CORE2_45, 127 INTEL_COREI7_IVYBRIDGE, 128 INTEL_COREI7_HASWELL, 129 INTEL_COREI7_BROADWELL, 130 INTEL_COREI7_SKYLAKE, 131 INTEL_COREI7_SKYLAKE_AVX512, 132 INTEL_ATOM_BONNELL, 133 INTEL_ATOM_SILVERMONT, 134 INTEL_KNIGHTS_LANDING, 135 AMDPENTIUM_K6, 136 AMDPENTIUM_K62, 137 AMDPENTIUM_K63, 138 AMDPENTIUM_GEODE, 139 AMDATHLON_TBIRD, 140 AMDATHLON_MP, 141 AMDATHLON_XP, 142 AMDATHLON_K8SSE3, 143 AMDATHLON_OPTERON, 144 AMDATHLON_FX, 145 AMDATHLON_64, 146 AMD_BTVER1, 147 AMD_BTVER2, 148 AMDFAM15H_BDVER3, 149 AMDFAM15H_BDVER4, 150 CPU_SUBTYPE_MAX 151 }; 152 153 enum ProcessorFeatures { 154 FEATURE_CMOV = 0, 155 FEATURE_MMX, 156 FEATURE_POPCNT, 157 FEATURE_SSE, 158 FEATURE_SSE2, 159 FEATURE_SSE3, 160 FEATURE_SSSE3, 161 FEATURE_SSE4_1, 162 FEATURE_SSE4_2, 163 FEATURE_AVX, 164 FEATURE_AVX2, 165 FEATURE_AVX512, 166 FEATURE_AVX512SAVE, 167 FEATURE_MOVBE, 168 FEATURE_ADX, 169 FEATURE_EM64T 170 }; 171 172 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 173 /// the specified arguments. If we can't run cpuid on the host, return true. 174 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 175 unsigned *rECX, unsigned *rEDX) { 176 #if defined(__GNUC__) || defined(__clang__) 177 #if defined(__x86_64__) || defined(_M_AMD64) || defined(_M_X64) 178 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. 179 asm("movq\t%%rbx, %%rsi\n\t" 180 "cpuid\n\t" 181 "xchgq\t%%rbx, %%rsi\n\t" 182 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 183 : "a"(value)); 184 return false; 185 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) 186 asm("movl\t%%ebx, %%esi\n\t" 187 "cpuid\n\t" 188 "xchgl\t%%ebx, %%esi\n\t" 189 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 190 : "a"(value)); 191 return false; 192 // pedantic #else returns to appease -Wunreachable-code (so we don't generate 193 // postprocessed code that looks like "return true; return false;") 194 #else 195 return true; 196 #endif 197 #elif defined(_MSC_VER) 198 // The MSVC intrinsic is portable across x86 and x64. 199 int registers[4]; 200 __cpuid(registers, value); 201 *rEAX = registers[0]; 202 *rEBX = registers[1]; 203 *rECX = registers[2]; 204 *rEDX = registers[3]; 205 return false; 206 #else 207 return true; 208 #endif 209 } 210 211 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 212 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 213 /// return true. 214 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 215 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 216 unsigned *rEDX) { 217 #if defined(__x86_64__) || defined(_M_AMD64) || defined(_M_X64) 218 #if defined(__GNUC__) 219 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. 220 asm("movq\t%%rbx, %%rsi\n\t" 221 "cpuid\n\t" 222 "xchgq\t%%rbx, %%rsi\n\t" 223 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 224 : "a"(value), "c"(subleaf)); 225 return false; 226 #elif defined(_MSC_VER) 227 int registers[4]; 228 __cpuidex(registers, value, subleaf); 229 *rEAX = registers[0]; 230 *rEBX = registers[1]; 231 *rECX = registers[2]; 232 *rEDX = registers[3]; 233 return false; 234 #else 235 return true; 236 #endif 237 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) 238 #if defined(__GNUC__) 239 asm("movl\t%%ebx, %%esi\n\t" 240 "cpuid\n\t" 241 "xchgl\t%%ebx, %%esi\n\t" 242 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 243 : "a"(value), "c"(subleaf)); 244 return false; 245 #elif defined(_MSC_VER) 246 __asm { 247 mov eax,value 248 mov ecx,subleaf 249 cpuid 250 mov esi,rEAX 251 mov dword ptr [esi],eax 252 mov esi,rEBX 253 mov dword ptr [esi],ebx 254 mov esi,rECX 255 mov dword ptr [esi],ecx 256 mov esi,rEDX 257 mov dword ptr [esi],edx 258 } 259 return false; 260 #else 261 return true; 262 #endif 263 #else 264 return true; 265 #endif 266 } 267 268 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 269 #if defined(__GNUC__) 270 // Check xgetbv; this uses a .byte sequence instead of the instruction 271 // directly because older assemblers do not include support for xgetbv and 272 // there is no easy way to conditionally compile based on the assembler used. 273 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 274 return false; 275 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 276 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 277 *rEAX = Result; 278 *rEDX = Result >> 32; 279 return false; 280 #else 281 return true; 282 #endif 283 } 284 285 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 286 unsigned *Model) { 287 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 288 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 289 if (*Family == 6 || *Family == 0xf) { 290 if (*Family == 0xf) 291 // Examine extended family ID if family ID is F. 292 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 293 // Examine extended model ID if family ID is 6 or F. 294 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 295 } 296 } 297 298 static void 299 getIntelProcessorTypeAndSubtype(unsigned int Family, unsigned int Model, 300 unsigned int Brand_id, unsigned int Features, 301 unsigned *Type, unsigned *Subtype) { 302 if (Brand_id != 0) 303 return; 304 switch (Family) { 305 case 3: 306 *Type = INTEL_i386; 307 break; 308 case 4: 309 switch (Model) { 310 case 0: // Intel486 DX processors 311 case 1: // Intel486 DX processors 312 case 2: // Intel486 SX processors 313 case 3: // Intel487 processors, IntelDX2 OverDrive processors, 314 // IntelDX2 processors 315 case 4: // Intel486 SL processor 316 case 5: // IntelSX2 processors 317 case 7: // Write-Back Enhanced IntelDX2 processors 318 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors 319 default: 320 *Type = INTEL_i486; 321 break; 322 } 323 case 5: 324 switch (Model) { 325 case 1: // Pentium OverDrive processor for Pentium processor (60, 66), 326 // Pentium processors (60, 66) 327 case 2: // Pentium OverDrive processor for Pentium processor (75, 90, 328 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133, 329 // 150, 166, 200) 330 case 3: // Pentium OverDrive processors for Intel486 processor-based 331 // systems 332 *Type = INTEL_PENTIUM; 333 break; 334 case 4: // Pentium OverDrive processor with MMX technology for Pentium 335 // processor (75, 90, 100, 120, 133), Pentium processor with 336 // MMX technology (166, 200) 337 *Type = INTEL_PENTIUM; 338 *Subtype = INTEL_PENTIUM_MMX; 339 break; 340 default: 341 *Type = INTEL_PENTIUM; 342 break; 343 } 344 case 6: 345 switch (Model) { 346 case 0x01: // Pentium Pro processor 347 *Type = INTEL_PENTIUM_PRO; 348 break; 349 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 350 // model 03 351 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 352 // model 05, and Intel Celeron processor, model 05 353 case 0x06: // Celeron processor, model 06 354 *Type = INTEL_PENTIUM_II; 355 break; 356 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 357 // processor, model 07 358 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 359 // model 08, and Celeron processor, model 08 360 case 0x0a: // Pentium III Xeon processor, model 0Ah 361 case 0x0b: // Pentium III processor, model 0Bh 362 *Type = INTEL_PENTIUM_III; 363 break; 364 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 365 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 366 // 0Dh. All processors are manufactured using the 90 nm process. 367 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 368 // Integrated Processor with Intel QuickAssist Technology 369 *Type = INTEL_PENTIUM_M; 370 break; 371 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 372 // 0Eh. All processors are manufactured using the 65 nm process. 373 *Type = INTEL_CORE_DUO; 374 break; // yonah 375 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 376 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 377 // mobile processor, Intel Core 2 Extreme processor, Intel 378 // Pentium Dual-Core processor, Intel Xeon processor, model 379 // 0Fh. All processors are manufactured using the 65 nm process. 380 case 0x16: // Intel Celeron processor model 16h. All processors are 381 // manufactured using the 65 nm process 382 *Type = INTEL_CORE2; // "core2" 383 *Subtype = INTEL_CORE2_65; 384 break; 385 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 386 // 17h. All processors are manufactured using the 45 nm process. 387 // 388 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 389 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 390 // the 45 nm process. 391 *Type = INTEL_CORE2; // "penryn" 392 *Subtype = INTEL_CORE2_45; 393 break; 394 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 395 // processors are manufactured using the 45 nm process. 396 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 397 // As found in a Summer 2010 model iMac. 398 case 0x1f: 399 case 0x2e: // Nehalem EX 400 *Type = INTEL_COREI7; // "nehalem" 401 *Subtype = INTEL_COREI7_NEHALEM; 402 break; 403 case 0x25: // Intel Core i7, laptop version. 404 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 405 // processors are manufactured using the 32 nm process. 406 case 0x2f: // Westmere EX 407 *Type = INTEL_COREI7; // "westmere" 408 *Subtype = INTEL_COREI7_WESTMERE; 409 break; 410 case 0x2a: // Intel Core i7 processor. All processors are manufactured 411 // using the 32 nm process. 412 case 0x2d: 413 *Type = INTEL_COREI7; //"sandybridge" 414 *Subtype = INTEL_COREI7_SANDYBRIDGE; 415 break; 416 case 0x3a: 417 case 0x3e: // Ivy Bridge EP 418 *Type = INTEL_COREI7; // "ivybridge" 419 *Subtype = INTEL_COREI7_IVYBRIDGE; 420 break; 421 422 // Haswell: 423 case 0x3c: 424 case 0x3f: 425 case 0x45: 426 case 0x46: 427 *Type = INTEL_COREI7; // "haswell" 428 *Subtype = INTEL_COREI7_HASWELL; 429 break; 430 431 // Broadwell: 432 case 0x3d: 433 case 0x47: 434 case 0x4f: 435 case 0x56: 436 *Type = INTEL_COREI7; // "broadwell" 437 *Subtype = INTEL_COREI7_BROADWELL; 438 break; 439 440 // Skylake: 441 case 0x4e: 442 *Type = INTEL_COREI7; // "skylake-avx512" 443 *Subtype = INTEL_COREI7_SKYLAKE_AVX512; 444 break; 445 case 0x5e: 446 *Type = INTEL_COREI7; // "skylake" 447 *Subtype = INTEL_COREI7_SKYLAKE; 448 break; 449 450 case 0x1c: // Most 45 nm Intel Atom processors 451 case 0x26: // 45 nm Atom Lincroft 452 case 0x27: // 32 nm Atom Medfield 453 case 0x35: // 32 nm Atom Midview 454 case 0x36: // 32 nm Atom Midview 455 *Type = INTEL_ATOM; 456 *Subtype = INTEL_ATOM_BONNELL; 457 break; // "bonnell" 458 459 // Atom Silvermont codes from the Intel software optimization guide. 460 case 0x37: 461 case 0x4a: 462 case 0x4d: 463 case 0x5a: 464 case 0x5d: 465 case 0x4c: // really airmont 466 *Type = INTEL_ATOM; 467 *Subtype = INTEL_ATOM_SILVERMONT; 468 break; // "silvermont" 469 470 case 0x57: 471 *Type = INTEL_XEONPHI; // knl 472 *Subtype = INTEL_KNIGHTS_LANDING; 473 break; 474 475 default: // Unknown family 6 CPU, try to guess. 476 if (Features & (1 << FEATURE_AVX512)) { 477 *Type = INTEL_XEONPHI; // knl 478 *Subtype = INTEL_KNIGHTS_LANDING; 479 break; 480 } 481 if (Features & (1 << FEATURE_ADX)) { 482 *Type = INTEL_COREI7; 483 *Subtype = INTEL_COREI7_BROADWELL; 484 break; 485 } 486 if (Features & (1 << FEATURE_AVX2)) { 487 *Type = INTEL_COREI7; 488 *Subtype = INTEL_COREI7_HASWELL; 489 break; 490 } 491 if (Features & (1 << FEATURE_AVX)) { 492 *Type = INTEL_COREI7; 493 *Subtype = INTEL_COREI7_SANDYBRIDGE; 494 break; 495 } 496 if (Features & (1 << FEATURE_SSE4_2)) { 497 if (Features & (1 << FEATURE_MOVBE)) { 498 *Type = INTEL_ATOM; 499 *Subtype = INTEL_ATOM_SILVERMONT; 500 } else { 501 *Type = INTEL_COREI7; 502 *Subtype = INTEL_COREI7_NEHALEM; 503 } 504 break; 505 } 506 if (Features & (1 << FEATURE_SSE4_1)) { 507 *Type = INTEL_CORE2; // "penryn" 508 *Subtype = INTEL_CORE2_45; 509 break; 510 } 511 if (Features & (1 << FEATURE_SSSE3)) { 512 if (Features & (1 << FEATURE_MOVBE)) { 513 *Type = INTEL_ATOM; 514 *Subtype = INTEL_ATOM_BONNELL; // "bonnell" 515 } else { 516 *Type = INTEL_CORE2; // "core2" 517 *Subtype = INTEL_CORE2_65; 518 } 519 break; 520 } 521 if (Features & (1 << FEATURE_EM64T)) { 522 *Type = INTEL_X86_64; 523 break; // x86-64 524 } 525 if (Features & (1 << FEATURE_SSE2)) { 526 *Type = INTEL_PENTIUM_M; 527 break; 528 } 529 if (Features & (1 << FEATURE_SSE)) { 530 *Type = INTEL_PENTIUM_III; 531 break; 532 } 533 if (Features & (1 << FEATURE_MMX)) { 534 *Type = INTEL_PENTIUM_II; 535 break; 536 } 537 *Type = INTEL_PENTIUM_PRO; 538 break; 539 } 540 case 15: { 541 switch (Model) { 542 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are 543 // model 00h and manufactured using the 0.18 micron process. 544 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon 545 // processor MP, and Intel Celeron processor. All processors are 546 // model 01h and manufactured using the 0.18 micron process. 547 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M, 548 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron 549 // processor, and Mobile Intel Celeron processor. All processors 550 // are model 02h and manufactured using the 0.13 micron process. 551 *Type = 552 ((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV); 553 break; 554 555 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D 556 // processor. All processors are model 03h and manufactured using 557 // the 90 nm process. 558 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition, 559 // Pentium D processor, Intel Xeon processor, Intel Xeon 560 // processor MP, Intel Celeron D processor. All processors are 561 // model 04h and manufactured using the 90 nm process. 562 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor 563 // Extreme Edition, Intel Xeon processor, Intel Xeon processor 564 // MP, Intel Celeron D processor. All processors are model 06h 565 // and manufactured using the 65 nm process. 566 *Type = 567 ((Features & (1 << FEATURE_EM64T)) ? INTEL_NOCONA : INTEL_PRESCOTT); 568 break; 569 570 default: 571 *Type = 572 ((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV); 573 break; 574 } 575 } 576 default: 577 break; /*"generic"*/ 578 } 579 } 580 581 static void getAMDProcessorTypeAndSubtype(unsigned int Family, 582 unsigned int Model, 583 unsigned int Features, 584 unsigned *Type, 585 unsigned *Subtype) { 586 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 587 // appears to be no way to generate the wide variety of AMD-specific targets 588 // from the information returned from CPUID. 589 switch (Family) { 590 case 4: 591 *Type = AMD_i486; 592 case 5: 593 *Type = AMDPENTIUM; 594 switch (Model) { 595 case 6: 596 case 7: 597 *Subtype = AMDPENTIUM_K6; 598 break; // "k6" 599 case 8: 600 *Subtype = AMDPENTIUM_K62; 601 break; // "k6-2" 602 case 9: 603 case 13: 604 *Subtype = AMDPENTIUM_K63; 605 break; // "k6-3" 606 case 10: 607 *Subtype = AMDPENTIUM_GEODE; 608 break; // "geode" 609 default: 610 break; 611 } 612 case 6: 613 *Type = AMDATHLON; 614 switch (Model) { 615 case 4: 616 *Subtype = AMDATHLON_TBIRD; 617 break; // "athlon-tbird" 618 case 6: 619 case 7: 620 case 8: 621 *Subtype = AMDATHLON_MP; 622 break; // "athlon-mp" 623 case 10: 624 *Subtype = AMDATHLON_XP; 625 break; // "athlon-xp" 626 default: 627 break; 628 } 629 case 15: 630 *Type = AMDATHLON; 631 if (Features & (1 << FEATURE_SSE3)) { 632 *Subtype = AMDATHLON_K8SSE3; 633 break; // "k8-sse3" 634 } 635 switch (Model) { 636 case 1: 637 *Subtype = AMDATHLON_OPTERON; 638 break; // "opteron" 639 case 5: 640 *Subtype = AMDATHLON_FX; 641 break; // "athlon-fx"; also opteron 642 default: 643 *Subtype = AMDATHLON_64; 644 break; // "athlon64" 645 } 646 case 16: 647 *Type = AMDFAM10H; // "amdfam10" 648 switch (Model) { 649 case 2: 650 *Subtype = AMDFAM10H_BARCELONA; 651 break; 652 case 4: 653 *Subtype = AMDFAM10H_SHANGHAI; 654 break; 655 case 8: 656 *Subtype = AMDFAM10H_ISTANBUL; 657 break; 658 default: 659 break; 660 } 661 case 20: 662 *Type = AMDFAM14H; 663 *Subtype = AMD_BTVER1; 664 break; // "btver1"; 665 case 21: 666 *Type = AMDFAM15H; 667 if (!(Features & 668 (1 << FEATURE_AVX))) { // If no AVX support, provide a sane fallback. 669 *Subtype = AMD_BTVER1; 670 break; // "btver1" 671 } 672 if (Model >= 0x50 && Model <= 0x6f) { 673 *Subtype = AMDFAM15H_BDVER4; 674 break; // "bdver4"; 50h-6Fh: Excavator 675 } 676 if (Model >= 0x30 && Model <= 0x3f) { 677 *Subtype = AMDFAM15H_BDVER3; 678 break; // "bdver3"; 30h-3Fh: Steamroller 679 } 680 if (Model >= 0x10 && Model <= 0x1f) { 681 *Subtype = AMDFAM15H_BDVER2; 682 break; // "bdver2"; 10h-1Fh: Piledriver 683 } 684 if (Model <= 0x0f) { 685 *Subtype = AMDFAM15H_BDVER1; 686 break; // "bdver1"; 00h-0Fh: Bulldozer 687 } 688 break; 689 case 22: 690 *Type = AMDFAM16H; 691 if (!(Features & 692 (1 << FEATURE_AVX))) { // If no AVX support provide a sane fallback. 693 *Subtype = AMD_BTVER1; 694 break; // "btver1"; 695 } 696 *Subtype = AMD_BTVER2; 697 break; // "btver2" 698 default: 699 break; // "generic" 700 } 701 } 702 703 unsigned getAvailableFeatures(unsigned int ECX, unsigned int EDX, 704 unsigned MaxLeaf) { 705 unsigned Features = 0; 706 unsigned int EAX, EBX; 707 Features |= (((EDX >> 23) & 1) << FEATURE_MMX); 708 Features |= (((EDX >> 25) & 1) << FEATURE_SSE); 709 Features |= (((EDX >> 26) & 1) << FEATURE_SSE2); 710 Features |= (((ECX >> 0) & 1) << FEATURE_SSE3); 711 Features |= (((ECX >> 9) & 1) << FEATURE_SSSE3); 712 Features |= (((ECX >> 19) & 1) << FEATURE_SSE4_1); 713 Features |= (((ECX >> 20) & 1) << FEATURE_SSE4_2); 714 Features |= (((ECX >> 22) & 1) << FEATURE_MOVBE); 715 716 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 717 // indicates that the AVX registers will be saved and restored on context 718 // switch, then we have full AVX support. 719 const unsigned AVXBits = (1 << 27) | (1 << 28); 720 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 721 ((EAX & 0x6) == 0x6); 722 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 723 bool HasLeaf7 = 724 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 725 bool HasADX = HasLeaf7 && ((EBX >> 19) & 1); 726 bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20); 727 bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1); 728 Features |= (HasAVX << FEATURE_AVX); 729 Features |= (HasAVX2 << FEATURE_AVX2); 730 Features |= (HasAVX512 << FEATURE_AVX512); 731 Features |= (HasAVX512Save << FEATURE_AVX512SAVE); 732 Features |= (HasADX << FEATURE_ADX); 733 734 getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 735 Features |= (((EDX >> 29) & 0x1) << FEATURE_EM64T); 736 return Features; 737 } 738 739 StringRef sys::getHostCPUName() { 740 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 741 unsigned MaxLeaf, Vendor; 742 743 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX)) 744 return "generic"; 745 if (getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX)) 746 return "generic"; 747 748 unsigned Brand_id = EBX & 0xff; 749 unsigned Family = 0, Model = 0; 750 unsigned Features = 0; 751 detectX86FamilyModel(EAX, &Family, &Model); 752 Features = getAvailableFeatures(ECX, EDX, MaxLeaf); 753 754 unsigned Type; 755 unsigned Subtype; 756 757 if (Vendor == SIG_INTEL) { 758 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, &Type, 759 &Subtype); 760 switch (Type) { 761 case INTEL_i386: 762 return "i386"; 763 case INTEL_i486: 764 return "i486"; 765 case INTEL_PENTIUM: 766 if (Subtype == INTEL_PENTIUM_MMX) 767 return "pentium-mmx"; 768 return "pentium"; 769 case INTEL_PENTIUM_PRO: 770 return "pentiumpro"; 771 case INTEL_PENTIUM_II: 772 return "pentium2"; 773 case INTEL_PENTIUM_III: 774 return "pentium3"; 775 case INTEL_PENTIUM_IV: 776 return "pentium4"; 777 case INTEL_PENTIUM_M: 778 return "pentium-m"; 779 case INTEL_CORE_DUO: 780 return "yonah"; 781 case INTEL_CORE2: 782 switch (Subtype) { 783 case INTEL_CORE2_65: 784 return "core2"; 785 case INTEL_CORE2_45: 786 return "penryn"; 787 default: 788 return "core2"; 789 } 790 case INTEL_COREI7: 791 switch (Subtype) { 792 case INTEL_COREI7_NEHALEM: 793 return "nehalem"; 794 case INTEL_COREI7_WESTMERE: 795 return "westmere"; 796 case INTEL_COREI7_SANDYBRIDGE: 797 return "sandybridge"; 798 case INTEL_COREI7_IVYBRIDGE: 799 return "ivybridge"; 800 case INTEL_COREI7_HASWELL: 801 return "haswell"; 802 case INTEL_COREI7_BROADWELL: 803 return "broadwell"; 804 case INTEL_COREI7_SKYLAKE: 805 return "skylake"; 806 case INTEL_COREI7_SKYLAKE_AVX512: 807 return "skylake-avx512"; 808 default: 809 return "corei7"; 810 } 811 case INTEL_ATOM: 812 switch (Subtype) { 813 case INTEL_ATOM_BONNELL: 814 return "bonnell"; 815 case INTEL_ATOM_SILVERMONT: 816 return "silvermont"; 817 default: 818 return "atom"; 819 } 820 case INTEL_XEONPHI: 821 return "knl"; /*update for more variants added*/ 822 case INTEL_X86_64: 823 return "x86-64"; 824 case INTEL_NOCONA: 825 return "nocona"; 826 case INTEL_PRESCOTT: 827 return "prescott"; 828 default: 829 return "generic"; 830 } 831 } else if (Vendor == SIG_AMD) { 832 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 833 switch (Type) { 834 case AMD_i486: 835 return "i486"; 836 case AMDPENTIUM: 837 switch (Subtype) { 838 case AMDPENTIUM_K6: 839 return "k6"; 840 case AMDPENTIUM_K62: 841 return "k6-2"; 842 case AMDPENTIUM_K63: 843 return "k6-3"; 844 case AMDPENTIUM_GEODE: 845 return "geode"; 846 default: 847 return "pentium"; 848 } 849 case AMDATHLON: 850 switch (Subtype) { 851 case AMDATHLON_TBIRD: 852 return "athlon-tbird"; 853 case AMDATHLON_MP: 854 return "athlon-mp"; 855 case AMDATHLON_XP: 856 return "athlon-xp"; 857 case AMDATHLON_K8SSE3: 858 return "k8-sse3"; 859 case AMDATHLON_OPTERON: 860 return "opteron"; 861 case AMDATHLON_FX: 862 return "athlon-fx"; 863 case AMDATHLON_64: 864 return "athlon64"; 865 default: 866 return "athlon"; 867 } 868 case AMDFAM10H: 869 switch (Subtype) { 870 case AMDFAM10H_BARCELONA: 871 return "amdfam10-barcelona"; 872 case AMDFAM10H_SHANGHAI: 873 return "amdfam10-shanghai"; 874 case AMDFAM10H_ISTANBUL: 875 return "amdfam10-istanbul"; 876 default: 877 return "amdfam10"; 878 } 879 case AMDFAM14H: 880 return "btver1"; 881 case AMDFAM15H: 882 switch (Subtype) { 883 case AMDFAM15H_BDVER1: 884 return "bdver1"; 885 case AMDFAM15H_BDVER2: 886 return "bdver2"; 887 case AMDFAM15H_BDVER3: 888 return "bdver3"; 889 case AMDFAM15H_BDVER4: 890 return "bdver4"; 891 case AMD_BTVER1: 892 return "btver1"; 893 default: 894 return "amdfam15"; 895 } 896 case AMDFAM16H: 897 switch (Subtype) { 898 case AMD_BTVER1: 899 return "btver1"; 900 case AMD_BTVER2: 901 return "btver2"; 902 default: 903 return "amdfam16"; 904 } 905 default: 906 return "generic"; 907 } 908 } 909 return "generic"; 910 } 911 912 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 913 StringRef sys::getHostCPUName() { 914 host_basic_info_data_t hostInfo; 915 mach_msg_type_number_t infoCount; 916 917 infoCount = HOST_BASIC_INFO_COUNT; 918 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo, 919 &infoCount); 920 921 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 922 return "generic"; 923 924 switch (hostInfo.cpu_subtype) { 925 case CPU_SUBTYPE_POWERPC_601: 926 return "601"; 927 case CPU_SUBTYPE_POWERPC_602: 928 return "602"; 929 case CPU_SUBTYPE_POWERPC_603: 930 return "603"; 931 case CPU_SUBTYPE_POWERPC_603e: 932 return "603e"; 933 case CPU_SUBTYPE_POWERPC_603ev: 934 return "603ev"; 935 case CPU_SUBTYPE_POWERPC_604: 936 return "604"; 937 case CPU_SUBTYPE_POWERPC_604e: 938 return "604e"; 939 case CPU_SUBTYPE_POWERPC_620: 940 return "620"; 941 case CPU_SUBTYPE_POWERPC_750: 942 return "750"; 943 case CPU_SUBTYPE_POWERPC_7400: 944 return "7400"; 945 case CPU_SUBTYPE_POWERPC_7450: 946 return "7450"; 947 case CPU_SUBTYPE_POWERPC_970: 948 return "970"; 949 default:; 950 } 951 952 return "generic"; 953 } 954 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 955 StringRef sys::getHostCPUName() { 956 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 957 // and so we must use an operating-system interface to determine the current 958 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 959 const char *generic = "generic"; 960 961 // The cpu line is second (after the 'processor: 0' line), so if this 962 // buffer is too small then something has changed (or is wrong). 963 char buffer[1024]; 964 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer)); 965 if (CPUInfoSize == -1) 966 return generic; 967 968 const char *CPUInfoStart = buffer; 969 const char *CPUInfoEnd = buffer + CPUInfoSize; 970 971 const char *CIP = CPUInfoStart; 972 973 const char *CPUStart = 0; 974 size_t CPULen = 0; 975 976 // We need to find the first line which starts with cpu, spaces, and a colon. 977 // After the colon, there may be some additional spaces and then the cpu type. 978 while (CIP < CPUInfoEnd && CPUStart == 0) { 979 if (CIP < CPUInfoEnd && *CIP == '\n') 980 ++CIP; 981 982 if (CIP < CPUInfoEnd && *CIP == 'c') { 983 ++CIP; 984 if (CIP < CPUInfoEnd && *CIP == 'p') { 985 ++CIP; 986 if (CIP < CPUInfoEnd && *CIP == 'u') { 987 ++CIP; 988 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 989 ++CIP; 990 991 if (CIP < CPUInfoEnd && *CIP == ':') { 992 ++CIP; 993 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 994 ++CIP; 995 996 if (CIP < CPUInfoEnd) { 997 CPUStart = CIP; 998 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 999 *CIP != ',' && *CIP != '\n')) 1000 ++CIP; 1001 CPULen = CIP - CPUStart; 1002 } 1003 } 1004 } 1005 } 1006 } 1007 1008 if (CPUStart == 0) 1009 while (CIP < CPUInfoEnd && *CIP != '\n') 1010 ++CIP; 1011 } 1012 1013 if (CPUStart == 0) 1014 return generic; 1015 1016 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 1017 .Case("604e", "604e") 1018 .Case("604", "604") 1019 .Case("7400", "7400") 1020 .Case("7410", "7400") 1021 .Case("7447", "7400") 1022 .Case("7455", "7450") 1023 .Case("G4", "g4") 1024 .Case("POWER4", "970") 1025 .Case("PPC970FX", "970") 1026 .Case("PPC970MP", "970") 1027 .Case("G5", "g5") 1028 .Case("POWER5", "g5") 1029 .Case("A2", "a2") 1030 .Case("POWER6", "pwr6") 1031 .Case("POWER7", "pwr7") 1032 .Case("POWER8", "pwr8") 1033 .Case("POWER8E", "pwr8") 1034 .Case("POWER9", "pwr9") 1035 .Default(generic); 1036 } 1037 #elif defined(__linux__) && defined(__arm__) 1038 StringRef sys::getHostCPUName() { 1039 // The cpuid register on arm is not accessible from user space. On Linux, 1040 // it is exposed through the /proc/cpuinfo file. 1041 1042 // Read 1024 bytes from /proc/cpuinfo, which should contain the CPU part line 1043 // in all cases. 1044 char buffer[1024]; 1045 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer)); 1046 if (CPUInfoSize == -1) 1047 return "generic"; 1048 1049 StringRef Str(buffer, CPUInfoSize); 1050 1051 SmallVector<StringRef, 32> Lines; 1052 Str.split(Lines, "\n"); 1053 1054 // Look for the CPU implementer line. 1055 StringRef Implementer; 1056 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1057 if (Lines[I].startswith("CPU implementer")) 1058 Implementer = Lines[I].substr(15).ltrim("\t :"); 1059 1060 if (Implementer == "0x41") // ARM Ltd. 1061 // Look for the CPU part line. 1062 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1063 if (Lines[I].startswith("CPU part")) 1064 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 1065 // values correspond to the "Part number" in the CP15/c0 register. The 1066 // contents are specified in the various processor manuals. 1067 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 1068 .Case("0x926", "arm926ej-s") 1069 .Case("0xb02", "mpcore") 1070 .Case("0xb36", "arm1136j-s") 1071 .Case("0xb56", "arm1156t2-s") 1072 .Case("0xb76", "arm1176jz-s") 1073 .Case("0xc08", "cortex-a8") 1074 .Case("0xc09", "cortex-a9") 1075 .Case("0xc0f", "cortex-a15") 1076 .Case("0xc20", "cortex-m0") 1077 .Case("0xc23", "cortex-m3") 1078 .Case("0xc24", "cortex-m4") 1079 .Default("generic"); 1080 1081 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 1082 // Look for the CPU part line. 1083 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1084 if (Lines[I].startswith("CPU part")) 1085 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 1086 // values correspond to the "Part number" in the CP15/c0 register. The 1087 // contents are specified in the various processor manuals. 1088 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 1089 .Case("0x06f", "krait") // APQ8064 1090 .Default("generic"); 1091 1092 return "generic"; 1093 } 1094 #elif defined(__linux__) && defined(__s390x__) 1095 StringRef sys::getHostCPUName() { 1096 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 1097 1098 // The "processor 0:" line comes after a fair amount of other information, 1099 // including a cache breakdown, but this should be plenty. 1100 char buffer[2048]; 1101 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer)); 1102 if (CPUInfoSize == -1) 1103 return "generic"; 1104 1105 StringRef Str(buffer, CPUInfoSize); 1106 SmallVector<StringRef, 32> Lines; 1107 Str.split(Lines, "\n"); 1108 1109 // Look for the CPU features. 1110 SmallVector<StringRef, 32> CPUFeatures; 1111 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1112 if (Lines[I].startswith("features")) { 1113 size_t Pos = Lines[I].find(":"); 1114 if (Pos != StringRef::npos) { 1115 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 1116 break; 1117 } 1118 } 1119 1120 // We need to check for the presence of vector support independently of 1121 // the machine type, since we may only use the vector register set when 1122 // supported by the kernel (and hypervisor). 1123 bool HaveVectorSupport = false; 1124 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1125 if (CPUFeatures[I] == "vx") 1126 HaveVectorSupport = true; 1127 } 1128 1129 // Now check the processor machine type. 1130 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 1131 if (Lines[I].startswith("processor ")) { 1132 size_t Pos = Lines[I].find("machine = "); 1133 if (Pos != StringRef::npos) { 1134 Pos += sizeof("machine = ") - 1; 1135 unsigned int Id; 1136 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 1137 if (Id >= 2964 && HaveVectorSupport) 1138 return "z13"; 1139 if (Id >= 2827) 1140 return "zEC12"; 1141 if (Id >= 2817) 1142 return "z196"; 1143 } 1144 } 1145 break; 1146 } 1147 } 1148 1149 return "generic"; 1150 } 1151 #else 1152 StringRef sys::getHostCPUName() { return "generic"; } 1153 #endif 1154 1155 #if defined(i386) || defined(__i386__) || defined(__x86__) || \ 1156 defined(_M_IX86) || defined(__x86_64__) || defined(_M_AMD64) || \ 1157 defined(_M_X64) 1158 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1159 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1160 unsigned MaxLevel; 1161 union { 1162 unsigned u[3]; 1163 char c[12]; 1164 } text; 1165 1166 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1167 MaxLevel < 1) 1168 return false; 1169 1170 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1171 1172 Features["cmov"] = (EDX >> 15) & 1; 1173 Features["mmx"] = (EDX >> 23) & 1; 1174 Features["sse"] = (EDX >> 25) & 1; 1175 Features["sse2"] = (EDX >> 26) & 1; 1176 Features["sse3"] = (ECX >> 0) & 1; 1177 Features["ssse3"] = (ECX >> 9) & 1; 1178 Features["sse4.1"] = (ECX >> 19) & 1; 1179 Features["sse4.2"] = (ECX >> 20) & 1; 1180 1181 Features["pclmul"] = (ECX >> 1) & 1; 1182 Features["cx16"] = (ECX >> 13) & 1; 1183 Features["movbe"] = (ECX >> 22) & 1; 1184 Features["popcnt"] = (ECX >> 23) & 1; 1185 Features["aes"] = (ECX >> 25) & 1; 1186 Features["rdrnd"] = (ECX >> 30) & 1; 1187 1188 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1189 // indicates that the AVX registers will be saved and restored on context 1190 // switch, then we have full AVX support. 1191 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1192 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1193 Features["avx"] = HasAVXSave; 1194 Features["fma"] = HasAVXSave && (ECX >> 12) & 1; 1195 Features["f16c"] = HasAVXSave && (ECX >> 29) & 1; 1196 1197 // Only enable XSAVE if OS has enabled support for saving YMM state. 1198 Features["xsave"] = HasAVXSave && (ECX >> 26) & 1; 1199 1200 // AVX512 requires additional context to be saved by the OS. 1201 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1202 1203 unsigned MaxExtLevel; 1204 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1205 1206 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1207 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1208 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1209 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1210 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1211 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1212 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1213 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1214 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1215 1216 bool HasLeaf7 = 1217 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1218 1219 // AVX2 is only supported if we have the OS save support from AVX. 1220 Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1); 1221 1222 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1223 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1224 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1225 Features["hle"] = HasLeaf7 && ((EBX >> 4) & 1); 1226 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1227 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1228 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1229 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1230 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1231 Features["smap"] = HasLeaf7 && ((EBX >> 20) & 1); 1232 Features["pcommit"] = HasLeaf7 && ((EBX >> 22) & 1); 1233 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1234 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1235 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1236 1237 // AVX512 is only supported if the OS supports the context save for it. 1238 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1239 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1240 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1241 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1242 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1243 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1244 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1245 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1246 1247 Features["prefetchwt1"] = HasLeaf7 && (ECX & 1); 1248 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1249 // Enable protection keys 1250 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1251 1252 bool HasLeafD = MaxLevel >= 0xd && 1253 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1254 1255 // Only enable XSAVE if OS has enabled support for saving YMM state. 1256 Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1); 1257 Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1); 1258 Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1); 1259 1260 return true; 1261 } 1262 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1263 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1264 // Read 1024 bytes from /proc/cpuinfo, which should contain the Features line 1265 // in all cases. 1266 char buffer[1024]; 1267 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer)); 1268 if (CPUInfoSize == -1) 1269 return false; 1270 1271 StringRef Str(buffer, CPUInfoSize); 1272 1273 SmallVector<StringRef, 32> Lines; 1274 Str.split(Lines, "\n"); 1275 1276 SmallVector<StringRef, 32> CPUFeatures; 1277 1278 // Look for the CPU features. 1279 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1280 if (Lines[I].startswith("Features")) { 1281 Lines[I].split(CPUFeatures, ' '); 1282 break; 1283 } 1284 1285 #if defined(__aarch64__) 1286 // Keep track of which crypto features we have seen 1287 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1288 uint32_t crypto = 0; 1289 #endif 1290 1291 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1292 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1293 #if defined(__aarch64__) 1294 .Case("asimd", "neon") 1295 .Case("fp", "fp-armv8") 1296 .Case("crc32", "crc") 1297 #else 1298 .Case("half", "fp16") 1299 .Case("neon", "neon") 1300 .Case("vfpv3", "vfp3") 1301 .Case("vfpv3d16", "d16") 1302 .Case("vfpv4", "vfp4") 1303 .Case("idiva", "hwdiv-arm") 1304 .Case("idivt", "hwdiv") 1305 #endif 1306 .Default(""); 1307 1308 #if defined(__aarch64__) 1309 // We need to check crypto separately since we need all of the crypto 1310 // extensions to enable the subtarget feature 1311 if (CPUFeatures[I] == "aes") 1312 crypto |= CAP_AES; 1313 else if (CPUFeatures[I] == "pmull") 1314 crypto |= CAP_PMULL; 1315 else if (CPUFeatures[I] == "sha1") 1316 crypto |= CAP_SHA1; 1317 else if (CPUFeatures[I] == "sha2") 1318 crypto |= CAP_SHA2; 1319 #endif 1320 1321 if (LLVMFeatureStr != "") 1322 Features[LLVMFeatureStr] = true; 1323 } 1324 1325 #if defined(__aarch64__) 1326 // If we have all crypto bits we can add the feature 1327 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1328 Features["crypto"] = true; 1329 #endif 1330 1331 return true; 1332 } 1333 #else 1334 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1335 #endif 1336 1337 std::string sys::getProcessTriple() { 1338 Triple PT(Triple::normalize(LLVM_HOST_TRIPLE)); 1339 1340 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1341 PT = PT.get64BitArchVariant(); 1342 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1343 PT = PT.get32BitArchVariant(); 1344 1345 return PT.str(); 1346 } 1347