1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the operating system Host concept. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/Host.h" 14 #include "llvm/ADT/SmallSet.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringMap.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/llvm-config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/X86TargetParser.h" 25 #include "llvm/Support/raw_ostream.h" 26 #include <assert.h> 27 #include <string.h> 28 29 // Include the platform-specific parts of this class. 30 #ifdef LLVM_ON_UNIX 31 #include "Unix/Host.inc" 32 #include <sched.h> 33 #endif 34 #ifdef _WIN32 35 #include "Windows/Host.inc" 36 #endif 37 #ifdef _MSC_VER 38 #include <intrin.h> 39 #endif 40 #if defined(__APPLE__) && (!defined(__x86_64__)) 41 #include <mach/host_info.h> 42 #include <mach/mach.h> 43 #include <mach/mach_host.h> 44 #include <mach/machine.h> 45 #endif 46 47 #define DEBUG_TYPE "host-detection" 48 49 //===----------------------------------------------------------------------===// 50 // 51 // Implementations of the CPU detection routines 52 // 53 //===----------------------------------------------------------------------===// 54 55 using namespace llvm; 56 57 static std::unique_ptr<llvm::MemoryBuffer> 58 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 59 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 60 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 61 if (std::error_code EC = Text.getError()) { 62 llvm::errs() << "Can't read " 63 << "/proc/cpuinfo: " << EC.message() << "\n"; 64 return nullptr; 65 } 66 return std::move(*Text); 67 } 68 69 StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) { 70 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 71 // and so we must use an operating-system interface to determine the current 72 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 73 const char *generic = "generic"; 74 75 // The cpu line is second (after the 'processor: 0' line), so if this 76 // buffer is too small then something has changed (or is wrong). 77 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 78 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 79 80 StringRef::const_iterator CIP = CPUInfoStart; 81 82 StringRef::const_iterator CPUStart = 0; 83 size_t CPULen = 0; 84 85 // We need to find the first line which starts with cpu, spaces, and a colon. 86 // After the colon, there may be some additional spaces and then the cpu type. 87 while (CIP < CPUInfoEnd && CPUStart == 0) { 88 if (CIP < CPUInfoEnd && *CIP == '\n') 89 ++CIP; 90 91 if (CIP < CPUInfoEnd && *CIP == 'c') { 92 ++CIP; 93 if (CIP < CPUInfoEnd && *CIP == 'p') { 94 ++CIP; 95 if (CIP < CPUInfoEnd && *CIP == 'u') { 96 ++CIP; 97 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 98 ++CIP; 99 100 if (CIP < CPUInfoEnd && *CIP == ':') { 101 ++CIP; 102 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 103 ++CIP; 104 105 if (CIP < CPUInfoEnd) { 106 CPUStart = CIP; 107 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 108 *CIP != ',' && *CIP != '\n')) 109 ++CIP; 110 CPULen = CIP - CPUStart; 111 } 112 } 113 } 114 } 115 } 116 117 if (CPUStart == 0) 118 while (CIP < CPUInfoEnd && *CIP != '\n') 119 ++CIP; 120 } 121 122 if (CPUStart == 0) 123 return generic; 124 125 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 126 .Case("604e", "604e") 127 .Case("604", "604") 128 .Case("7400", "7400") 129 .Case("7410", "7400") 130 .Case("7447", "7400") 131 .Case("7455", "7450") 132 .Case("G4", "g4") 133 .Case("POWER4", "970") 134 .Case("PPC970FX", "970") 135 .Case("PPC970MP", "970") 136 .Case("G5", "g5") 137 .Case("POWER5", "g5") 138 .Case("A2", "a2") 139 .Case("POWER6", "pwr6") 140 .Case("POWER7", "pwr7") 141 .Case("POWER8", "pwr8") 142 .Case("POWER8E", "pwr8") 143 .Case("POWER8NVL", "pwr8") 144 .Case("POWER9", "pwr9") 145 .Case("POWER10", "pwr10") 146 // FIXME: If we get a simulator or machine with the capabilities of 147 // mcpu=future, we should revisit this and add the name reported by the 148 // simulator/machine. 149 .Default(generic); 150 } 151 152 StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { 153 // The cpuid register on arm is not accessible from user space. On Linux, 154 // it is exposed through the /proc/cpuinfo file. 155 156 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 157 // in all cases. 158 SmallVector<StringRef, 32> Lines; 159 ProcCpuinfoContent.split(Lines, "\n"); 160 161 // Look for the CPU implementer line. 162 StringRef Implementer; 163 StringRef Hardware; 164 StringRef Part; 165 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 166 if (Lines[I].startswith("CPU implementer")) 167 Implementer = Lines[I].substr(15).ltrim("\t :"); 168 if (Lines[I].startswith("Hardware")) 169 Hardware = Lines[I].substr(8).ltrim("\t :"); 170 if (Lines[I].startswith("CPU part")) 171 Part = Lines[I].substr(8).ltrim("\t :"); 172 } 173 174 if (Implementer == "0x41") { // ARM Ltd. 175 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 176 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 177 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 178 return "cortex-a53"; 179 180 181 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 182 // values correspond to the "Part number" in the CP15/c0 register. The 183 // contents are specified in the various processor manuals. 184 // This corresponds to the Main ID Register in Technical Reference Manuals. 185 // and is used in programs like sys-utils 186 return StringSwitch<const char *>(Part) 187 .Case("0x926", "arm926ej-s") 188 .Case("0xb02", "mpcore") 189 .Case("0xb36", "arm1136j-s") 190 .Case("0xb56", "arm1156t2-s") 191 .Case("0xb76", "arm1176jz-s") 192 .Case("0xc08", "cortex-a8") 193 .Case("0xc09", "cortex-a9") 194 .Case("0xc0f", "cortex-a15") 195 .Case("0xc20", "cortex-m0") 196 .Case("0xc23", "cortex-m3") 197 .Case("0xc24", "cortex-m4") 198 .Case("0xd22", "cortex-m55") 199 .Case("0xd02", "cortex-a34") 200 .Case("0xd04", "cortex-a35") 201 .Case("0xd03", "cortex-a53") 202 .Case("0xd07", "cortex-a57") 203 .Case("0xd08", "cortex-a72") 204 .Case("0xd09", "cortex-a73") 205 .Case("0xd0a", "cortex-a75") 206 .Case("0xd0b", "cortex-a76") 207 .Case("0xd0d", "cortex-a77") 208 .Case("0xd41", "cortex-a78") 209 .Case("0xd44", "cortex-x1") 210 .Case("0xd0c", "neoverse-n1") 211 .Case("0xd49", "neoverse-n2") 212 .Default("generic"); 213 } 214 215 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium. 216 return StringSwitch<const char *>(Part) 217 .Case("0x516", "thunderx2t99") 218 .Case("0x0516", "thunderx2t99") 219 .Case("0xaf", "thunderx2t99") 220 .Case("0x0af", "thunderx2t99") 221 .Case("0xa1", "thunderxt88") 222 .Case("0x0a1", "thunderxt88") 223 .Default("generic"); 224 } 225 226 if (Implementer == "0x46") { // Fujitsu Ltd. 227 return StringSwitch<const char *>(Part) 228 .Case("0x001", "a64fx") 229 .Default("generic"); 230 } 231 232 if (Implementer == "0x4e") { // NVIDIA Corporation 233 return StringSwitch<const char *>(Part) 234 .Case("0x004", "carmel") 235 .Default("generic"); 236 } 237 238 if (Implementer == "0x48") // HiSilicon Technologies, Inc. 239 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 240 // values correspond to the "Part number" in the CP15/c0 register. The 241 // contents are specified in the various processor manuals. 242 return StringSwitch<const char *>(Part) 243 .Case("0xd01", "tsv110") 244 .Default("generic"); 245 246 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 247 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 248 // values correspond to the "Part number" in the CP15/c0 register. The 249 // contents are specified in the various processor manuals. 250 return StringSwitch<const char *>(Part) 251 .Case("0x06f", "krait") // APQ8064 252 .Case("0x201", "kryo") 253 .Case("0x205", "kryo") 254 .Case("0x211", "kryo") 255 .Case("0x800", "cortex-a73") // Kryo 2xx Gold 256 .Case("0x801", "cortex-a73") // Kryo 2xx Silver 257 .Case("0x802", "cortex-a75") // Kryo 3xx Gold 258 .Case("0x803", "cortex-a75") // Kryo 3xx Silver 259 .Case("0x804", "cortex-a76") // Kryo 4xx Gold 260 .Case("0x805", "cortex-a76") // Kryo 4xx/5xx Silver 261 .Case("0xc00", "falkor") 262 .Case("0xc01", "saphira") 263 .Default("generic"); 264 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. 265 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow 266 // any predictive pattern across variants and parts. 267 unsigned Variant = 0, Part = 0; 268 269 // Look for the CPU variant line, whose value is a 1 digit hexadecimal 270 // number, corresponding to the Variant bits in the CP15/C0 register. 271 for (auto I : Lines) 272 if (I.consume_front("CPU variant")) 273 I.ltrim("\t :").getAsInteger(0, Variant); 274 275 // Look for the CPU part line, whose value is a 3 digit hexadecimal 276 // number, corresponding to the PartNum bits in the CP15/C0 register. 277 for (auto I : Lines) 278 if (I.consume_front("CPU part")) 279 I.ltrim("\t :").getAsInteger(0, Part); 280 281 unsigned Exynos = (Variant << 12) | Part; 282 switch (Exynos) { 283 default: 284 // Default by falling through to Exynos M3. 285 LLVM_FALLTHROUGH; 286 case 0x1002: 287 return "exynos-m3"; 288 case 0x1003: 289 return "exynos-m4"; 290 } 291 } 292 293 return "generic"; 294 } 295 296 StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { 297 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 298 299 // The "processor 0:" line comes after a fair amount of other information, 300 // including a cache breakdown, but this should be plenty. 301 SmallVector<StringRef, 32> Lines; 302 ProcCpuinfoContent.split(Lines, "\n"); 303 304 // Look for the CPU features. 305 SmallVector<StringRef, 32> CPUFeatures; 306 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 307 if (Lines[I].startswith("features")) { 308 size_t Pos = Lines[I].find(':'); 309 if (Pos != StringRef::npos) { 310 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 311 break; 312 } 313 } 314 315 // We need to check for the presence of vector support independently of 316 // the machine type, since we may only use the vector register set when 317 // supported by the kernel (and hypervisor). 318 bool HaveVectorSupport = false; 319 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 320 if (CPUFeatures[I] == "vx") 321 HaveVectorSupport = true; 322 } 323 324 // Now check the processor machine type. 325 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 326 if (Lines[I].startswith("processor ")) { 327 size_t Pos = Lines[I].find("machine = "); 328 if (Pos != StringRef::npos) { 329 Pos += sizeof("machine = ") - 1; 330 unsigned int Id; 331 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 332 if (Id >= 8561 && HaveVectorSupport) 333 return "z15"; 334 if (Id >= 3906 && HaveVectorSupport) 335 return "z14"; 336 if (Id >= 2964 && HaveVectorSupport) 337 return "z13"; 338 if (Id >= 2827) 339 return "zEC12"; 340 if (Id >= 2817) 341 return "z196"; 342 } 343 } 344 break; 345 } 346 } 347 348 return "generic"; 349 } 350 351 StringRef sys::detail::getHostCPUNameForBPF() { 352 #if !defined(__linux__) || !defined(__x86_64__) 353 return "generic"; 354 #else 355 uint8_t v3_insns[40] __attribute__ ((aligned (8))) = 356 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 357 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 358 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 359 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 360 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 361 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 362 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 363 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 364 /* BPF_EXIT_INSN() */ 365 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 366 367 uint8_t v2_insns[40] __attribute__ ((aligned (8))) = 368 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 369 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 370 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 371 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 372 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 373 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 374 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 375 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 376 /* BPF_EXIT_INSN() */ 377 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 378 379 struct bpf_prog_load_attr { 380 uint32_t prog_type; 381 uint32_t insn_cnt; 382 uint64_t insns; 383 uint64_t license; 384 uint32_t log_level; 385 uint32_t log_size; 386 uint64_t log_buf; 387 uint32_t kern_version; 388 uint32_t prog_flags; 389 } attr = {}; 390 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 391 attr.insn_cnt = 5; 392 attr.insns = (uint64_t)v3_insns; 393 attr.license = (uint64_t)"DUMMY"; 394 395 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, 396 sizeof(attr)); 397 if (fd >= 0) { 398 close(fd); 399 return "v3"; 400 } 401 402 /* Clear the whole attr in case its content changed by syscall. */ 403 memset(&attr, 0, sizeof(attr)); 404 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 405 attr.insn_cnt = 5; 406 attr.insns = (uint64_t)v2_insns; 407 attr.license = (uint64_t)"DUMMY"; 408 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 409 if (fd >= 0) { 410 close(fd); 411 return "v2"; 412 } 413 return "v1"; 414 #endif 415 } 416 417 #if defined(__i386__) || defined(_M_IX86) || \ 418 defined(__x86_64__) || defined(_M_X64) 419 420 enum VendorSignatures { 421 SIG_INTEL = 0x756e6547 /* Genu */, 422 SIG_AMD = 0x68747541 /* Auth */ 423 }; 424 425 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 426 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 427 // support. Consequently, for i386, the presence of CPUID is checked first 428 // via the corresponding eflags bit. 429 // Removal of cpuid.h header motivated by PR30384 430 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 431 // or test-suite, but are used in external projects e.g. libstdcxx 432 static bool isCpuIdSupported() { 433 #if defined(__GNUC__) || defined(__clang__) 434 #if defined(__i386__) 435 int __cpuid_supported; 436 __asm__(" pushfl\n" 437 " popl %%eax\n" 438 " movl %%eax,%%ecx\n" 439 " xorl $0x00200000,%%eax\n" 440 " pushl %%eax\n" 441 " popfl\n" 442 " pushfl\n" 443 " popl %%eax\n" 444 " movl $0,%0\n" 445 " cmpl %%eax,%%ecx\n" 446 " je 1f\n" 447 " movl $1,%0\n" 448 "1:" 449 : "=r"(__cpuid_supported) 450 : 451 : "eax", "ecx"); 452 if (!__cpuid_supported) 453 return false; 454 #endif 455 return true; 456 #endif 457 return true; 458 } 459 460 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 461 /// the specified arguments. If we can't run cpuid on the host, return true. 462 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 463 unsigned *rECX, unsigned *rEDX) { 464 #if defined(__GNUC__) || defined(__clang__) 465 #if defined(__x86_64__) 466 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 467 // FIXME: should we save this for Clang? 468 __asm__("movq\t%%rbx, %%rsi\n\t" 469 "cpuid\n\t" 470 "xchgq\t%%rbx, %%rsi\n\t" 471 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 472 : "a"(value)); 473 return false; 474 #elif defined(__i386__) 475 __asm__("movl\t%%ebx, %%esi\n\t" 476 "cpuid\n\t" 477 "xchgl\t%%ebx, %%esi\n\t" 478 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 479 : "a"(value)); 480 return false; 481 #else 482 return true; 483 #endif 484 #elif defined(_MSC_VER) 485 // The MSVC intrinsic is portable across x86 and x64. 486 int registers[4]; 487 __cpuid(registers, value); 488 *rEAX = registers[0]; 489 *rEBX = registers[1]; 490 *rECX = registers[2]; 491 *rEDX = registers[3]; 492 return false; 493 #else 494 return true; 495 #endif 496 } 497 498 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 499 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 500 /// return true. 501 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 502 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 503 unsigned *rEDX) { 504 #if defined(__GNUC__) || defined(__clang__) 505 #if defined(__x86_64__) 506 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 507 // FIXME: should we save this for Clang? 508 __asm__("movq\t%%rbx, %%rsi\n\t" 509 "cpuid\n\t" 510 "xchgq\t%%rbx, %%rsi\n\t" 511 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 512 : "a"(value), "c"(subleaf)); 513 return false; 514 #elif defined(__i386__) 515 __asm__("movl\t%%ebx, %%esi\n\t" 516 "cpuid\n\t" 517 "xchgl\t%%ebx, %%esi\n\t" 518 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 519 : "a"(value), "c"(subleaf)); 520 return false; 521 #else 522 return true; 523 #endif 524 #elif defined(_MSC_VER) 525 int registers[4]; 526 __cpuidex(registers, value, subleaf); 527 *rEAX = registers[0]; 528 *rEBX = registers[1]; 529 *rECX = registers[2]; 530 *rEDX = registers[3]; 531 return false; 532 #else 533 return true; 534 #endif 535 } 536 537 // Read control register 0 (XCR0). Used to detect features such as AVX. 538 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 539 #if defined(__GNUC__) || defined(__clang__) 540 // Check xgetbv; this uses a .byte sequence instead of the instruction 541 // directly because older assemblers do not include support for xgetbv and 542 // there is no easy way to conditionally compile based on the assembler used. 543 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 544 return false; 545 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 546 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 547 *rEAX = Result; 548 *rEDX = Result >> 32; 549 return false; 550 #else 551 return true; 552 #endif 553 } 554 555 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 556 unsigned *Model) { 557 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 558 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 559 if (*Family == 6 || *Family == 0xf) { 560 if (*Family == 0xf) 561 // Examine extended family ID if family ID is F. 562 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 563 // Examine extended model ID if family ID is 6 or F. 564 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 565 } 566 } 567 568 static StringRef 569 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 570 const unsigned *Features, 571 unsigned *Type, unsigned *Subtype) { 572 auto testFeature = [&](unsigned F) { 573 return (Features[F / 32] & (1U << (F % 32))) != 0; 574 }; 575 576 StringRef CPU; 577 578 switch (Family) { 579 case 3: 580 CPU = "i386"; 581 break; 582 case 4: 583 CPU = "i486"; 584 break; 585 case 5: 586 if (testFeature(X86::FEATURE_MMX)) { 587 CPU = "pentium-mmx"; 588 break; 589 } 590 CPU = "pentium"; 591 break; 592 case 6: 593 switch (Model) { 594 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 595 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 596 // mobile processor, Intel Core 2 Extreme processor, Intel 597 // Pentium Dual-Core processor, Intel Xeon processor, model 598 // 0Fh. All processors are manufactured using the 65 nm process. 599 case 0x16: // Intel Celeron processor model 16h. All processors are 600 // manufactured using the 65 nm process 601 CPU = "core2"; 602 *Type = X86::INTEL_CORE2; 603 break; 604 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 605 // 17h. All processors are manufactured using the 45 nm process. 606 // 607 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 608 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 609 // the 45 nm process. 610 CPU = "penryn"; 611 *Type = X86::INTEL_CORE2; 612 break; 613 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 614 // processors are manufactured using the 45 nm process. 615 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 616 // As found in a Summer 2010 model iMac. 617 case 0x1f: 618 case 0x2e: // Nehalem EX 619 CPU = "nehalem"; 620 *Type = X86::INTEL_COREI7; 621 *Subtype = X86::INTEL_COREI7_NEHALEM; 622 break; 623 case 0x25: // Intel Core i7, laptop version. 624 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 625 // processors are manufactured using the 32 nm process. 626 case 0x2f: // Westmere EX 627 CPU = "westmere"; 628 *Type = X86::INTEL_COREI7; 629 *Subtype = X86::INTEL_COREI7_WESTMERE; 630 break; 631 case 0x2a: // Intel Core i7 processor. All processors are manufactured 632 // using the 32 nm process. 633 case 0x2d: 634 CPU = "sandybridge"; 635 *Type = X86::INTEL_COREI7; 636 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 637 break; 638 case 0x3a: 639 case 0x3e: // Ivy Bridge EP 640 CPU = "ivybridge"; 641 *Type = X86::INTEL_COREI7; 642 *Subtype = X86::INTEL_COREI7_IVYBRIDGE; 643 break; 644 645 // Haswell: 646 case 0x3c: 647 case 0x3f: 648 case 0x45: 649 case 0x46: 650 CPU = "haswell"; 651 *Type = X86::INTEL_COREI7; 652 *Subtype = X86::INTEL_COREI7_HASWELL; 653 break; 654 655 // Broadwell: 656 case 0x3d: 657 case 0x47: 658 case 0x4f: 659 case 0x56: 660 CPU = "broadwell"; 661 *Type = X86::INTEL_COREI7; 662 *Subtype = X86::INTEL_COREI7_BROADWELL; 663 break; 664 665 // Skylake: 666 case 0x4e: // Skylake mobile 667 case 0x5e: // Skylake desktop 668 case 0x8e: // Kaby Lake mobile 669 case 0x9e: // Kaby Lake desktop 670 case 0xa5: // Comet Lake-H/S 671 case 0xa6: // Comet Lake-U 672 CPU = "skylake"; 673 *Type = X86::INTEL_COREI7; 674 *Subtype = X86::INTEL_COREI7_SKYLAKE; 675 break; 676 677 // Skylake Xeon: 678 case 0x55: 679 *Type = X86::INTEL_COREI7; 680 if (testFeature(X86::FEATURE_AVX512BF16)) { 681 CPU = "cooperlake"; 682 *Subtype = X86::INTEL_COREI7_COOPERLAKE; 683 } else if (testFeature(X86::FEATURE_AVX512VNNI)) { 684 CPU = "cascadelake"; 685 *Subtype = X86::INTEL_COREI7_CASCADELAKE; 686 } else { 687 CPU = "skylake-avx512"; 688 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; 689 } 690 break; 691 692 // Cannonlake: 693 case 0x66: 694 CPU = "cannonlake"; 695 *Type = X86::INTEL_COREI7; 696 *Subtype = X86::INTEL_COREI7_CANNONLAKE; 697 break; 698 699 // Icelake: 700 case 0x7d: 701 case 0x7e: 702 CPU = "icelake-client"; 703 *Type = X86::INTEL_COREI7; 704 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; 705 break; 706 707 // Icelake Xeon: 708 case 0x6a: 709 case 0x6c: 710 CPU = "icelake-server"; 711 *Type = X86::INTEL_COREI7; 712 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; 713 break; 714 715 // Sapphire Rapids: 716 case 0x8f: 717 CPU = "sapphirerapids"; 718 *Type = X86::INTEL_COREI7; 719 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS; 720 break; 721 722 case 0x1c: // Most 45 nm Intel Atom processors 723 case 0x26: // 45 nm Atom Lincroft 724 case 0x27: // 32 nm Atom Medfield 725 case 0x35: // 32 nm Atom Midview 726 case 0x36: // 32 nm Atom Midview 727 CPU = "bonnell"; 728 *Type = X86::INTEL_BONNELL; 729 break; 730 731 // Atom Silvermont codes from the Intel software optimization guide. 732 case 0x37: 733 case 0x4a: 734 case 0x4d: 735 case 0x5a: 736 case 0x5d: 737 case 0x4c: // really airmont 738 CPU = "silvermont"; 739 *Type = X86::INTEL_SILVERMONT; 740 break; 741 // Goldmont: 742 case 0x5c: // Apollo Lake 743 case 0x5f: // Denverton 744 CPU = "goldmont"; 745 *Type = X86::INTEL_GOLDMONT; 746 break; 747 case 0x7a: 748 CPU = "goldmont-plus"; 749 *Type = X86::INTEL_GOLDMONT_PLUS; 750 break; 751 case 0x86: 752 CPU = "tremont"; 753 *Type = X86::INTEL_TREMONT; 754 break; 755 756 // Xeon Phi (Knights Landing + Knights Mill): 757 case 0x57: 758 CPU = "knl"; 759 *Type = X86::INTEL_KNL; 760 break; 761 case 0x85: 762 CPU = "knm"; 763 *Type = X86::INTEL_KNM; 764 break; 765 766 default: // Unknown family 6 CPU, try to guess. 767 // Don't both with Type/Subtype here, they aren't used by the caller. 768 // They're used above to keep the code in sync with compiler-rt. 769 // TODO detect tigerlake host from model 770 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) { 771 CPU = "tigerlake"; 772 } else if (testFeature(X86::FEATURE_AVX512VBMI2)) { 773 CPU = "icelake-client"; 774 } else if (testFeature(X86::FEATURE_AVX512VBMI)) { 775 CPU = "cannonlake"; 776 } else if (testFeature(X86::FEATURE_AVX512BF16)) { 777 CPU = "cooperlake"; 778 } else if (testFeature(X86::FEATURE_AVX512VNNI)) { 779 CPU = "cascadelake"; 780 } else if (testFeature(X86::FEATURE_AVX512VL)) { 781 CPU = "skylake-avx512"; 782 } else if (testFeature(X86::FEATURE_AVX512ER)) { 783 CPU = "knl"; 784 } else if (testFeature(X86::FEATURE_CLFLUSHOPT)) { 785 if (testFeature(X86::FEATURE_SHA)) 786 CPU = "goldmont"; 787 else 788 CPU = "skylake"; 789 } else if (testFeature(X86::FEATURE_ADX)) { 790 CPU = "broadwell"; 791 } else if (testFeature(X86::FEATURE_AVX2)) { 792 CPU = "haswell"; 793 } else if (testFeature(X86::FEATURE_AVX)) { 794 CPU = "sandybridge"; 795 } else if (testFeature(X86::FEATURE_SSE4_2)) { 796 if (testFeature(X86::FEATURE_MOVBE)) 797 CPU = "silvermont"; 798 else 799 CPU = "nehalem"; 800 } else if (testFeature(X86::FEATURE_SSE4_1)) { 801 CPU = "penryn"; 802 } else if (testFeature(X86::FEATURE_SSSE3)) { 803 if (testFeature(X86::FEATURE_MOVBE)) 804 CPU = "bonnell"; 805 else 806 CPU = "core2"; 807 } else if (testFeature(X86::FEATURE_64BIT)) { 808 CPU = "core2"; 809 } else if (testFeature(X86::FEATURE_SSE3)) { 810 CPU = "yonah"; 811 } else if (testFeature(X86::FEATURE_SSE2)) { 812 CPU = "pentium-m"; 813 } else if (testFeature(X86::FEATURE_SSE)) { 814 CPU = "pentium3"; 815 } else if (testFeature(X86::FEATURE_MMX)) { 816 CPU = "pentium2"; 817 } else { 818 CPU = "pentiumpro"; 819 } 820 break; 821 } 822 break; 823 case 15: { 824 if (testFeature(X86::FEATURE_64BIT)) { 825 CPU = "nocona"; 826 break; 827 } 828 if (testFeature(X86::FEATURE_SSE3)) { 829 CPU = "prescott"; 830 break; 831 } 832 CPU = "pentium4"; 833 break; 834 } 835 default: 836 break; // Unknown. 837 } 838 839 return CPU; 840 } 841 842 static StringRef 843 getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 844 const unsigned *Features, 845 unsigned *Type, unsigned *Subtype) { 846 auto testFeature = [&](unsigned F) { 847 return (Features[F / 32] & (1U << (F % 32))) != 0; 848 }; 849 850 StringRef CPU; 851 852 switch (Family) { 853 case 4: 854 CPU = "i486"; 855 break; 856 case 5: 857 CPU = "pentium"; 858 switch (Model) { 859 case 6: 860 case 7: 861 CPU = "k6"; 862 break; 863 case 8: 864 CPU = "k6-2"; 865 break; 866 case 9: 867 case 13: 868 CPU = "k6-3"; 869 break; 870 case 10: 871 CPU = "geode"; 872 break; 873 } 874 break; 875 case 6: 876 if (testFeature(X86::FEATURE_SSE)) { 877 CPU = "athlon-xp"; 878 break; 879 } 880 CPU = "athlon"; 881 break; 882 case 15: 883 if (testFeature(X86::FEATURE_SSE3)) { 884 CPU = "k8-sse3"; 885 break; 886 } 887 CPU = "k8"; 888 break; 889 case 16: 890 CPU = "amdfam10"; 891 *Type = X86::AMDFAM10H; // "amdfam10" 892 switch (Model) { 893 case 2: 894 *Subtype = X86::AMDFAM10H_BARCELONA; 895 break; 896 case 4: 897 *Subtype = X86::AMDFAM10H_SHANGHAI; 898 break; 899 case 8: 900 *Subtype = X86::AMDFAM10H_ISTANBUL; 901 break; 902 } 903 break; 904 case 20: 905 CPU = "btver1"; 906 *Type = X86::AMD_BTVER1; 907 break; 908 case 21: 909 CPU = "bdver1"; 910 *Type = X86::AMDFAM15H; 911 if (Model >= 0x60 && Model <= 0x7f) { 912 CPU = "bdver4"; 913 *Subtype = X86::AMDFAM15H_BDVER4; 914 break; // 60h-7Fh: Excavator 915 } 916 if (Model >= 0x30 && Model <= 0x3f) { 917 CPU = "bdver3"; 918 *Subtype = X86::AMDFAM15H_BDVER3; 919 break; // 30h-3Fh: Steamroller 920 } 921 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) { 922 CPU = "bdver2"; 923 *Subtype = X86::AMDFAM15H_BDVER2; 924 break; // 02h, 10h-1Fh: Piledriver 925 } 926 if (Model <= 0x0f) { 927 *Subtype = X86::AMDFAM15H_BDVER1; 928 break; // 00h-0Fh: Bulldozer 929 } 930 break; 931 case 22: 932 CPU = "btver2"; 933 *Type = X86::AMD_BTVER2; 934 break; 935 case 23: 936 CPU = "znver1"; 937 *Type = X86::AMDFAM17H; 938 if ((Model >= 0x30 && Model <= 0x3f) || Model == 0x71) { 939 CPU = "znver2"; 940 *Subtype = X86::AMDFAM17H_ZNVER2; 941 break; // 30h-3fh, 71h: Zen2 942 } 943 if (Model <= 0x0f) { 944 *Subtype = X86::AMDFAM17H_ZNVER1; 945 break; // 00h-0Fh: Zen1 946 } 947 break; 948 case 25: 949 CPU = "znver3"; 950 *Type = X86::AMDFAM19H; 951 if (Model <= 0x0f) { 952 *Subtype = X86::AMDFAM19H_ZNVER3; 953 break; // 00h-0Fh: Zen3 954 } 955 break; 956 default: 957 break; // Unknown AMD CPU. 958 } 959 960 return CPU; 961 } 962 963 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 964 unsigned *Features) { 965 unsigned EAX, EBX; 966 967 auto setFeature = [&](unsigned F) { 968 Features[F / 32] |= 1U << (F % 32); 969 }; 970 971 if ((EDX >> 15) & 1) 972 setFeature(X86::FEATURE_CMOV); 973 if ((EDX >> 23) & 1) 974 setFeature(X86::FEATURE_MMX); 975 if ((EDX >> 25) & 1) 976 setFeature(X86::FEATURE_SSE); 977 if ((EDX >> 26) & 1) 978 setFeature(X86::FEATURE_SSE2); 979 980 if ((ECX >> 0) & 1) 981 setFeature(X86::FEATURE_SSE3); 982 if ((ECX >> 1) & 1) 983 setFeature(X86::FEATURE_PCLMUL); 984 if ((ECX >> 9) & 1) 985 setFeature(X86::FEATURE_SSSE3); 986 if ((ECX >> 12) & 1) 987 setFeature(X86::FEATURE_FMA); 988 if ((ECX >> 19) & 1) 989 setFeature(X86::FEATURE_SSE4_1); 990 if ((ECX >> 20) & 1) 991 setFeature(X86::FEATURE_SSE4_2); 992 if ((ECX >> 23) & 1) 993 setFeature(X86::FEATURE_POPCNT); 994 if ((ECX >> 25) & 1) 995 setFeature(X86::FEATURE_AES); 996 997 if ((ECX >> 22) & 1) 998 setFeature(X86::FEATURE_MOVBE); 999 1000 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1001 // indicates that the AVX registers will be saved and restored on context 1002 // switch, then we have full AVX support. 1003 const unsigned AVXBits = (1 << 27) | (1 << 28); 1004 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 1005 ((EAX & 0x6) == 0x6); 1006 #if defined(__APPLE__) 1007 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1008 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1009 // set right now. 1010 bool HasAVX512Save = true; 1011 #else 1012 // AVX512 requires additional context to be saved by the OS. 1013 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 1014 #endif 1015 1016 if (HasAVX) 1017 setFeature(X86::FEATURE_AVX); 1018 1019 bool HasLeaf7 = 1020 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1021 1022 if (HasLeaf7 && ((EBX >> 3) & 1)) 1023 setFeature(X86::FEATURE_BMI); 1024 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 1025 setFeature(X86::FEATURE_AVX2); 1026 if (HasLeaf7 && ((EBX >> 8) & 1)) 1027 setFeature(X86::FEATURE_BMI2); 1028 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 1029 setFeature(X86::FEATURE_AVX512F); 1030 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 1031 setFeature(X86::FEATURE_AVX512DQ); 1032 if (HasLeaf7 && ((EBX >> 19) & 1)) 1033 setFeature(X86::FEATURE_ADX); 1034 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 1035 setFeature(X86::FEATURE_AVX512IFMA); 1036 if (HasLeaf7 && ((EBX >> 23) & 1)) 1037 setFeature(X86::FEATURE_CLFLUSHOPT); 1038 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 1039 setFeature(X86::FEATURE_AVX512PF); 1040 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 1041 setFeature(X86::FEATURE_AVX512ER); 1042 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 1043 setFeature(X86::FEATURE_AVX512CD); 1044 if (HasLeaf7 && ((EBX >> 29) & 1)) 1045 setFeature(X86::FEATURE_SHA); 1046 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 1047 setFeature(X86::FEATURE_AVX512BW); 1048 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 1049 setFeature(X86::FEATURE_AVX512VL); 1050 1051 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 1052 setFeature(X86::FEATURE_AVX512VBMI); 1053 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save) 1054 setFeature(X86::FEATURE_AVX512VBMI2); 1055 if (HasLeaf7 && ((ECX >> 8) & 1)) 1056 setFeature(X86::FEATURE_GFNI); 1057 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX) 1058 setFeature(X86::FEATURE_VPCLMULQDQ); 1059 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save) 1060 setFeature(X86::FEATURE_AVX512VNNI); 1061 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save) 1062 setFeature(X86::FEATURE_AVX512BITALG); 1063 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1064 setFeature(X86::FEATURE_AVX512VPOPCNTDQ); 1065 1066 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1067 setFeature(X86::FEATURE_AVX5124VNNIW); 1068 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1069 setFeature(X86::FEATURE_AVX5124FMAPS); 1070 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save) 1071 setFeature(X86::FEATURE_AVX512VP2INTERSECT); 1072 1073 bool HasLeaf7Subleaf1 = 1074 MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1075 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save) 1076 setFeature(X86::FEATURE_AVX512BF16); 1077 1078 unsigned MaxExtLevel; 1079 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1080 1081 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1082 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1083 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1084 setFeature(X86::FEATURE_SSE4_A); 1085 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1086 setFeature(X86::FEATURE_XOP); 1087 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1088 setFeature(X86::FEATURE_FMA4); 1089 1090 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1091 setFeature(X86::FEATURE_64BIT); 1092 } 1093 1094 StringRef sys::getHostCPUName() { 1095 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1096 unsigned MaxLeaf, Vendor; 1097 1098 if (!isCpuIdSupported()) 1099 return "generic"; 1100 1101 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) 1102 return "generic"; 1103 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1104 1105 unsigned Family = 0, Model = 0; 1106 unsigned Features[(X86::CPU_FEATURE_MAX + 31) / 32] = {0}; 1107 detectX86FamilyModel(EAX, &Family, &Model); 1108 getAvailableFeatures(ECX, EDX, MaxLeaf, Features); 1109 1110 // These aren't consumed in this file, but we try to keep some source code the 1111 // same or similar to compiler-rt. 1112 unsigned Type = 0; 1113 unsigned Subtype = 0; 1114 1115 StringRef CPU; 1116 1117 if (Vendor == SIG_INTEL) { 1118 CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &Type, 1119 &Subtype); 1120 } else if (Vendor == SIG_AMD) { 1121 CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, 1122 &Subtype); 1123 } 1124 1125 if (!CPU.empty()) 1126 return CPU; 1127 1128 return "generic"; 1129 } 1130 1131 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1132 StringRef sys::getHostCPUName() { 1133 host_basic_info_data_t hostInfo; 1134 mach_msg_type_number_t infoCount; 1135 1136 infoCount = HOST_BASIC_INFO_COUNT; 1137 mach_port_t hostPort = mach_host_self(); 1138 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1139 &infoCount); 1140 mach_port_deallocate(mach_task_self(), hostPort); 1141 1142 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1143 return "generic"; 1144 1145 switch (hostInfo.cpu_subtype) { 1146 case CPU_SUBTYPE_POWERPC_601: 1147 return "601"; 1148 case CPU_SUBTYPE_POWERPC_602: 1149 return "602"; 1150 case CPU_SUBTYPE_POWERPC_603: 1151 return "603"; 1152 case CPU_SUBTYPE_POWERPC_603e: 1153 return "603e"; 1154 case CPU_SUBTYPE_POWERPC_603ev: 1155 return "603ev"; 1156 case CPU_SUBTYPE_POWERPC_604: 1157 return "604"; 1158 case CPU_SUBTYPE_POWERPC_604e: 1159 return "604e"; 1160 case CPU_SUBTYPE_POWERPC_620: 1161 return "620"; 1162 case CPU_SUBTYPE_POWERPC_750: 1163 return "750"; 1164 case CPU_SUBTYPE_POWERPC_7400: 1165 return "7400"; 1166 case CPU_SUBTYPE_POWERPC_7450: 1167 return "7450"; 1168 case CPU_SUBTYPE_POWERPC_970: 1169 return "970"; 1170 default:; 1171 } 1172 1173 return "generic"; 1174 } 1175 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1176 StringRef sys::getHostCPUName() { 1177 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1178 StringRef Content = P ? P->getBuffer() : ""; 1179 return detail::getHostCPUNameForPowerPC(Content); 1180 } 1181 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1182 StringRef sys::getHostCPUName() { 1183 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1184 StringRef Content = P ? P->getBuffer() : ""; 1185 return detail::getHostCPUNameForARM(Content); 1186 } 1187 #elif defined(__linux__) && defined(__s390x__) 1188 StringRef sys::getHostCPUName() { 1189 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1190 StringRef Content = P ? P->getBuffer() : ""; 1191 return detail::getHostCPUNameForS390x(Content); 1192 } 1193 #elif defined(__APPLE__) && defined(__aarch64__) 1194 StringRef sys::getHostCPUName() { 1195 return "cyclone"; 1196 } 1197 #elif defined(__APPLE__) && defined(__arm__) 1198 StringRef sys::getHostCPUName() { 1199 host_basic_info_data_t hostInfo; 1200 mach_msg_type_number_t infoCount; 1201 1202 infoCount = HOST_BASIC_INFO_COUNT; 1203 mach_port_t hostPort = mach_host_self(); 1204 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1205 &infoCount); 1206 mach_port_deallocate(mach_task_self(), hostPort); 1207 1208 if (hostInfo.cpu_type != CPU_TYPE_ARM) { 1209 assert(false && "CPUType not equal to ARM should not be possible on ARM"); 1210 return "generic"; 1211 } 1212 switch (hostInfo.cpu_subtype) { 1213 case CPU_SUBTYPE_ARM_V7S: 1214 return "swift"; 1215 default:; 1216 } 1217 1218 return "generic"; 1219 } 1220 #else 1221 StringRef sys::getHostCPUName() { return "generic"; } 1222 #endif 1223 1224 #if defined(__linux__) && (defined(__i386__) || defined(__x86_64__)) 1225 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1226 // using the number of unique physical/core id pairs. The following 1227 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1228 int computeHostNumPhysicalCores() { 1229 // Enabled represents the number of physical id/core id pairs with at least 1230 // one processor id enabled by the CPU affinity mask. 1231 cpu_set_t Affinity, Enabled; 1232 if (sched_getaffinity(0, sizeof(Affinity), &Affinity) != 0) 1233 return -1; 1234 CPU_ZERO(&Enabled); 1235 1236 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1237 // mmapped because it appears to have 0 size. 1238 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1239 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1240 if (std::error_code EC = Text.getError()) { 1241 llvm::errs() << "Can't read " 1242 << "/proc/cpuinfo: " << EC.message() << "\n"; 1243 return -1; 1244 } 1245 SmallVector<StringRef, 8> strs; 1246 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1247 /*KeepEmpty=*/false); 1248 int CurProcessor = -1; 1249 int CurPhysicalId = -1; 1250 int CurSiblings = -1; 1251 int CurCoreId = -1; 1252 for (StringRef Line : strs) { 1253 std::pair<StringRef, StringRef> Data = Line.split(':'); 1254 auto Name = Data.first.trim(); 1255 auto Val = Data.second.trim(); 1256 // These fields are available if the kernel is configured with CONFIG_SMP. 1257 if (Name == "processor") 1258 Val.getAsInteger(10, CurProcessor); 1259 else if (Name == "physical id") 1260 Val.getAsInteger(10, CurPhysicalId); 1261 else if (Name == "siblings") 1262 Val.getAsInteger(10, CurSiblings); 1263 else if (Name == "core id") { 1264 Val.getAsInteger(10, CurCoreId); 1265 // The processor id corresponds to an index into cpu_set_t. 1266 if (CPU_ISSET(CurProcessor, &Affinity)) 1267 CPU_SET(CurPhysicalId * CurSiblings + CurCoreId, &Enabled); 1268 } 1269 } 1270 return CPU_COUNT(&Enabled); 1271 } 1272 #elif defined(__linux__) && defined(__powerpc__) 1273 int computeHostNumPhysicalCores() { 1274 cpu_set_t Affinity; 1275 if (sched_getaffinity(0, sizeof(Affinity), &Affinity) == 0) 1276 return CPU_COUNT(&Affinity); 1277 1278 // The call to sched_getaffinity() may have failed because the Affinity 1279 // mask is too small for the number of CPU's on the system (i.e. the 1280 // system has more than 1024 CPUs). Allocate a mask large enough for 1281 // twice as many CPUs. 1282 cpu_set_t *DynAffinity; 1283 DynAffinity = CPU_ALLOC(2048); 1284 if (sched_getaffinity(0, CPU_ALLOC_SIZE(2048), DynAffinity) == 0) { 1285 int NumCPUs = CPU_COUNT(DynAffinity); 1286 CPU_FREE(DynAffinity); 1287 return NumCPUs; 1288 } 1289 return -1; 1290 } 1291 #elif defined(__linux__) && defined(__s390x__) 1292 int computeHostNumPhysicalCores() { return sysconf(_SC_NPROCESSORS_ONLN); } 1293 #elif defined(__APPLE__) && defined(__x86_64__) 1294 #include <sys/param.h> 1295 #include <sys/sysctl.h> 1296 1297 // Gets the number of *physical cores* on the machine. 1298 int computeHostNumPhysicalCores() { 1299 uint32_t count; 1300 size_t len = sizeof(count); 1301 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1302 if (count < 1) { 1303 int nm[2]; 1304 nm[0] = CTL_HW; 1305 nm[1] = HW_AVAILCPU; 1306 sysctl(nm, 2, &count, &len, NULL, 0); 1307 if (count < 1) 1308 return -1; 1309 } 1310 return count; 1311 } 1312 #elif defined(__MVS__) 1313 int computeHostNumPhysicalCores() { 1314 enum { 1315 // Byte offset of the pointer to the Communications Vector Table (CVT) in 1316 // the Prefixed Save Area (PSA). The table entry is a 31-bit pointer and 1317 // will be zero-extended to uintptr_t. 1318 FLCCVT = 16, 1319 // Byte offset of the pointer to the Common System Data Area (CSD) in the 1320 // CVT. The table entry is a 31-bit pointer and will be zero-extended to 1321 // uintptr_t. 1322 CVTCSD = 660, 1323 // Byte offset to the number of live CPs in the LPAR, stored as a signed 1324 // 32-bit value in the table. 1325 CSD_NUMBER_ONLINE_STANDARD_CPS = 264, 1326 }; 1327 char *PSA = 0; 1328 char *CVT = reinterpret_cast<char *>( 1329 static_cast<uintptr_t>(reinterpret_cast<unsigned int &>(PSA[FLCCVT]))); 1330 char *CSD = reinterpret_cast<char *>( 1331 static_cast<uintptr_t>(reinterpret_cast<unsigned int &>(CVT[CVTCSD]))); 1332 return reinterpret_cast<int &>(CSD[CSD_NUMBER_ONLINE_STANDARD_CPS]); 1333 } 1334 #elif defined(_WIN32) && LLVM_ENABLE_THREADS != 0 1335 // Defined in llvm/lib/Support/Windows/Threading.inc 1336 int computeHostNumPhysicalCores(); 1337 #else 1338 // On other systems, return -1 to indicate unknown. 1339 static int computeHostNumPhysicalCores() { return -1; } 1340 #endif 1341 1342 int sys::getHostNumPhysicalCores() { 1343 static int NumCores = computeHostNumPhysicalCores(); 1344 return NumCores; 1345 } 1346 1347 #if defined(__i386__) || defined(_M_IX86) || \ 1348 defined(__x86_64__) || defined(_M_X64) 1349 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1350 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1351 unsigned MaxLevel; 1352 1353 if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1) 1354 return false; 1355 1356 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1357 1358 Features["cx8"] = (EDX >> 8) & 1; 1359 Features["cmov"] = (EDX >> 15) & 1; 1360 Features["mmx"] = (EDX >> 23) & 1; 1361 Features["fxsr"] = (EDX >> 24) & 1; 1362 Features["sse"] = (EDX >> 25) & 1; 1363 Features["sse2"] = (EDX >> 26) & 1; 1364 1365 Features["sse3"] = (ECX >> 0) & 1; 1366 Features["pclmul"] = (ECX >> 1) & 1; 1367 Features["ssse3"] = (ECX >> 9) & 1; 1368 Features["cx16"] = (ECX >> 13) & 1; 1369 Features["sse4.1"] = (ECX >> 19) & 1; 1370 Features["sse4.2"] = (ECX >> 20) & 1; 1371 Features["movbe"] = (ECX >> 22) & 1; 1372 Features["popcnt"] = (ECX >> 23) & 1; 1373 Features["aes"] = (ECX >> 25) & 1; 1374 Features["rdrnd"] = (ECX >> 30) & 1; 1375 1376 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1377 // indicates that the AVX registers will be saved and restored on context 1378 // switch, then we have full AVX support. 1379 bool HasXSave = ((ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX); 1380 bool HasAVXSave = HasXSave && ((ECX >> 28) & 1) && ((EAX & 0x6) == 0x6); 1381 #if defined(__APPLE__) 1382 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1383 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1384 // set right now. 1385 bool HasAVX512Save = true; 1386 #else 1387 // AVX512 requires additional context to be saved by the OS. 1388 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1389 #endif 1390 // AMX requires additional context to be saved by the OS. 1391 const unsigned AMXBits = (1 << 17) | (1 << 18); 1392 bool HasAMXSave = HasXSave && ((EAX & AMXBits) == AMXBits); 1393 1394 Features["avx"] = HasAVXSave; 1395 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave; 1396 // Only enable XSAVE if OS has enabled support for saving YMM state. 1397 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave; 1398 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave; 1399 1400 unsigned MaxExtLevel; 1401 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1402 1403 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1404 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1405 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1); 1406 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1407 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1408 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1409 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1410 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1411 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1412 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1413 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1414 1415 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1); 1416 1417 // Miscellaneous memory related features, detected by 1418 // using the 0x80000008 leaf of the CPUID instruction 1419 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1420 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX); 1421 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1422 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1); 1423 1424 bool HasLeaf7 = 1425 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1426 1427 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1428 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1429 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1430 // AVX2 is only supported if we have the OS save support from AVX. 1431 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave; 1432 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1433 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1434 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1435 // AVX512 is only supported if the OS supports the context save for it. 1436 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1437 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1438 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1439 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1440 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1441 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1442 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1443 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1444 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1445 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1446 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1447 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1448 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1449 1450 Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1); 1451 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1452 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1453 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1); 1454 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save; 1455 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1); 1456 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1); 1457 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave; 1458 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave; 1459 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save; 1460 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save; 1461 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1462 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1); 1463 Features["kl"] = HasLeaf7 && ((ECX >> 23) & 1); // key locker 1464 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1); 1465 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1); 1466 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1); 1467 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1); 1468 1469 Features["uintr"] = HasLeaf7 && ((EDX >> 5) & 1); 1470 Features["avx512vp2intersect"] = 1471 HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save; 1472 Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1); 1473 Features["tsxldtrk"] = HasLeaf7 && ((EDX >> 16) & 1); 1474 // There are two CPUID leafs which information associated with the pconfig 1475 // instruction: 1476 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th 1477 // bit of EDX), while the EAX=0x1b leaf returns information on the 1478 // availability of specific pconfig leafs. 1479 // The target feature here only refers to the the first of these two. 1480 // Users might need to check for the availability of specific pconfig 1481 // leaves using cpuid, since that information is ignored while 1482 // detecting features using the "-march=native" flag. 1483 // For more info, see X86 ISA docs. 1484 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1); 1485 Features["amx-bf16"] = HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave; 1486 Features["amx-tile"] = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave; 1487 Features["amx-int8"] = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave; 1488 bool HasLeaf7Subleaf1 = 1489 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1490 Features["avxvnni"] = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave; 1491 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save; 1492 Features["hreset"] = HasLeaf7Subleaf1 && ((EAX >> 22) & 1); 1493 1494 bool HasLeafD = MaxLevel >= 0xd && 1495 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1496 1497 // Only enable XSAVE if OS has enabled support for saving YMM state. 1498 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave; 1499 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave; 1500 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave; 1501 1502 bool HasLeaf14 = MaxLevel >= 0x14 && 1503 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX); 1504 1505 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1); 1506 1507 bool HasLeaf19 = 1508 MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX); 1509 Features["widekl"] = HasLeaf7 && HasLeaf19 && ((EBX >> 2) & 1); 1510 1511 return true; 1512 } 1513 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1514 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1515 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1516 if (!P) 1517 return false; 1518 1519 SmallVector<StringRef, 32> Lines; 1520 P->getBuffer().split(Lines, "\n"); 1521 1522 SmallVector<StringRef, 32> CPUFeatures; 1523 1524 // Look for the CPU features. 1525 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1526 if (Lines[I].startswith("Features")) { 1527 Lines[I].split(CPUFeatures, ' '); 1528 break; 1529 } 1530 1531 #if defined(__aarch64__) 1532 // Keep track of which crypto features we have seen 1533 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1534 uint32_t crypto = 0; 1535 #endif 1536 1537 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1538 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1539 #if defined(__aarch64__) 1540 .Case("asimd", "neon") 1541 .Case("fp", "fp-armv8") 1542 .Case("crc32", "crc") 1543 #else 1544 .Case("half", "fp16") 1545 .Case("neon", "neon") 1546 .Case("vfpv3", "vfp3") 1547 .Case("vfpv3d16", "d16") 1548 .Case("vfpv4", "vfp4") 1549 .Case("idiva", "hwdiv-arm") 1550 .Case("idivt", "hwdiv") 1551 #endif 1552 .Default(""); 1553 1554 #if defined(__aarch64__) 1555 // We need to check crypto separately since we need all of the crypto 1556 // extensions to enable the subtarget feature 1557 if (CPUFeatures[I] == "aes") 1558 crypto |= CAP_AES; 1559 else if (CPUFeatures[I] == "pmull") 1560 crypto |= CAP_PMULL; 1561 else if (CPUFeatures[I] == "sha1") 1562 crypto |= CAP_SHA1; 1563 else if (CPUFeatures[I] == "sha2") 1564 crypto |= CAP_SHA2; 1565 #endif 1566 1567 if (LLVMFeatureStr != "") 1568 Features[LLVMFeatureStr] = true; 1569 } 1570 1571 #if defined(__aarch64__) 1572 // If we have all crypto bits we can add the feature 1573 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1574 Features["crypto"] = true; 1575 #endif 1576 1577 return true; 1578 } 1579 #elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64)) 1580 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1581 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE)) 1582 Features["neon"] = true; 1583 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE)) 1584 Features["crc"] = true; 1585 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) 1586 Features["crypto"] = true; 1587 1588 return true; 1589 } 1590 #else 1591 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1592 #endif 1593 1594 std::string sys::getProcessTriple() { 1595 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1596 Triple PT(Triple::normalize(TargetTripleString)); 1597 1598 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1599 PT = PT.get64BitArchVariant(); 1600 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1601 PT = PT.get32BitArchVariant(); 1602 1603 return PT.str(); 1604 } 1605