1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the operating system Host concept. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/Host.h" 14 #include "llvm/ADT/SmallSet.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringMap.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/llvm-config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/TargetParser.h" 25 #include "llvm/Support/raw_ostream.h" 26 #include <assert.h> 27 #include <string.h> 28 29 // Include the platform-specific parts of this class. 30 #ifdef LLVM_ON_UNIX 31 #include "Unix/Host.inc" 32 #include <sched.h> 33 #endif 34 #ifdef _WIN32 35 #include "Windows/Host.inc" 36 #endif 37 #ifdef _MSC_VER 38 #include <intrin.h> 39 #endif 40 #if defined(__APPLE__) && (!defined(__x86_64__)) 41 #include <mach/host_info.h> 42 #include <mach/mach.h> 43 #include <mach/mach_host.h> 44 #include <mach/machine.h> 45 #endif 46 47 #define DEBUG_TYPE "host-detection" 48 49 //===----------------------------------------------------------------------===// 50 // 51 // Implementations of the CPU detection routines 52 // 53 //===----------------------------------------------------------------------===// 54 55 using namespace llvm; 56 57 static std::unique_ptr<llvm::MemoryBuffer> 58 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 59 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 60 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 61 if (std::error_code EC = Text.getError()) { 62 llvm::errs() << "Can't read " 63 << "/proc/cpuinfo: " << EC.message() << "\n"; 64 return nullptr; 65 } 66 return std::move(*Text); 67 } 68 69 StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) { 70 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 71 // and so we must use an operating-system interface to determine the current 72 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 73 const char *generic = "generic"; 74 75 // The cpu line is second (after the 'processor: 0' line), so if this 76 // buffer is too small then something has changed (or is wrong). 77 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 78 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 79 80 StringRef::const_iterator CIP = CPUInfoStart; 81 82 StringRef::const_iterator CPUStart = 0; 83 size_t CPULen = 0; 84 85 // We need to find the first line which starts with cpu, spaces, and a colon. 86 // After the colon, there may be some additional spaces and then the cpu type. 87 while (CIP < CPUInfoEnd && CPUStart == 0) { 88 if (CIP < CPUInfoEnd && *CIP == '\n') 89 ++CIP; 90 91 if (CIP < CPUInfoEnd && *CIP == 'c') { 92 ++CIP; 93 if (CIP < CPUInfoEnd && *CIP == 'p') { 94 ++CIP; 95 if (CIP < CPUInfoEnd && *CIP == 'u') { 96 ++CIP; 97 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 98 ++CIP; 99 100 if (CIP < CPUInfoEnd && *CIP == ':') { 101 ++CIP; 102 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 103 ++CIP; 104 105 if (CIP < CPUInfoEnd) { 106 CPUStart = CIP; 107 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 108 *CIP != ',' && *CIP != '\n')) 109 ++CIP; 110 CPULen = CIP - CPUStart; 111 } 112 } 113 } 114 } 115 } 116 117 if (CPUStart == 0) 118 while (CIP < CPUInfoEnd && *CIP != '\n') 119 ++CIP; 120 } 121 122 if (CPUStart == 0) 123 return generic; 124 125 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 126 .Case("604e", "604e") 127 .Case("604", "604") 128 .Case("7400", "7400") 129 .Case("7410", "7400") 130 .Case("7447", "7400") 131 .Case("7455", "7450") 132 .Case("G4", "g4") 133 .Case("POWER4", "970") 134 .Case("PPC970FX", "970") 135 .Case("PPC970MP", "970") 136 .Case("G5", "g5") 137 .Case("POWER5", "g5") 138 .Case("A2", "a2") 139 .Case("POWER6", "pwr6") 140 .Case("POWER7", "pwr7") 141 .Case("POWER8", "pwr8") 142 .Case("POWER8E", "pwr8") 143 .Case("POWER8NVL", "pwr8") 144 .Case("POWER9", "pwr9") 145 // FIXME: If we get a simulator or machine with the capabilities of 146 // mcpu=future, we should revisit this and add the name reported by the 147 // simulator/machine. 148 .Default(generic); 149 } 150 151 StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { 152 // The cpuid register on arm is not accessible from user space. On Linux, 153 // it is exposed through the /proc/cpuinfo file. 154 155 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 156 // in all cases. 157 SmallVector<StringRef, 32> Lines; 158 ProcCpuinfoContent.split(Lines, "\n"); 159 160 // Look for the CPU implementer line. 161 StringRef Implementer; 162 StringRef Hardware; 163 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 164 if (Lines[I].startswith("CPU implementer")) 165 Implementer = Lines[I].substr(15).ltrim("\t :"); 166 if (Lines[I].startswith("Hardware")) 167 Hardware = Lines[I].substr(8).ltrim("\t :"); 168 } 169 170 if (Implementer == "0x41") { // ARM Ltd. 171 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 172 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 173 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 174 return "cortex-a53"; 175 176 177 // Look for the CPU part line. 178 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 179 if (Lines[I].startswith("CPU part")) 180 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 181 // values correspond to the "Part number" in the CP15/c0 register. The 182 // contents are specified in the various processor manuals. 183 // This corresponds to the Main ID Register in Technical Reference Manuals. 184 // and is used in programs like sys-utils 185 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 186 .Case("0x926", "arm926ej-s") 187 .Case("0xb02", "mpcore") 188 .Case("0xb36", "arm1136j-s") 189 .Case("0xb56", "arm1156t2-s") 190 .Case("0xb76", "arm1176jz-s") 191 .Case("0xc08", "cortex-a8") 192 .Case("0xc09", "cortex-a9") 193 .Case("0xc0f", "cortex-a15") 194 .Case("0xc20", "cortex-m0") 195 .Case("0xc23", "cortex-m3") 196 .Case("0xc24", "cortex-m4") 197 .Case("0xd22", "cortex-m55") 198 .Case("0xd02", "cortex-a34") 199 .Case("0xd04", "cortex-a35") 200 .Case("0xd03", "cortex-a53") 201 .Case("0xd07", "cortex-a57") 202 .Case("0xd08", "cortex-a72") 203 .Case("0xd09", "cortex-a73") 204 .Case("0xd0a", "cortex-a75") 205 .Case("0xd0b", "cortex-a76") 206 .Default("generic"); 207 } 208 209 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium. 210 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 211 if (Lines[I].startswith("CPU part")) { 212 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 213 .Case("0x516", "thunderx2t99") 214 .Case("0x0516", "thunderx2t99") 215 .Case("0xaf", "thunderx2t99") 216 .Case("0x0af", "thunderx2t99") 217 .Case("0xa1", "thunderxt88") 218 .Case("0x0a1", "thunderxt88") 219 .Default("generic"); 220 } 221 } 222 } 223 224 if (Implementer == "0x46") { // Fujitsu Ltd. 225 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 226 if (Lines[I].startswith("CPU part")) { 227 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 228 .Case("0x001", "a64fx") 229 .Default("generic"); 230 } 231 } 232 } 233 234 if (Implementer == "0x48") // HiSilicon Technologies, Inc. 235 // Look for the CPU part line. 236 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 237 if (Lines[I].startswith("CPU part")) 238 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 239 // values correspond to the "Part number" in the CP15/c0 register. The 240 // contents are specified in the various processor manuals. 241 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 242 .Case("0xd01", "tsv110") 243 .Default("generic"); 244 245 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 246 // Look for the CPU part line. 247 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 248 if (Lines[I].startswith("CPU part")) 249 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 250 // values correspond to the "Part number" in the CP15/c0 register. The 251 // contents are specified in the various processor manuals. 252 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 253 .Case("0x06f", "krait") // APQ8064 254 .Case("0x201", "kryo") 255 .Case("0x205", "kryo") 256 .Case("0x211", "kryo") 257 .Case("0x800", "cortex-a73") 258 .Case("0x801", "cortex-a73") 259 .Case("0x802", "cortex-a73") 260 .Case("0x803", "cortex-a73") 261 .Case("0x804", "cortex-a73") 262 .Case("0x805", "cortex-a73") 263 .Case("0xc00", "falkor") 264 .Case("0xc01", "saphira") 265 .Default("generic"); 266 267 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. 268 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow 269 // any predictive pattern across variants and parts. 270 unsigned Variant = 0, Part = 0; 271 272 // Look for the CPU variant line, whose value is a 1 digit hexadecimal 273 // number, corresponding to the Variant bits in the CP15/C0 register. 274 for (auto I : Lines) 275 if (I.consume_front("CPU variant")) 276 I.ltrim("\t :").getAsInteger(0, Variant); 277 278 // Look for the CPU part line, whose value is a 3 digit hexadecimal 279 // number, corresponding to the PartNum bits in the CP15/C0 register. 280 for (auto I : Lines) 281 if (I.consume_front("CPU part")) 282 I.ltrim("\t :").getAsInteger(0, Part); 283 284 unsigned Exynos = (Variant << 12) | Part; 285 switch (Exynos) { 286 default: 287 // Default by falling through to Exynos M3. 288 LLVM_FALLTHROUGH; 289 case 0x1002: 290 return "exynos-m3"; 291 case 0x1003: 292 return "exynos-m4"; 293 } 294 } 295 296 return "generic"; 297 } 298 299 StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { 300 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 301 302 // The "processor 0:" line comes after a fair amount of other information, 303 // including a cache breakdown, but this should be plenty. 304 SmallVector<StringRef, 32> Lines; 305 ProcCpuinfoContent.split(Lines, "\n"); 306 307 // Look for the CPU features. 308 SmallVector<StringRef, 32> CPUFeatures; 309 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 310 if (Lines[I].startswith("features")) { 311 size_t Pos = Lines[I].find(":"); 312 if (Pos != StringRef::npos) { 313 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 314 break; 315 } 316 } 317 318 // We need to check for the presence of vector support independently of 319 // the machine type, since we may only use the vector register set when 320 // supported by the kernel (and hypervisor). 321 bool HaveVectorSupport = false; 322 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 323 if (CPUFeatures[I] == "vx") 324 HaveVectorSupport = true; 325 } 326 327 // Now check the processor machine type. 328 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 329 if (Lines[I].startswith("processor ")) { 330 size_t Pos = Lines[I].find("machine = "); 331 if (Pos != StringRef::npos) { 332 Pos += sizeof("machine = ") - 1; 333 unsigned int Id; 334 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 335 if (Id >= 8561 && HaveVectorSupport) 336 return "z15"; 337 if (Id >= 3906 && HaveVectorSupport) 338 return "z14"; 339 if (Id >= 2964 && HaveVectorSupport) 340 return "z13"; 341 if (Id >= 2827) 342 return "zEC12"; 343 if (Id >= 2817) 344 return "z196"; 345 } 346 } 347 break; 348 } 349 } 350 351 return "generic"; 352 } 353 354 StringRef sys::detail::getHostCPUNameForBPF() { 355 #if !defined(__linux__) || !defined(__x86_64__) 356 return "generic"; 357 #else 358 uint8_t v3_insns[40] __attribute__ ((aligned (8))) = 359 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 360 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 361 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 362 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 363 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 364 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 365 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 366 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 367 /* BPF_EXIT_INSN() */ 368 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 369 370 uint8_t v2_insns[40] __attribute__ ((aligned (8))) = 371 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 372 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 373 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 374 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 375 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 376 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 377 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 378 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 379 /* BPF_EXIT_INSN() */ 380 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 381 382 struct bpf_prog_load_attr { 383 uint32_t prog_type; 384 uint32_t insn_cnt; 385 uint64_t insns; 386 uint64_t license; 387 uint32_t log_level; 388 uint32_t log_size; 389 uint64_t log_buf; 390 uint32_t kern_version; 391 uint32_t prog_flags; 392 } attr = {}; 393 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 394 attr.insn_cnt = 5; 395 attr.insns = (uint64_t)v3_insns; 396 attr.license = (uint64_t)"DUMMY"; 397 398 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, 399 sizeof(attr)); 400 if (fd >= 0) { 401 close(fd); 402 return "v3"; 403 } 404 405 /* Clear the whole attr in case its content changed by syscall. */ 406 memset(&attr, 0, sizeof(attr)); 407 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 408 attr.insn_cnt = 5; 409 attr.insns = (uint64_t)v2_insns; 410 attr.license = (uint64_t)"DUMMY"; 411 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 412 if (fd >= 0) { 413 close(fd); 414 return "v2"; 415 } 416 return "v1"; 417 #endif 418 } 419 420 #if defined(__i386__) || defined(_M_IX86) || \ 421 defined(__x86_64__) || defined(_M_X64) 422 423 enum VendorSignatures { 424 SIG_INTEL = 0x756e6547 /* Genu */, 425 SIG_AMD = 0x68747541 /* Auth */ 426 }; 427 428 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 429 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 430 // support. Consequently, for i386, the presence of CPUID is checked first 431 // via the corresponding eflags bit. 432 // Removal of cpuid.h header motivated by PR30384 433 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 434 // or test-suite, but are used in external projects e.g. libstdcxx 435 static bool isCpuIdSupported() { 436 #if defined(__GNUC__) || defined(__clang__) 437 #if defined(__i386__) 438 int __cpuid_supported; 439 __asm__(" pushfl\n" 440 " popl %%eax\n" 441 " movl %%eax,%%ecx\n" 442 " xorl $0x00200000,%%eax\n" 443 " pushl %%eax\n" 444 " popfl\n" 445 " pushfl\n" 446 " popl %%eax\n" 447 " movl $0,%0\n" 448 " cmpl %%eax,%%ecx\n" 449 " je 1f\n" 450 " movl $1,%0\n" 451 "1:" 452 : "=r"(__cpuid_supported) 453 : 454 : "eax", "ecx"); 455 if (!__cpuid_supported) 456 return false; 457 #endif 458 return true; 459 #endif 460 return true; 461 } 462 463 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 464 /// the specified arguments. If we can't run cpuid on the host, return true. 465 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 466 unsigned *rECX, unsigned *rEDX) { 467 #if defined(__GNUC__) || defined(__clang__) 468 #if defined(__x86_64__) 469 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 470 // FIXME: should we save this for Clang? 471 __asm__("movq\t%%rbx, %%rsi\n\t" 472 "cpuid\n\t" 473 "xchgq\t%%rbx, %%rsi\n\t" 474 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 475 : "a"(value)); 476 return false; 477 #elif defined(__i386__) 478 __asm__("movl\t%%ebx, %%esi\n\t" 479 "cpuid\n\t" 480 "xchgl\t%%ebx, %%esi\n\t" 481 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 482 : "a"(value)); 483 return false; 484 #else 485 return true; 486 #endif 487 #elif defined(_MSC_VER) 488 // The MSVC intrinsic is portable across x86 and x64. 489 int registers[4]; 490 __cpuid(registers, value); 491 *rEAX = registers[0]; 492 *rEBX = registers[1]; 493 *rECX = registers[2]; 494 *rEDX = registers[3]; 495 return false; 496 #else 497 return true; 498 #endif 499 } 500 501 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 502 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 503 /// return true. 504 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 505 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 506 unsigned *rEDX) { 507 #if defined(__GNUC__) || defined(__clang__) 508 #if defined(__x86_64__) 509 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 510 // FIXME: should we save this for Clang? 511 __asm__("movq\t%%rbx, %%rsi\n\t" 512 "cpuid\n\t" 513 "xchgq\t%%rbx, %%rsi\n\t" 514 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 515 : "a"(value), "c"(subleaf)); 516 return false; 517 #elif defined(__i386__) 518 __asm__("movl\t%%ebx, %%esi\n\t" 519 "cpuid\n\t" 520 "xchgl\t%%ebx, %%esi\n\t" 521 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 522 : "a"(value), "c"(subleaf)); 523 return false; 524 #else 525 return true; 526 #endif 527 #elif defined(_MSC_VER) 528 int registers[4]; 529 __cpuidex(registers, value, subleaf); 530 *rEAX = registers[0]; 531 *rEBX = registers[1]; 532 *rECX = registers[2]; 533 *rEDX = registers[3]; 534 return false; 535 #else 536 return true; 537 #endif 538 } 539 540 // Read control register 0 (XCR0). Used to detect features such as AVX. 541 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 542 #if defined(__GNUC__) || defined(__clang__) 543 // Check xgetbv; this uses a .byte sequence instead of the instruction 544 // directly because older assemblers do not include support for xgetbv and 545 // there is no easy way to conditionally compile based on the assembler used. 546 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 547 return false; 548 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 549 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 550 *rEAX = Result; 551 *rEDX = Result >> 32; 552 return false; 553 #else 554 return true; 555 #endif 556 } 557 558 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 559 unsigned *Model) { 560 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 561 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 562 if (*Family == 6 || *Family == 0xf) { 563 if (*Family == 0xf) 564 // Examine extended family ID if family ID is F. 565 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 566 // Examine extended model ID if family ID is 6 or F. 567 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 568 } 569 } 570 571 static void 572 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 573 unsigned Brand_id, unsigned Features, 574 unsigned Features2, unsigned Features3, 575 unsigned *Type, unsigned *Subtype) { 576 if (Brand_id != 0) 577 return; 578 switch (Family) { 579 case 3: 580 *Type = X86::INTEL_i386; 581 break; 582 case 4: 583 *Type = X86::INTEL_i486; 584 break; 585 case 5: 586 if (Features & (1 << X86::FEATURE_MMX)) { 587 *Type = X86::INTEL_PENTIUM_MMX; 588 break; 589 } 590 *Type = X86::INTEL_PENTIUM; 591 break; 592 case 6: 593 switch (Model) { 594 case 0x01: // Pentium Pro processor 595 *Type = X86::INTEL_PENTIUM_PRO; 596 break; 597 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 598 // model 03 599 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 600 // model 05, and Intel Celeron processor, model 05 601 case 0x06: // Celeron processor, model 06 602 *Type = X86::INTEL_PENTIUM_II; 603 break; 604 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 605 // processor, model 07 606 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 607 // model 08, and Celeron processor, model 08 608 case 0x0a: // Pentium III Xeon processor, model 0Ah 609 case 0x0b: // Pentium III processor, model 0Bh 610 *Type = X86::INTEL_PENTIUM_III; 611 break; 612 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 613 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 614 // 0Dh. All processors are manufactured using the 90 nm process. 615 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 616 // Integrated Processor with Intel QuickAssist Technology 617 *Type = X86::INTEL_PENTIUM_M; 618 break; 619 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 620 // 0Eh. All processors are manufactured using the 65 nm process. 621 *Type = X86::INTEL_CORE_DUO; 622 break; // yonah 623 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 624 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 625 // mobile processor, Intel Core 2 Extreme processor, Intel 626 // Pentium Dual-Core processor, Intel Xeon processor, model 627 // 0Fh. All processors are manufactured using the 65 nm process. 628 case 0x16: // Intel Celeron processor model 16h. All processors are 629 // manufactured using the 65 nm process 630 *Type = X86::INTEL_CORE2; // "core2" 631 *Subtype = X86::INTEL_CORE2_65; 632 break; 633 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 634 // 17h. All processors are manufactured using the 45 nm process. 635 // 636 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 637 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 638 // the 45 nm process. 639 *Type = X86::INTEL_CORE2; // "penryn" 640 *Subtype = X86::INTEL_CORE2_45; 641 break; 642 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 643 // processors are manufactured using the 45 nm process. 644 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 645 // As found in a Summer 2010 model iMac. 646 case 0x1f: 647 case 0x2e: // Nehalem EX 648 *Type = X86::INTEL_COREI7; // "nehalem" 649 *Subtype = X86::INTEL_COREI7_NEHALEM; 650 break; 651 case 0x25: // Intel Core i7, laptop version. 652 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 653 // processors are manufactured using the 32 nm process. 654 case 0x2f: // Westmere EX 655 *Type = X86::INTEL_COREI7; // "westmere" 656 *Subtype = X86::INTEL_COREI7_WESTMERE; 657 break; 658 case 0x2a: // Intel Core i7 processor. All processors are manufactured 659 // using the 32 nm process. 660 case 0x2d: 661 *Type = X86::INTEL_COREI7; //"sandybridge" 662 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 663 break; 664 case 0x3a: 665 case 0x3e: // Ivy Bridge EP 666 *Type = X86::INTEL_COREI7; // "ivybridge" 667 *Subtype = X86::INTEL_COREI7_IVYBRIDGE; 668 break; 669 670 // Haswell: 671 case 0x3c: 672 case 0x3f: 673 case 0x45: 674 case 0x46: 675 *Type = X86::INTEL_COREI7; // "haswell" 676 *Subtype = X86::INTEL_COREI7_HASWELL; 677 break; 678 679 // Broadwell: 680 case 0x3d: 681 case 0x47: 682 case 0x4f: 683 case 0x56: 684 *Type = X86::INTEL_COREI7; // "broadwell" 685 *Subtype = X86::INTEL_COREI7_BROADWELL; 686 break; 687 688 // Skylake: 689 case 0x4e: // Skylake mobile 690 case 0x5e: // Skylake desktop 691 case 0x8e: // Kaby Lake mobile 692 case 0x9e: // Kaby Lake desktop 693 *Type = X86::INTEL_COREI7; // "skylake" 694 *Subtype = X86::INTEL_COREI7_SKYLAKE; 695 break; 696 697 // Skylake Xeon: 698 case 0x55: 699 *Type = X86::INTEL_COREI7; 700 if (Features2 & (1 << (X86::FEATURE_AVX512BF16 - 32))) 701 *Subtype = X86::INTEL_COREI7_COOPERLAKE; // "cooperlake" 702 else if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) 703 *Subtype = X86::INTEL_COREI7_CASCADELAKE; // "cascadelake" 704 else 705 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 706 break; 707 708 // Cannonlake: 709 case 0x66: 710 *Type = X86::INTEL_COREI7; 711 *Subtype = X86::INTEL_COREI7_CANNONLAKE; // "cannonlake" 712 break; 713 714 // Icelake: 715 case 0x7d: 716 case 0x7e: 717 *Type = X86::INTEL_COREI7; 718 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; // "icelake-client" 719 break; 720 721 // Icelake Xeon: 722 case 0x6a: 723 case 0x6c: 724 *Type = X86::INTEL_COREI7; 725 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; // "icelake-server" 726 break; 727 728 case 0x1c: // Most 45 nm Intel Atom processors 729 case 0x26: // 45 nm Atom Lincroft 730 case 0x27: // 32 nm Atom Medfield 731 case 0x35: // 32 nm Atom Midview 732 case 0x36: // 32 nm Atom Midview 733 *Type = X86::INTEL_BONNELL; 734 break; // "bonnell" 735 736 // Atom Silvermont codes from the Intel software optimization guide. 737 case 0x37: 738 case 0x4a: 739 case 0x4d: 740 case 0x5a: 741 case 0x5d: 742 case 0x4c: // really airmont 743 *Type = X86::INTEL_SILVERMONT; 744 break; // "silvermont" 745 // Goldmont: 746 case 0x5c: // Apollo Lake 747 case 0x5f: // Denverton 748 *Type = X86::INTEL_GOLDMONT; 749 break; // "goldmont" 750 case 0x7a: 751 *Type = X86::INTEL_GOLDMONT_PLUS; 752 break; 753 case 0x86: 754 *Type = X86::INTEL_TREMONT; 755 break; 756 757 case 0x57: 758 *Type = X86::INTEL_KNL; // knl 759 break; 760 761 case 0x85: 762 *Type = X86::INTEL_KNM; // knm 763 break; 764 765 default: // Unknown family 6 CPU, try to guess. 766 // TODO detect tigerlake host 767 if (Features3 & (1 << (X86::FEATURE_AVX512VP2INTERSECT - 64))) { 768 *Type = X86::INTEL_COREI7; 769 *Subtype = X86::INTEL_COREI7_TIGERLAKE; 770 break; 771 } 772 773 if (Features & (1 << X86::FEATURE_AVX512VBMI2)) { 774 *Type = X86::INTEL_COREI7; 775 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; 776 break; 777 } 778 779 if (Features & (1 << X86::FEATURE_AVX512VBMI)) { 780 *Type = X86::INTEL_COREI7; 781 *Subtype = X86::INTEL_COREI7_CANNONLAKE; 782 break; 783 } 784 785 if (Features2 & (1 << (X86::FEATURE_AVX512BF16 - 32))) { 786 *Type = X86::INTEL_COREI7; 787 *Subtype = X86::INTEL_COREI7_COOPERLAKE; 788 break; 789 } 790 791 if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) { 792 *Type = X86::INTEL_COREI7; 793 *Subtype = X86::INTEL_COREI7_CASCADELAKE; 794 break; 795 } 796 797 if (Features & (1 << X86::FEATURE_AVX512VL)) { 798 *Type = X86::INTEL_COREI7; 799 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; 800 break; 801 } 802 803 if (Features & (1 << X86::FEATURE_AVX512ER)) { 804 *Type = X86::INTEL_KNL; // knl 805 break; 806 } 807 808 if (Features3 & (1 << (X86::FEATURE_CLFLUSHOPT - 64))) { 809 if (Features3 & (1 << (X86::FEATURE_SHA - 64))) { 810 *Type = X86::INTEL_GOLDMONT; 811 } else { 812 *Type = X86::INTEL_COREI7; 813 *Subtype = X86::INTEL_COREI7_SKYLAKE; 814 } 815 break; 816 } 817 if (Features3 & (1 << (X86::FEATURE_ADX - 64))) { 818 *Type = X86::INTEL_COREI7; 819 *Subtype = X86::INTEL_COREI7_BROADWELL; 820 break; 821 } 822 if (Features & (1 << X86::FEATURE_AVX2)) { 823 *Type = X86::INTEL_COREI7; 824 *Subtype = X86::INTEL_COREI7_HASWELL; 825 break; 826 } 827 if (Features & (1 << X86::FEATURE_AVX)) { 828 *Type = X86::INTEL_COREI7; 829 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 830 break; 831 } 832 if (Features & (1 << X86::FEATURE_SSE4_2)) { 833 if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { 834 *Type = X86::INTEL_SILVERMONT; 835 } else { 836 *Type = X86::INTEL_COREI7; 837 *Subtype = X86::INTEL_COREI7_NEHALEM; 838 } 839 break; 840 } 841 if (Features & (1 << X86::FEATURE_SSE4_1)) { 842 *Type = X86::INTEL_CORE2; // "penryn" 843 *Subtype = X86::INTEL_CORE2_45; 844 break; 845 } 846 if (Features & (1 << X86::FEATURE_SSSE3)) { 847 if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { 848 *Type = X86::INTEL_BONNELL; // "bonnell" 849 } else { 850 *Type = X86::INTEL_CORE2; // "core2" 851 *Subtype = X86::INTEL_CORE2_65; 852 } 853 break; 854 } 855 if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { 856 *Type = X86::INTEL_CORE2; // "core2" 857 *Subtype = X86::INTEL_CORE2_65; 858 break; 859 } 860 if (Features & (1 << X86::FEATURE_SSE3)) { 861 *Type = X86::INTEL_CORE_DUO; 862 break; 863 } 864 if (Features & (1 << X86::FEATURE_SSE2)) { 865 *Type = X86::INTEL_PENTIUM_M; 866 break; 867 } 868 if (Features & (1 << X86::FEATURE_SSE)) { 869 *Type = X86::INTEL_PENTIUM_III; 870 break; 871 } 872 if (Features & (1 << X86::FEATURE_MMX)) { 873 *Type = X86::INTEL_PENTIUM_II; 874 break; 875 } 876 *Type = X86::INTEL_PENTIUM_PRO; 877 break; 878 } 879 break; 880 case 15: { 881 if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { 882 *Type = X86::INTEL_NOCONA; 883 break; 884 } 885 if (Features & (1 << X86::FEATURE_SSE3)) { 886 *Type = X86::INTEL_PRESCOTT; 887 break; 888 } 889 *Type = X86::INTEL_PENTIUM_IV; 890 break; 891 } 892 default: 893 break; /*"generic"*/ 894 } 895 } 896 897 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 898 unsigned Features, unsigned *Type, 899 unsigned *Subtype) { 900 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 901 // appears to be no way to generate the wide variety of AMD-specific targets 902 // from the information returned from CPUID. 903 switch (Family) { 904 case 4: 905 *Type = X86::AMD_i486; 906 break; 907 case 5: 908 *Type = X86::AMDPENTIUM; 909 switch (Model) { 910 case 6: 911 case 7: 912 *Subtype = X86::AMDPENTIUM_K6; 913 break; // "k6" 914 case 8: 915 *Subtype = X86::AMDPENTIUM_K62; 916 break; // "k6-2" 917 case 9: 918 case 13: 919 *Subtype = X86::AMDPENTIUM_K63; 920 break; // "k6-3" 921 case 10: 922 *Subtype = X86::AMDPENTIUM_GEODE; 923 break; // "geode" 924 } 925 break; 926 case 6: 927 if (Features & (1 << X86::FEATURE_SSE)) { 928 *Type = X86::AMD_ATHLON_XP; 929 break; // "athlon-xp" 930 } 931 *Type = X86::AMD_ATHLON; 932 break; // "athlon" 933 case 15: 934 if (Features & (1 << X86::FEATURE_SSE3)) { 935 *Type = X86::AMD_K8SSE3; 936 break; // "k8-sse3" 937 } 938 *Type = X86::AMD_K8; 939 break; // "k8" 940 case 16: 941 *Type = X86::AMDFAM10H; // "amdfam10" 942 switch (Model) { 943 case 2: 944 *Subtype = X86::AMDFAM10H_BARCELONA; 945 break; 946 case 4: 947 *Subtype = X86::AMDFAM10H_SHANGHAI; 948 break; 949 case 8: 950 *Subtype = X86::AMDFAM10H_ISTANBUL; 951 break; 952 } 953 break; 954 case 20: 955 *Type = X86::AMD_BTVER1; 956 break; // "btver1"; 957 case 21: 958 *Type = X86::AMDFAM15H; 959 if (Model >= 0x60 && Model <= 0x7f) { 960 *Subtype = X86::AMDFAM15H_BDVER4; 961 break; // "bdver4"; 60h-7Fh: Excavator 962 } 963 if (Model >= 0x30 && Model <= 0x3f) { 964 *Subtype = X86::AMDFAM15H_BDVER3; 965 break; // "bdver3"; 30h-3Fh: Steamroller 966 } 967 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) { 968 *Subtype = X86::AMDFAM15H_BDVER2; 969 break; // "bdver2"; 02h, 10h-1Fh: Piledriver 970 } 971 if (Model <= 0x0f) { 972 *Subtype = X86::AMDFAM15H_BDVER1; 973 break; // "bdver1"; 00h-0Fh: Bulldozer 974 } 975 break; 976 case 22: 977 *Type = X86::AMD_BTVER2; 978 break; // "btver2" 979 case 23: 980 *Type = X86::AMDFAM17H; 981 if ((Model >= 0x30 && Model <= 0x3f) || Model == 0x71) { 982 *Subtype = X86::AMDFAM17H_ZNVER2; 983 break; // "znver2"; 30h-3fh, 71h: Zen2 984 } 985 if (Model <= 0x0f) { 986 *Subtype = X86::AMDFAM17H_ZNVER1; 987 break; // "znver1"; 00h-0Fh: Zen1 988 } 989 break; 990 default: 991 break; // "generic" 992 } 993 } 994 995 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 996 unsigned *FeaturesOut, unsigned *Features2Out, 997 unsigned *Features3Out) { 998 unsigned Features = 0; 999 unsigned Features2 = 0; 1000 unsigned Features3 = 0; 1001 unsigned EAX, EBX; 1002 1003 auto setFeature = [&](unsigned F) { 1004 if (F < 32) 1005 Features |= 1U << (F & 0x1f); 1006 else if (F < 64) 1007 Features2 |= 1U << ((F - 32) & 0x1f); 1008 else if (F < 96) 1009 Features3 |= 1U << ((F - 64) & 0x1f); 1010 else 1011 llvm_unreachable("Unexpected FeatureBit"); 1012 }; 1013 1014 if ((EDX >> 15) & 1) 1015 setFeature(X86::FEATURE_CMOV); 1016 if ((EDX >> 23) & 1) 1017 setFeature(X86::FEATURE_MMX); 1018 if ((EDX >> 25) & 1) 1019 setFeature(X86::FEATURE_SSE); 1020 if ((EDX >> 26) & 1) 1021 setFeature(X86::FEATURE_SSE2); 1022 1023 if ((ECX >> 0) & 1) 1024 setFeature(X86::FEATURE_SSE3); 1025 if ((ECX >> 1) & 1) 1026 setFeature(X86::FEATURE_PCLMUL); 1027 if ((ECX >> 9) & 1) 1028 setFeature(X86::FEATURE_SSSE3); 1029 if ((ECX >> 12) & 1) 1030 setFeature(X86::FEATURE_FMA); 1031 if ((ECX >> 19) & 1) 1032 setFeature(X86::FEATURE_SSE4_1); 1033 if ((ECX >> 20) & 1) 1034 setFeature(X86::FEATURE_SSE4_2); 1035 if ((ECX >> 23) & 1) 1036 setFeature(X86::FEATURE_POPCNT); 1037 if ((ECX >> 25) & 1) 1038 setFeature(X86::FEATURE_AES); 1039 1040 if ((ECX >> 22) & 1) 1041 setFeature(X86::FEATURE_MOVBE); 1042 1043 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1044 // indicates that the AVX registers will be saved and restored on context 1045 // switch, then we have full AVX support. 1046 const unsigned AVXBits = (1 << 27) | (1 << 28); 1047 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 1048 ((EAX & 0x6) == 0x6); 1049 #if defined(__APPLE__) 1050 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1051 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1052 // set right now. 1053 bool HasAVX512Save = true; 1054 #else 1055 // AVX512 requires additional context to be saved by the OS. 1056 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 1057 #endif 1058 1059 if (HasAVX) 1060 setFeature(X86::FEATURE_AVX); 1061 1062 bool HasLeaf7 = 1063 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1064 1065 if (HasLeaf7 && ((EBX >> 3) & 1)) 1066 setFeature(X86::FEATURE_BMI); 1067 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 1068 setFeature(X86::FEATURE_AVX2); 1069 if (HasLeaf7 && ((EBX >> 8) & 1)) 1070 setFeature(X86::FEATURE_BMI2); 1071 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 1072 setFeature(X86::FEATURE_AVX512F); 1073 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 1074 setFeature(X86::FEATURE_AVX512DQ); 1075 if (HasLeaf7 && ((EBX >> 19) & 1)) 1076 setFeature(X86::FEATURE_ADX); 1077 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 1078 setFeature(X86::FEATURE_AVX512IFMA); 1079 if (HasLeaf7 && ((EBX >> 23) & 1)) 1080 setFeature(X86::FEATURE_CLFLUSHOPT); 1081 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 1082 setFeature(X86::FEATURE_AVX512PF); 1083 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 1084 setFeature(X86::FEATURE_AVX512ER); 1085 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 1086 setFeature(X86::FEATURE_AVX512CD); 1087 if (HasLeaf7 && ((EBX >> 29) & 1)) 1088 setFeature(X86::FEATURE_SHA); 1089 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 1090 setFeature(X86::FEATURE_AVX512BW); 1091 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 1092 setFeature(X86::FEATURE_AVX512VL); 1093 1094 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 1095 setFeature(X86::FEATURE_AVX512VBMI); 1096 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save) 1097 setFeature(X86::FEATURE_AVX512VBMI2); 1098 if (HasLeaf7 && ((ECX >> 8) & 1)) 1099 setFeature(X86::FEATURE_GFNI); 1100 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX) 1101 setFeature(X86::FEATURE_VPCLMULQDQ); 1102 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save) 1103 setFeature(X86::FEATURE_AVX512VNNI); 1104 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save) 1105 setFeature(X86::FEATURE_AVX512BITALG); 1106 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1107 setFeature(X86::FEATURE_AVX512VPOPCNTDQ); 1108 1109 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1110 setFeature(X86::FEATURE_AVX5124VNNIW); 1111 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1112 setFeature(X86::FEATURE_AVX5124FMAPS); 1113 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save) 1114 setFeature(X86::FEATURE_AVX512VP2INTERSECT); 1115 1116 bool HasLeaf7Subleaf1 = 1117 MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1118 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save) 1119 setFeature(X86::FEATURE_AVX512BF16); 1120 1121 unsigned MaxExtLevel; 1122 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1123 1124 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1125 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1126 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1127 setFeature(X86::FEATURE_SSE4_A); 1128 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1129 setFeature(X86::FEATURE_XOP); 1130 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1131 setFeature(X86::FEATURE_FMA4); 1132 1133 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1134 setFeature(X86::FEATURE_EM64T); 1135 1136 *FeaturesOut = Features; 1137 *Features2Out = Features2; 1138 *Features3Out = Features3; 1139 } 1140 1141 StringRef sys::getHostCPUName() { 1142 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1143 unsigned MaxLeaf, Vendor; 1144 1145 #if defined(__GNUC__) || defined(__clang__) 1146 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here 1147 // and simplify it to not invoke __cpuid (like cpu_model.c in 1148 // compiler-rt/lib/builtins/cpu_model.c? 1149 // Opting for the second option. 1150 if(!isCpuIdSupported()) 1151 return "generic"; 1152 #endif 1153 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) 1154 return "generic"; 1155 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1156 1157 unsigned Brand_id = EBX & 0xff; 1158 unsigned Family = 0, Model = 0; 1159 unsigned Features = 0, Features2 = 0, Features3 = 0; 1160 detectX86FamilyModel(EAX, &Family, &Model); 1161 getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2, &Features3); 1162 1163 unsigned Type = 0; 1164 unsigned Subtype = 0; 1165 1166 if (Vendor == SIG_INTEL) { 1167 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, 1168 Features2, Features3, &Type, &Subtype); 1169 } else if (Vendor == SIG_AMD) { 1170 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1171 } 1172 1173 // Check subtypes first since those are more specific. 1174 #define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \ 1175 if (Subtype == X86::ENUM) \ 1176 return ARCHNAME; 1177 #include "llvm/Support/X86TargetParser.def" 1178 1179 // Now check types. 1180 #define X86_CPU_TYPE(ARCHNAME, ENUM) \ 1181 if (Type == X86::ENUM) \ 1182 return ARCHNAME; 1183 #include "llvm/Support/X86TargetParser.def" 1184 1185 return "generic"; 1186 } 1187 1188 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1189 StringRef sys::getHostCPUName() { 1190 host_basic_info_data_t hostInfo; 1191 mach_msg_type_number_t infoCount; 1192 1193 infoCount = HOST_BASIC_INFO_COUNT; 1194 mach_port_t hostPort = mach_host_self(); 1195 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1196 &infoCount); 1197 mach_port_deallocate(mach_task_self(), hostPort); 1198 1199 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1200 return "generic"; 1201 1202 switch (hostInfo.cpu_subtype) { 1203 case CPU_SUBTYPE_POWERPC_601: 1204 return "601"; 1205 case CPU_SUBTYPE_POWERPC_602: 1206 return "602"; 1207 case CPU_SUBTYPE_POWERPC_603: 1208 return "603"; 1209 case CPU_SUBTYPE_POWERPC_603e: 1210 return "603e"; 1211 case CPU_SUBTYPE_POWERPC_603ev: 1212 return "603ev"; 1213 case CPU_SUBTYPE_POWERPC_604: 1214 return "604"; 1215 case CPU_SUBTYPE_POWERPC_604e: 1216 return "604e"; 1217 case CPU_SUBTYPE_POWERPC_620: 1218 return "620"; 1219 case CPU_SUBTYPE_POWERPC_750: 1220 return "750"; 1221 case CPU_SUBTYPE_POWERPC_7400: 1222 return "7400"; 1223 case CPU_SUBTYPE_POWERPC_7450: 1224 return "7450"; 1225 case CPU_SUBTYPE_POWERPC_970: 1226 return "970"; 1227 default:; 1228 } 1229 1230 return "generic"; 1231 } 1232 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1233 StringRef sys::getHostCPUName() { 1234 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1235 StringRef Content = P ? P->getBuffer() : ""; 1236 return detail::getHostCPUNameForPowerPC(Content); 1237 } 1238 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1239 StringRef sys::getHostCPUName() { 1240 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1241 StringRef Content = P ? P->getBuffer() : ""; 1242 return detail::getHostCPUNameForARM(Content); 1243 } 1244 #elif defined(__linux__) && defined(__s390x__) 1245 StringRef sys::getHostCPUName() { 1246 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1247 StringRef Content = P ? P->getBuffer() : ""; 1248 return detail::getHostCPUNameForS390x(Content); 1249 } 1250 #elif defined(__APPLE__) && defined(__aarch64__) 1251 StringRef sys::getHostCPUName() { 1252 return "cyclone"; 1253 } 1254 #elif defined(__APPLE__) && defined(__arm__) 1255 StringRef sys::getHostCPUName() { 1256 host_basic_info_data_t hostInfo; 1257 mach_msg_type_number_t infoCount; 1258 1259 infoCount = HOST_BASIC_INFO_COUNT; 1260 mach_port_t hostPort = mach_host_self(); 1261 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1262 &infoCount); 1263 mach_port_deallocate(mach_task_self(), hostPort); 1264 1265 if (hostInfo.cpu_type != CPU_TYPE_ARM) { 1266 assert(false && "CPUType not equal to ARM should not be possible on ARM"); 1267 return "generic"; 1268 } 1269 switch (hostInfo.cpu_subtype) { 1270 case CPU_SUBTYPE_ARM_V7S: 1271 return "swift"; 1272 default:; 1273 } 1274 1275 return "generic"; 1276 } 1277 #else 1278 StringRef sys::getHostCPUName() { return "generic"; } 1279 #endif 1280 1281 #if defined(__linux__) && (defined(__i386__) || defined(__x86_64__)) 1282 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1283 // using the number of unique physical/core id pairs. The following 1284 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1285 int computeHostNumPhysicalCores() { 1286 // Enabled represents the number of physical id/core id pairs with at least 1287 // one processor id enabled by the CPU affinity mask. 1288 cpu_set_t Affinity, Enabled; 1289 if (sched_getaffinity(0, sizeof(Affinity), &Affinity) != 0) 1290 return -1; 1291 CPU_ZERO(&Enabled); 1292 1293 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1294 // mmapped because it appears to have 0 size. 1295 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1296 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1297 if (std::error_code EC = Text.getError()) { 1298 llvm::errs() << "Can't read " 1299 << "/proc/cpuinfo: " << EC.message() << "\n"; 1300 return -1; 1301 } 1302 SmallVector<StringRef, 8> strs; 1303 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1304 /*KeepEmpty=*/false); 1305 int CurProcessor = -1; 1306 int CurPhysicalId = -1; 1307 int CurSiblings = -1; 1308 int CurCoreId = -1; 1309 for (StringRef Line : strs) { 1310 std::pair<StringRef, StringRef> Data = Line.split(':'); 1311 auto Name = Data.first.trim(); 1312 auto Val = Data.second.trim(); 1313 // These fields are available if the kernel is configured with CONFIG_SMP. 1314 if (Name == "processor") 1315 Val.getAsInteger(10, CurProcessor); 1316 else if (Name == "physical id") 1317 Val.getAsInteger(10, CurPhysicalId); 1318 else if (Name == "siblings") 1319 Val.getAsInteger(10, CurSiblings); 1320 else if (Name == "core id") { 1321 Val.getAsInteger(10, CurCoreId); 1322 // The processor id corresponds to an index into cpu_set_t. 1323 if (CPU_ISSET(CurProcessor, &Affinity)) 1324 CPU_SET(CurPhysicalId * CurSiblings + CurCoreId, &Enabled); 1325 } 1326 } 1327 return CPU_COUNT(&Enabled); 1328 } 1329 #elif defined(__APPLE__) && defined(__x86_64__) 1330 #include <sys/param.h> 1331 #include <sys/sysctl.h> 1332 1333 // Gets the number of *physical cores* on the machine. 1334 int computeHostNumPhysicalCores() { 1335 uint32_t count; 1336 size_t len = sizeof(count); 1337 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1338 if (count < 1) { 1339 int nm[2]; 1340 nm[0] = CTL_HW; 1341 nm[1] = HW_AVAILCPU; 1342 sysctl(nm, 2, &count, &len, NULL, 0); 1343 if (count < 1) 1344 return -1; 1345 } 1346 return count; 1347 } 1348 #elif defined(_WIN32) && LLVM_ENABLE_THREADS != 0 1349 // Defined in llvm/lib/Support/Windows/Threading.inc 1350 int computeHostNumPhysicalCores(); 1351 #else 1352 // On other systems, return -1 to indicate unknown. 1353 static int computeHostNumPhysicalCores() { return -1; } 1354 #endif 1355 1356 int sys::getHostNumPhysicalCores() { 1357 static int NumCores = computeHostNumPhysicalCores(); 1358 return NumCores; 1359 } 1360 1361 #if defined(__i386__) || defined(_M_IX86) || \ 1362 defined(__x86_64__) || defined(_M_X64) 1363 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1364 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1365 unsigned MaxLevel; 1366 union { 1367 unsigned u[3]; 1368 char c[12]; 1369 } text; 1370 1371 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1372 MaxLevel < 1) 1373 return false; 1374 1375 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1376 1377 Features["cx8"] = (EDX >> 8) & 1; 1378 Features["cmov"] = (EDX >> 15) & 1; 1379 Features["mmx"] = (EDX >> 23) & 1; 1380 Features["fxsr"] = (EDX >> 24) & 1; 1381 Features["sse"] = (EDX >> 25) & 1; 1382 Features["sse2"] = (EDX >> 26) & 1; 1383 1384 Features["sse3"] = (ECX >> 0) & 1; 1385 Features["pclmul"] = (ECX >> 1) & 1; 1386 Features["ssse3"] = (ECX >> 9) & 1; 1387 Features["cx16"] = (ECX >> 13) & 1; 1388 Features["sse4.1"] = (ECX >> 19) & 1; 1389 Features["sse4.2"] = (ECX >> 20) & 1; 1390 Features["movbe"] = (ECX >> 22) & 1; 1391 Features["popcnt"] = (ECX >> 23) & 1; 1392 Features["aes"] = (ECX >> 25) & 1; 1393 Features["rdrnd"] = (ECX >> 30) & 1; 1394 1395 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1396 // indicates that the AVX registers will be saved and restored on context 1397 // switch, then we have full AVX support. 1398 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1399 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1400 #if defined(__APPLE__) 1401 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1402 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1403 // set right now. 1404 bool HasAVX512Save = true; 1405 #else 1406 // AVX512 requires additional context to be saved by the OS. 1407 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1408 #endif 1409 1410 Features["avx"] = HasAVXSave; 1411 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave; 1412 // Only enable XSAVE if OS has enabled support for saving YMM state. 1413 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave; 1414 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave; 1415 1416 unsigned MaxExtLevel; 1417 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1418 1419 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1420 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1421 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1); 1422 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1423 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1424 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1425 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1426 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1427 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1428 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1429 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1430 1431 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1); 1432 1433 // Miscellaneous memory related features, detected by 1434 // using the 0x80000008 leaf of the CPUID instruction 1435 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1436 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX); 1437 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1438 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1); 1439 1440 bool HasLeaf7 = 1441 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1442 1443 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1444 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1445 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1446 // AVX2 is only supported if we have the OS save support from AVX. 1447 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave; 1448 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1449 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1450 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1451 // AVX512 is only supported if the OS supports the context save for it. 1452 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1453 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1454 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1455 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1456 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1457 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1458 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1459 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1460 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1461 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1462 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1463 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1464 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1465 1466 Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1); 1467 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1468 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1469 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1); 1470 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save; 1471 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1); 1472 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1); 1473 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave; 1474 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave; 1475 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save; 1476 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save; 1477 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1478 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1); 1479 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1); 1480 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1); 1481 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1); 1482 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1); 1483 1484 Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1); 1485 Features["tsxldtrk"] = HasLeaf7 && ((EDX >> 16) & 1); 1486 // There are two CPUID leafs which information associated with the pconfig 1487 // instruction: 1488 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th 1489 // bit of EDX), while the EAX=0x1b leaf returns information on the 1490 // availability of specific pconfig leafs. 1491 // The target feature here only refers to the the first of these two. 1492 // Users might need to check for the availability of specific pconfig 1493 // leaves using cpuid, since that information is ignored while 1494 // detecting features using the "-march=native" flag. 1495 // For more info, see X86 ISA docs. 1496 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1); 1497 bool HasLeaf7Subleaf1 = 1498 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1499 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save; 1500 1501 bool HasLeafD = MaxLevel >= 0xd && 1502 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1503 1504 // Only enable XSAVE if OS has enabled support for saving YMM state. 1505 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave; 1506 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave; 1507 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave; 1508 1509 bool HasLeaf14 = MaxLevel >= 0x14 && 1510 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX); 1511 1512 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1); 1513 1514 return true; 1515 } 1516 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1517 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1518 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1519 if (!P) 1520 return false; 1521 1522 SmallVector<StringRef, 32> Lines; 1523 P->getBuffer().split(Lines, "\n"); 1524 1525 SmallVector<StringRef, 32> CPUFeatures; 1526 1527 // Look for the CPU features. 1528 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1529 if (Lines[I].startswith("Features")) { 1530 Lines[I].split(CPUFeatures, ' '); 1531 break; 1532 } 1533 1534 #if defined(__aarch64__) 1535 // Keep track of which crypto features we have seen 1536 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1537 uint32_t crypto = 0; 1538 #endif 1539 1540 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1541 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1542 #if defined(__aarch64__) 1543 .Case("asimd", "neon") 1544 .Case("fp", "fp-armv8") 1545 .Case("crc32", "crc") 1546 #else 1547 .Case("half", "fp16") 1548 .Case("neon", "neon") 1549 .Case("vfpv3", "vfp3") 1550 .Case("vfpv3d16", "d16") 1551 .Case("vfpv4", "vfp4") 1552 .Case("idiva", "hwdiv-arm") 1553 .Case("idivt", "hwdiv") 1554 #endif 1555 .Default(""); 1556 1557 #if defined(__aarch64__) 1558 // We need to check crypto separately since we need all of the crypto 1559 // extensions to enable the subtarget feature 1560 if (CPUFeatures[I] == "aes") 1561 crypto |= CAP_AES; 1562 else if (CPUFeatures[I] == "pmull") 1563 crypto |= CAP_PMULL; 1564 else if (CPUFeatures[I] == "sha1") 1565 crypto |= CAP_SHA1; 1566 else if (CPUFeatures[I] == "sha2") 1567 crypto |= CAP_SHA2; 1568 #endif 1569 1570 if (LLVMFeatureStr != "") 1571 Features[LLVMFeatureStr] = true; 1572 } 1573 1574 #if defined(__aarch64__) 1575 // If we have all crypto bits we can add the feature 1576 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1577 Features["crypto"] = true; 1578 #endif 1579 1580 return true; 1581 } 1582 #elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64)) 1583 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1584 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE)) 1585 Features["neon"] = true; 1586 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE)) 1587 Features["crc"] = true; 1588 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) 1589 Features["crypto"] = true; 1590 1591 return true; 1592 } 1593 #else 1594 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1595 #endif 1596 1597 std::string sys::getProcessTriple() { 1598 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1599 Triple PT(Triple::normalize(TargetTripleString)); 1600 1601 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1602 PT = PT.get64BitArchVariant(); 1603 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1604 PT = PT.get32BitArchVariant(); 1605 1606 return PT.str(); 1607 } 1608