1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the operating system Host concept. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/Host.h" 14 #include "llvm/Support/TargetParser.h" 15 #include "llvm/ADT/SmallSet.h" 16 #include "llvm/ADT/SmallVector.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/llvm-config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include <assert.h> 26 #include <string.h> 27 28 // Include the platform-specific parts of this class. 29 #ifdef LLVM_ON_UNIX 30 #include "Unix/Host.inc" 31 #endif 32 #ifdef _WIN32 33 #include "Windows/Host.inc" 34 #endif 35 #ifdef _MSC_VER 36 #include <intrin.h> 37 #endif 38 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 39 #include <mach/host_info.h> 40 #include <mach/mach.h> 41 #include <mach/mach_host.h> 42 #include <mach/machine.h> 43 #endif 44 45 #define DEBUG_TYPE "host-detection" 46 47 //===----------------------------------------------------------------------===// 48 // 49 // Implementations of the CPU detection routines 50 // 51 //===----------------------------------------------------------------------===// 52 53 using namespace llvm; 54 55 static std::unique_ptr<llvm::MemoryBuffer> 56 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 57 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 58 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 59 if (std::error_code EC = Text.getError()) { 60 llvm::errs() << "Can't read " 61 << "/proc/cpuinfo: " << EC.message() << "\n"; 62 return nullptr; 63 } 64 return std::move(*Text); 65 } 66 67 StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) { 68 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 69 // and so we must use an operating-system interface to determine the current 70 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 71 const char *generic = "generic"; 72 73 // The cpu line is second (after the 'processor: 0' line), so if this 74 // buffer is too small then something has changed (or is wrong). 75 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 76 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 77 78 StringRef::const_iterator CIP = CPUInfoStart; 79 80 StringRef::const_iterator CPUStart = 0; 81 size_t CPULen = 0; 82 83 // We need to find the first line which starts with cpu, spaces, and a colon. 84 // After the colon, there may be some additional spaces and then the cpu type. 85 while (CIP < CPUInfoEnd && CPUStart == 0) { 86 if (CIP < CPUInfoEnd && *CIP == '\n') 87 ++CIP; 88 89 if (CIP < CPUInfoEnd && *CIP == 'c') { 90 ++CIP; 91 if (CIP < CPUInfoEnd && *CIP == 'p') { 92 ++CIP; 93 if (CIP < CPUInfoEnd && *CIP == 'u') { 94 ++CIP; 95 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 96 ++CIP; 97 98 if (CIP < CPUInfoEnd && *CIP == ':') { 99 ++CIP; 100 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 101 ++CIP; 102 103 if (CIP < CPUInfoEnd) { 104 CPUStart = CIP; 105 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 106 *CIP != ',' && *CIP != '\n')) 107 ++CIP; 108 CPULen = CIP - CPUStart; 109 } 110 } 111 } 112 } 113 } 114 115 if (CPUStart == 0) 116 while (CIP < CPUInfoEnd && *CIP != '\n') 117 ++CIP; 118 } 119 120 if (CPUStart == 0) 121 return generic; 122 123 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 124 .Case("604e", "604e") 125 .Case("604", "604") 126 .Case("7400", "7400") 127 .Case("7410", "7400") 128 .Case("7447", "7400") 129 .Case("7455", "7450") 130 .Case("G4", "g4") 131 .Case("POWER4", "970") 132 .Case("PPC970FX", "970") 133 .Case("PPC970MP", "970") 134 .Case("G5", "g5") 135 .Case("POWER5", "g5") 136 .Case("A2", "a2") 137 .Case("POWER6", "pwr6") 138 .Case("POWER7", "pwr7") 139 .Case("POWER8", "pwr8") 140 .Case("POWER8E", "pwr8") 141 .Case("POWER8NVL", "pwr8") 142 .Case("POWER9", "pwr9") 143 .Default(generic); 144 } 145 146 StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { 147 // The cpuid register on arm is not accessible from user space. On Linux, 148 // it is exposed through the /proc/cpuinfo file. 149 150 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 151 // in all cases. 152 SmallVector<StringRef, 32> Lines; 153 ProcCpuinfoContent.split(Lines, "\n"); 154 155 // Look for the CPU implementer line. 156 StringRef Implementer; 157 StringRef Hardware; 158 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 159 if (Lines[I].startswith("CPU implementer")) 160 Implementer = Lines[I].substr(15).ltrim("\t :"); 161 if (Lines[I].startswith("Hardware")) 162 Hardware = Lines[I].substr(8).ltrim("\t :"); 163 } 164 165 if (Implementer == "0x41") { // ARM Ltd. 166 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 167 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 168 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 169 return "cortex-a53"; 170 171 172 // Look for the CPU part line. 173 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 174 if (Lines[I].startswith("CPU part")) 175 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 176 // values correspond to the "Part number" in the CP15/c0 register. The 177 // contents are specified in the various processor manuals. 178 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 179 .Case("0x926", "arm926ej-s") 180 .Case("0xb02", "mpcore") 181 .Case("0xb36", "arm1136j-s") 182 .Case("0xb56", "arm1156t2-s") 183 .Case("0xb76", "arm1176jz-s") 184 .Case("0xc08", "cortex-a8") 185 .Case("0xc09", "cortex-a9") 186 .Case("0xc0f", "cortex-a15") 187 .Case("0xc20", "cortex-m0") 188 .Case("0xc23", "cortex-m3") 189 .Case("0xc24", "cortex-m4") 190 .Case("0xd04", "cortex-a35") 191 .Case("0xd03", "cortex-a53") 192 .Case("0xd07", "cortex-a57") 193 .Case("0xd08", "cortex-a72") 194 .Case("0xd09", "cortex-a73") 195 .Default("generic"); 196 } 197 198 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium. 199 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 200 if (Lines[I].startswith("CPU part")) { 201 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 202 .Case("0x516", "thunderx2t99") 203 .Case("0x0516", "thunderx2t99") 204 .Case("0xaf", "thunderx2t99") 205 .Case("0x0af", "thunderx2t99") 206 .Case("0xa1", "thunderxt88") 207 .Case("0x0a1", "thunderxt88") 208 .Default("generic"); 209 } 210 } 211 } 212 213 if (Implementer == "0x48") // HiSilicon Technologies, Inc. 214 // Look for the CPU part line. 215 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 216 if (Lines[I].startswith("CPU part")) 217 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 218 // values correspond to the "Part number" in the CP15/c0 register. The 219 // contents are specified in the various processor manuals. 220 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 221 .Case("0xd01", "tsv110") 222 .Default("generic"); 223 224 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 225 // Look for the CPU part line. 226 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 227 if (Lines[I].startswith("CPU part")) 228 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 229 // values correspond to the "Part number" in the CP15/c0 register. The 230 // contents are specified in the various processor manuals. 231 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 232 .Case("0x06f", "krait") // APQ8064 233 .Case("0x201", "kryo") 234 .Case("0x205", "kryo") 235 .Case("0x211", "kryo") 236 .Case("0x800", "cortex-a73") 237 .Case("0x801", "cortex-a73") 238 .Case("0xc00", "falkor") 239 .Case("0xc01", "saphira") 240 .Default("generic"); 241 242 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. 243 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow 244 // any predictive pattern across variants and parts. 245 unsigned Variant = 0, Part = 0; 246 247 // Look for the CPU variant line, whose value is a 1 digit hexadecimal 248 // number, corresponding to the Variant bits in the CP15/C0 register. 249 for (auto I : Lines) 250 if (I.consume_front("CPU variant")) 251 I.ltrim("\t :").getAsInteger(0, Variant); 252 253 // Look for the CPU part line, whose value is a 3 digit hexadecimal 254 // number, corresponding to the PartNum bits in the CP15/C0 register. 255 for (auto I : Lines) 256 if (I.consume_front("CPU part")) 257 I.ltrim("\t :").getAsInteger(0, Part); 258 259 unsigned Exynos = (Variant << 12) | Part; 260 switch (Exynos) { 261 default: 262 // Default by falling through to Exynos M1. 263 LLVM_FALLTHROUGH; 264 265 case 0x1001: 266 return "exynos-m1"; 267 268 case 0x4001: 269 return "exynos-m2"; 270 } 271 } 272 273 return "generic"; 274 } 275 276 StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { 277 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 278 279 // The "processor 0:" line comes after a fair amount of other information, 280 // including a cache breakdown, but this should be plenty. 281 SmallVector<StringRef, 32> Lines; 282 ProcCpuinfoContent.split(Lines, "\n"); 283 284 // Look for the CPU features. 285 SmallVector<StringRef, 32> CPUFeatures; 286 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 287 if (Lines[I].startswith("features")) { 288 size_t Pos = Lines[I].find(":"); 289 if (Pos != StringRef::npos) { 290 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 291 break; 292 } 293 } 294 295 // We need to check for the presence of vector support independently of 296 // the machine type, since we may only use the vector register set when 297 // supported by the kernel (and hypervisor). 298 bool HaveVectorSupport = false; 299 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 300 if (CPUFeatures[I] == "vx") 301 HaveVectorSupport = true; 302 } 303 304 // Now check the processor machine type. 305 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 306 if (Lines[I].startswith("processor ")) { 307 size_t Pos = Lines[I].find("machine = "); 308 if (Pos != StringRef::npos) { 309 Pos += sizeof("machine = ") - 1; 310 unsigned int Id; 311 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 312 if (Id >= 3906 && HaveVectorSupport) 313 return "z14"; 314 if (Id >= 2964 && HaveVectorSupport) 315 return "z13"; 316 if (Id >= 2827) 317 return "zEC12"; 318 if (Id >= 2817) 319 return "z196"; 320 } 321 } 322 break; 323 } 324 } 325 326 return "generic"; 327 } 328 329 StringRef sys::detail::getHostCPUNameForBPF() { 330 #if !defined(__linux__) || !defined(__x86_64__) 331 return "generic"; 332 #else 333 uint8_t v3_insns[40] __attribute__ ((aligned (8))) = 334 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 335 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 336 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 337 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 338 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 339 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 340 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 341 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 342 /* BPF_EXIT_INSN() */ 343 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 344 345 uint8_t v2_insns[40] __attribute__ ((aligned (8))) = 346 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 347 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 348 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 349 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 350 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 351 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 352 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 353 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 354 /* BPF_EXIT_INSN() */ 355 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 356 357 struct bpf_prog_load_attr { 358 uint32_t prog_type; 359 uint32_t insn_cnt; 360 uint64_t insns; 361 uint64_t license; 362 uint32_t log_level; 363 uint32_t log_size; 364 uint64_t log_buf; 365 uint32_t kern_version; 366 uint32_t prog_flags; 367 } attr = {}; 368 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 369 attr.insn_cnt = 5; 370 attr.insns = (uint64_t)v3_insns; 371 attr.license = (uint64_t)"DUMMY"; 372 373 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, 374 sizeof(attr)); 375 if (fd >= 0) { 376 close(fd); 377 return "v3"; 378 } 379 380 /* Clear the whole attr in case its content changed by syscall. */ 381 memset(&attr, 0, sizeof(attr)); 382 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 383 attr.insn_cnt = 5; 384 attr.insns = (uint64_t)v2_insns; 385 attr.license = (uint64_t)"DUMMY"; 386 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 387 if (fd >= 0) { 388 close(fd); 389 return "v2"; 390 } 391 return "v1"; 392 #endif 393 } 394 395 #if defined(__i386__) || defined(_M_IX86) || \ 396 defined(__x86_64__) || defined(_M_X64) 397 398 enum VendorSignatures { 399 SIG_INTEL = 0x756e6547 /* Genu */, 400 SIG_AMD = 0x68747541 /* Auth */ 401 }; 402 403 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 404 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 405 // support. Consequently, for i386, the presence of CPUID is checked first 406 // via the corresponding eflags bit. 407 // Removal of cpuid.h header motivated by PR30384 408 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 409 // or test-suite, but are used in external projects e.g. libstdcxx 410 static bool isCpuIdSupported() { 411 #if defined(__GNUC__) || defined(__clang__) 412 #if defined(__i386__) 413 int __cpuid_supported; 414 __asm__(" pushfl\n" 415 " popl %%eax\n" 416 " movl %%eax,%%ecx\n" 417 " xorl $0x00200000,%%eax\n" 418 " pushl %%eax\n" 419 " popfl\n" 420 " pushfl\n" 421 " popl %%eax\n" 422 " movl $0,%0\n" 423 " cmpl %%eax,%%ecx\n" 424 " je 1f\n" 425 " movl $1,%0\n" 426 "1:" 427 : "=r"(__cpuid_supported) 428 : 429 : "eax", "ecx"); 430 if (!__cpuid_supported) 431 return false; 432 #endif 433 return true; 434 #endif 435 return true; 436 } 437 438 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 439 /// the specified arguments. If we can't run cpuid on the host, return true. 440 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 441 unsigned *rECX, unsigned *rEDX) { 442 #if defined(__GNUC__) || defined(__clang__) 443 #if defined(__x86_64__) 444 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 445 // FIXME: should we save this for Clang? 446 __asm__("movq\t%%rbx, %%rsi\n\t" 447 "cpuid\n\t" 448 "xchgq\t%%rbx, %%rsi\n\t" 449 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 450 : "a"(value)); 451 return false; 452 #elif defined(__i386__) 453 __asm__("movl\t%%ebx, %%esi\n\t" 454 "cpuid\n\t" 455 "xchgl\t%%ebx, %%esi\n\t" 456 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 457 : "a"(value)); 458 return false; 459 #else 460 return true; 461 #endif 462 #elif defined(_MSC_VER) 463 // The MSVC intrinsic is portable across x86 and x64. 464 int registers[4]; 465 __cpuid(registers, value); 466 *rEAX = registers[0]; 467 *rEBX = registers[1]; 468 *rECX = registers[2]; 469 *rEDX = registers[3]; 470 return false; 471 #else 472 return true; 473 #endif 474 } 475 476 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 477 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 478 /// return true. 479 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 480 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 481 unsigned *rEDX) { 482 #if defined(__GNUC__) || defined(__clang__) 483 #if defined(__x86_64__) 484 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 485 // FIXME: should we save this for Clang? 486 __asm__("movq\t%%rbx, %%rsi\n\t" 487 "cpuid\n\t" 488 "xchgq\t%%rbx, %%rsi\n\t" 489 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 490 : "a"(value), "c"(subleaf)); 491 return false; 492 #elif defined(__i386__) 493 __asm__("movl\t%%ebx, %%esi\n\t" 494 "cpuid\n\t" 495 "xchgl\t%%ebx, %%esi\n\t" 496 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 497 : "a"(value), "c"(subleaf)); 498 return false; 499 #else 500 return true; 501 #endif 502 #elif defined(_MSC_VER) 503 int registers[4]; 504 __cpuidex(registers, value, subleaf); 505 *rEAX = registers[0]; 506 *rEBX = registers[1]; 507 *rECX = registers[2]; 508 *rEDX = registers[3]; 509 return false; 510 #else 511 return true; 512 #endif 513 } 514 515 // Read control register 0 (XCR0). Used to detect features such as AVX. 516 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 517 #if defined(__GNUC__) || defined(__clang__) 518 // Check xgetbv; this uses a .byte sequence instead of the instruction 519 // directly because older assemblers do not include support for xgetbv and 520 // there is no easy way to conditionally compile based on the assembler used. 521 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 522 return false; 523 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 524 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 525 *rEAX = Result; 526 *rEDX = Result >> 32; 527 return false; 528 #else 529 return true; 530 #endif 531 } 532 533 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 534 unsigned *Model) { 535 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 536 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 537 if (*Family == 6 || *Family == 0xf) { 538 if (*Family == 0xf) 539 // Examine extended family ID if family ID is F. 540 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 541 // Examine extended model ID if family ID is 6 or F. 542 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 543 } 544 } 545 546 static void 547 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 548 unsigned Brand_id, unsigned Features, 549 unsigned Features2, unsigned Features3, 550 unsigned *Type, unsigned *Subtype) { 551 if (Brand_id != 0) 552 return; 553 switch (Family) { 554 case 3: 555 *Type = X86::INTEL_i386; 556 break; 557 case 4: 558 *Type = X86::INTEL_i486; 559 break; 560 case 5: 561 if (Features & (1 << X86::FEATURE_MMX)) { 562 *Type = X86::INTEL_PENTIUM_MMX; 563 break; 564 } 565 *Type = X86::INTEL_PENTIUM; 566 break; 567 case 6: 568 switch (Model) { 569 case 0x01: // Pentium Pro processor 570 *Type = X86::INTEL_PENTIUM_PRO; 571 break; 572 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 573 // model 03 574 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 575 // model 05, and Intel Celeron processor, model 05 576 case 0x06: // Celeron processor, model 06 577 *Type = X86::INTEL_PENTIUM_II; 578 break; 579 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 580 // processor, model 07 581 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 582 // model 08, and Celeron processor, model 08 583 case 0x0a: // Pentium III Xeon processor, model 0Ah 584 case 0x0b: // Pentium III processor, model 0Bh 585 *Type = X86::INTEL_PENTIUM_III; 586 break; 587 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 588 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 589 // 0Dh. All processors are manufactured using the 90 nm process. 590 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 591 // Integrated Processor with Intel QuickAssist Technology 592 *Type = X86::INTEL_PENTIUM_M; 593 break; 594 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 595 // 0Eh. All processors are manufactured using the 65 nm process. 596 *Type = X86::INTEL_CORE_DUO; 597 break; // yonah 598 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 599 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 600 // mobile processor, Intel Core 2 Extreme processor, Intel 601 // Pentium Dual-Core processor, Intel Xeon processor, model 602 // 0Fh. All processors are manufactured using the 65 nm process. 603 case 0x16: // Intel Celeron processor model 16h. All processors are 604 // manufactured using the 65 nm process 605 *Type = X86::INTEL_CORE2; // "core2" 606 *Subtype = X86::INTEL_CORE2_65; 607 break; 608 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 609 // 17h. All processors are manufactured using the 45 nm process. 610 // 611 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 612 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 613 // the 45 nm process. 614 *Type = X86::INTEL_CORE2; // "penryn" 615 *Subtype = X86::INTEL_CORE2_45; 616 break; 617 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 618 // processors are manufactured using the 45 nm process. 619 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 620 // As found in a Summer 2010 model iMac. 621 case 0x1f: 622 case 0x2e: // Nehalem EX 623 *Type = X86::INTEL_COREI7; // "nehalem" 624 *Subtype = X86::INTEL_COREI7_NEHALEM; 625 break; 626 case 0x25: // Intel Core i7, laptop version. 627 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 628 // processors are manufactured using the 32 nm process. 629 case 0x2f: // Westmere EX 630 *Type = X86::INTEL_COREI7; // "westmere" 631 *Subtype = X86::INTEL_COREI7_WESTMERE; 632 break; 633 case 0x2a: // Intel Core i7 processor. All processors are manufactured 634 // using the 32 nm process. 635 case 0x2d: 636 *Type = X86::INTEL_COREI7; //"sandybridge" 637 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 638 break; 639 case 0x3a: 640 case 0x3e: // Ivy Bridge EP 641 *Type = X86::INTEL_COREI7; // "ivybridge" 642 *Subtype = X86::INTEL_COREI7_IVYBRIDGE; 643 break; 644 645 // Haswell: 646 case 0x3c: 647 case 0x3f: 648 case 0x45: 649 case 0x46: 650 *Type = X86::INTEL_COREI7; // "haswell" 651 *Subtype = X86::INTEL_COREI7_HASWELL; 652 break; 653 654 // Broadwell: 655 case 0x3d: 656 case 0x47: 657 case 0x4f: 658 case 0x56: 659 *Type = X86::INTEL_COREI7; // "broadwell" 660 *Subtype = X86::INTEL_COREI7_BROADWELL; 661 break; 662 663 // Skylake: 664 case 0x4e: // Skylake mobile 665 case 0x5e: // Skylake desktop 666 case 0x8e: // Kaby Lake mobile 667 case 0x9e: // Kaby Lake desktop 668 *Type = X86::INTEL_COREI7; // "skylake" 669 *Subtype = X86::INTEL_COREI7_SKYLAKE; 670 break; 671 672 // Skylake Xeon: 673 case 0x55: 674 *Type = X86::INTEL_COREI7; 675 if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) 676 *Subtype = X86::INTEL_COREI7_CASCADELAKE; // "cascadelake" 677 else 678 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 679 break; 680 681 // Cannonlake: 682 case 0x66: 683 *Type = X86::INTEL_COREI7; 684 *Subtype = X86::INTEL_COREI7_CANNONLAKE; // "cannonlake" 685 break; 686 687 // Icelake: 688 case 0x7d: 689 case 0x7e: 690 *Type = X86::INTEL_COREI7; 691 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; // "icelake-client" 692 break; 693 694 // Icelake Xeon: 695 case 0x6a: 696 case 0x6c: 697 *Type = X86::INTEL_COREI7; 698 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; // "icelake-server" 699 break; 700 701 case 0x1c: // Most 45 nm Intel Atom processors 702 case 0x26: // 45 nm Atom Lincroft 703 case 0x27: // 32 nm Atom Medfield 704 case 0x35: // 32 nm Atom Midview 705 case 0x36: // 32 nm Atom Midview 706 *Type = X86::INTEL_BONNELL; 707 break; // "bonnell" 708 709 // Atom Silvermont codes from the Intel software optimization guide. 710 case 0x37: 711 case 0x4a: 712 case 0x4d: 713 case 0x5a: 714 case 0x5d: 715 case 0x4c: // really airmont 716 *Type = X86::INTEL_SILVERMONT; 717 break; // "silvermont" 718 // Goldmont: 719 case 0x5c: // Apollo Lake 720 case 0x5f: // Denverton 721 *Type = X86::INTEL_GOLDMONT; 722 break; // "goldmont" 723 case 0x7a: 724 *Type = X86::INTEL_GOLDMONT_PLUS; 725 break; 726 case 0x86: 727 *Type = X86::INTEL_TREMONT; 728 break; 729 730 case 0x57: 731 *Type = X86::INTEL_KNL; // knl 732 break; 733 734 case 0x85: 735 *Type = X86::INTEL_KNM; // knm 736 break; 737 738 default: // Unknown family 6 CPU, try to guess. 739 if (Features & (1 << X86::FEATURE_AVX512VBMI2)) { 740 *Type = X86::INTEL_COREI7; 741 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; 742 break; 743 } 744 745 if (Features & (1 << X86::FEATURE_AVX512VBMI)) { 746 *Type = X86::INTEL_COREI7; 747 *Subtype = X86::INTEL_COREI7_CANNONLAKE; 748 break; 749 } 750 751 if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) { 752 *Type = X86::INTEL_COREI7; 753 *Subtype = X86::INTEL_COREI7_CASCADELAKE; 754 break; 755 } 756 757 if (Features & (1 << X86::FEATURE_AVX512VL)) { 758 *Type = X86::INTEL_COREI7; 759 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; 760 break; 761 } 762 763 if (Features & (1 << X86::FEATURE_AVX512ER)) { 764 *Type = X86::INTEL_KNL; // knl 765 break; 766 } 767 768 if (Features3 & (1 << (X86::FEATURE_CLFLUSHOPT - 64))) { 769 if (Features3 & (1 << (X86::FEATURE_SHA - 64))) { 770 *Type = X86::INTEL_GOLDMONT; 771 } else { 772 *Type = X86::INTEL_COREI7; 773 *Subtype = X86::INTEL_COREI7_SKYLAKE; 774 } 775 break; 776 } 777 if (Features3 & (1 << (X86::FEATURE_ADX - 64))) { 778 *Type = X86::INTEL_COREI7; 779 *Subtype = X86::INTEL_COREI7_BROADWELL; 780 break; 781 } 782 if (Features & (1 << X86::FEATURE_AVX2)) { 783 *Type = X86::INTEL_COREI7; 784 *Subtype = X86::INTEL_COREI7_HASWELL; 785 break; 786 } 787 if (Features & (1 << X86::FEATURE_AVX)) { 788 *Type = X86::INTEL_COREI7; 789 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 790 break; 791 } 792 if (Features & (1 << X86::FEATURE_SSE4_2)) { 793 if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { 794 *Type = X86::INTEL_SILVERMONT; 795 } else { 796 *Type = X86::INTEL_COREI7; 797 *Subtype = X86::INTEL_COREI7_NEHALEM; 798 } 799 break; 800 } 801 if (Features & (1 << X86::FEATURE_SSE4_1)) { 802 *Type = X86::INTEL_CORE2; // "penryn" 803 *Subtype = X86::INTEL_CORE2_45; 804 break; 805 } 806 if (Features & (1 << X86::FEATURE_SSSE3)) { 807 if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { 808 *Type = X86::INTEL_BONNELL; // "bonnell" 809 } else { 810 *Type = X86::INTEL_CORE2; // "core2" 811 *Subtype = X86::INTEL_CORE2_65; 812 } 813 break; 814 } 815 if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { 816 *Type = X86::INTEL_CORE2; // "core2" 817 *Subtype = X86::INTEL_CORE2_65; 818 break; 819 } 820 if (Features & (1 << X86::FEATURE_SSE3)) { 821 *Type = X86::INTEL_CORE_DUO; 822 break; 823 } 824 if (Features & (1 << X86::FEATURE_SSE2)) { 825 *Type = X86::INTEL_PENTIUM_M; 826 break; 827 } 828 if (Features & (1 << X86::FEATURE_SSE)) { 829 *Type = X86::INTEL_PENTIUM_III; 830 break; 831 } 832 if (Features & (1 << X86::FEATURE_MMX)) { 833 *Type = X86::INTEL_PENTIUM_II; 834 break; 835 } 836 *Type = X86::INTEL_PENTIUM_PRO; 837 break; 838 } 839 break; 840 case 15: { 841 if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { 842 *Type = X86::INTEL_NOCONA; 843 break; 844 } 845 if (Features & (1 << X86::FEATURE_SSE3)) { 846 *Type = X86::INTEL_PRESCOTT; 847 break; 848 } 849 *Type = X86::INTEL_PENTIUM_IV; 850 break; 851 } 852 default: 853 break; /*"generic"*/ 854 } 855 } 856 857 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 858 unsigned Features, unsigned *Type, 859 unsigned *Subtype) { 860 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 861 // appears to be no way to generate the wide variety of AMD-specific targets 862 // from the information returned from CPUID. 863 switch (Family) { 864 case 4: 865 *Type = X86::AMD_i486; 866 break; 867 case 5: 868 *Type = X86::AMDPENTIUM; 869 switch (Model) { 870 case 6: 871 case 7: 872 *Subtype = X86::AMDPENTIUM_K6; 873 break; // "k6" 874 case 8: 875 *Subtype = X86::AMDPENTIUM_K62; 876 break; // "k6-2" 877 case 9: 878 case 13: 879 *Subtype = X86::AMDPENTIUM_K63; 880 break; // "k6-3" 881 case 10: 882 *Subtype = X86::AMDPENTIUM_GEODE; 883 break; // "geode" 884 } 885 break; 886 case 6: 887 if (Features & (1 << X86::FEATURE_SSE)) { 888 *Type = X86::AMD_ATHLON_XP; 889 break; // "athlon-xp" 890 } 891 *Type = X86::AMD_ATHLON; 892 break; // "athlon" 893 case 15: 894 if (Features & (1 << X86::FEATURE_SSE3)) { 895 *Type = X86::AMD_K8SSE3; 896 break; // "k8-sse3" 897 } 898 *Type = X86::AMD_K8; 899 break; // "k8" 900 case 16: 901 *Type = X86::AMDFAM10H; // "amdfam10" 902 switch (Model) { 903 case 2: 904 *Subtype = X86::AMDFAM10H_BARCELONA; 905 break; 906 case 4: 907 *Subtype = X86::AMDFAM10H_SHANGHAI; 908 break; 909 case 8: 910 *Subtype = X86::AMDFAM10H_ISTANBUL; 911 break; 912 } 913 break; 914 case 20: 915 *Type = X86::AMD_BTVER1; 916 break; // "btver1"; 917 case 21: 918 *Type = X86::AMDFAM15H; 919 if (Model >= 0x60 && Model <= 0x7f) { 920 *Subtype = X86::AMDFAM15H_BDVER4; 921 break; // "bdver4"; 60h-7Fh: Excavator 922 } 923 if (Model >= 0x30 && Model <= 0x3f) { 924 *Subtype = X86::AMDFAM15H_BDVER3; 925 break; // "bdver3"; 30h-3Fh: Steamroller 926 } 927 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) { 928 *Subtype = X86::AMDFAM15H_BDVER2; 929 break; // "bdver2"; 02h, 10h-1Fh: Piledriver 930 } 931 if (Model <= 0x0f) { 932 *Subtype = X86::AMDFAM15H_BDVER1; 933 break; // "bdver1"; 00h-0Fh: Bulldozer 934 } 935 break; 936 case 22: 937 *Type = X86::AMD_BTVER2; 938 break; // "btver2" 939 case 23: 940 *Type = X86::AMDFAM17H; 941 if (Model >= 0x30 && Model <= 0x3f) { 942 *Subtype = X86::AMDFAM17H_ZNVER2; 943 break; // "znver2"; 30h-3fh: Zen2 944 } 945 if (Model <= 0x0f) { 946 *Subtype = X86::AMDFAM17H_ZNVER1; 947 break; // "znver1"; 00h-0Fh: Zen1 948 } 949 break; 950 default: 951 break; // "generic" 952 } 953 } 954 955 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 956 unsigned *FeaturesOut, unsigned *Features2Out, 957 unsigned *Features3Out) { 958 unsigned Features = 0; 959 unsigned Features2 = 0; 960 unsigned Features3 = 0; 961 unsigned EAX, EBX; 962 963 auto setFeature = [&](unsigned F) { 964 if (F < 32) 965 Features |= 1U << (F & 0x1f); 966 else if (F < 64) 967 Features2 |= 1U << ((F - 32) & 0x1f); 968 else if (F < 96) 969 Features3 |= 1U << ((F - 64) & 0x1f); 970 else 971 llvm_unreachable("Unexpected FeatureBit"); 972 }; 973 974 if ((EDX >> 15) & 1) 975 setFeature(X86::FEATURE_CMOV); 976 if ((EDX >> 23) & 1) 977 setFeature(X86::FEATURE_MMX); 978 if ((EDX >> 25) & 1) 979 setFeature(X86::FEATURE_SSE); 980 if ((EDX >> 26) & 1) 981 setFeature(X86::FEATURE_SSE2); 982 983 if ((ECX >> 0) & 1) 984 setFeature(X86::FEATURE_SSE3); 985 if ((ECX >> 1) & 1) 986 setFeature(X86::FEATURE_PCLMUL); 987 if ((ECX >> 9) & 1) 988 setFeature(X86::FEATURE_SSSE3); 989 if ((ECX >> 12) & 1) 990 setFeature(X86::FEATURE_FMA); 991 if ((ECX >> 19) & 1) 992 setFeature(X86::FEATURE_SSE4_1); 993 if ((ECX >> 20) & 1) 994 setFeature(X86::FEATURE_SSE4_2); 995 if ((ECX >> 23) & 1) 996 setFeature(X86::FEATURE_POPCNT); 997 if ((ECX >> 25) & 1) 998 setFeature(X86::FEATURE_AES); 999 1000 if ((ECX >> 22) & 1) 1001 setFeature(X86::FEATURE_MOVBE); 1002 1003 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1004 // indicates that the AVX registers will be saved and restored on context 1005 // switch, then we have full AVX support. 1006 const unsigned AVXBits = (1 << 27) | (1 << 28); 1007 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 1008 ((EAX & 0x6) == 0x6); 1009 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 1010 1011 if (HasAVX) 1012 setFeature(X86::FEATURE_AVX); 1013 1014 bool HasLeaf7 = 1015 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1016 1017 if (HasLeaf7 && ((EBX >> 3) & 1)) 1018 setFeature(X86::FEATURE_BMI); 1019 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 1020 setFeature(X86::FEATURE_AVX2); 1021 if (HasLeaf7 && ((EBX >> 9) & 1)) 1022 setFeature(X86::FEATURE_BMI2); 1023 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 1024 setFeature(X86::FEATURE_AVX512F); 1025 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 1026 setFeature(X86::FEATURE_AVX512DQ); 1027 if (HasLeaf7 && ((EBX >> 19) & 1)) 1028 setFeature(X86::FEATURE_ADX); 1029 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 1030 setFeature(X86::FEATURE_AVX512IFMA); 1031 if (HasLeaf7 && ((EBX >> 23) & 1)) 1032 setFeature(X86::FEATURE_CLFLUSHOPT); 1033 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 1034 setFeature(X86::FEATURE_AVX512PF); 1035 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 1036 setFeature(X86::FEATURE_AVX512ER); 1037 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 1038 setFeature(X86::FEATURE_AVX512CD); 1039 if (HasLeaf7 && ((EBX >> 29) & 1)) 1040 setFeature(X86::FEATURE_SHA); 1041 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 1042 setFeature(X86::FEATURE_AVX512BW); 1043 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 1044 setFeature(X86::FEATURE_AVX512VL); 1045 1046 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 1047 setFeature(X86::FEATURE_AVX512VBMI); 1048 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save) 1049 setFeature(X86::FEATURE_AVX512VBMI2); 1050 if (HasLeaf7 && ((ECX >> 8) & 1)) 1051 setFeature(X86::FEATURE_GFNI); 1052 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX) 1053 setFeature(X86::FEATURE_VPCLMULQDQ); 1054 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save) 1055 setFeature(X86::FEATURE_AVX512VNNI); 1056 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save) 1057 setFeature(X86::FEATURE_AVX512BITALG); 1058 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1059 setFeature(X86::FEATURE_AVX512VPOPCNTDQ); 1060 1061 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1062 setFeature(X86::FEATURE_AVX5124VNNIW); 1063 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1064 setFeature(X86::FEATURE_AVX5124FMAPS); 1065 1066 unsigned MaxExtLevel; 1067 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1068 1069 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1070 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1071 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1072 setFeature(X86::FEATURE_SSE4_A); 1073 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1074 setFeature(X86::FEATURE_XOP); 1075 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1076 setFeature(X86::FEATURE_FMA4); 1077 1078 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1079 setFeature(X86::FEATURE_EM64T); 1080 1081 *FeaturesOut = Features; 1082 *Features2Out = Features2; 1083 *Features3Out = Features3; 1084 } 1085 1086 StringRef sys::getHostCPUName() { 1087 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1088 unsigned MaxLeaf, Vendor; 1089 1090 #if defined(__GNUC__) || defined(__clang__) 1091 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here 1092 // and simplify it to not invoke __cpuid (like cpu_model.c in 1093 // compiler-rt/lib/builtins/cpu_model.c? 1094 // Opting for the second option. 1095 if(!isCpuIdSupported()) 1096 return "generic"; 1097 #endif 1098 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) 1099 return "generic"; 1100 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1101 1102 unsigned Brand_id = EBX & 0xff; 1103 unsigned Family = 0, Model = 0; 1104 unsigned Features = 0, Features2 = 0, Features3 = 0; 1105 detectX86FamilyModel(EAX, &Family, &Model); 1106 getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2, &Features3); 1107 1108 unsigned Type = 0; 1109 unsigned Subtype = 0; 1110 1111 if (Vendor == SIG_INTEL) { 1112 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, 1113 Features2, Features3, &Type, &Subtype); 1114 } else if (Vendor == SIG_AMD) { 1115 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1116 } 1117 1118 // Check subtypes first since those are more specific. 1119 #define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \ 1120 if (Subtype == X86::ENUM) \ 1121 return ARCHNAME; 1122 #include "llvm/Support/X86TargetParser.def" 1123 1124 // Now check types. 1125 #define X86_CPU_TYPE(ARCHNAME, ENUM) \ 1126 if (Type == X86::ENUM) \ 1127 return ARCHNAME; 1128 #include "llvm/Support/X86TargetParser.def" 1129 1130 return "generic"; 1131 } 1132 1133 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1134 StringRef sys::getHostCPUName() { 1135 host_basic_info_data_t hostInfo; 1136 mach_msg_type_number_t infoCount; 1137 1138 infoCount = HOST_BASIC_INFO_COUNT; 1139 mach_port_t hostPort = mach_host_self(); 1140 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1141 &infoCount); 1142 mach_port_deallocate(mach_task_self(), hostPort); 1143 1144 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1145 return "generic"; 1146 1147 switch (hostInfo.cpu_subtype) { 1148 case CPU_SUBTYPE_POWERPC_601: 1149 return "601"; 1150 case CPU_SUBTYPE_POWERPC_602: 1151 return "602"; 1152 case CPU_SUBTYPE_POWERPC_603: 1153 return "603"; 1154 case CPU_SUBTYPE_POWERPC_603e: 1155 return "603e"; 1156 case CPU_SUBTYPE_POWERPC_603ev: 1157 return "603ev"; 1158 case CPU_SUBTYPE_POWERPC_604: 1159 return "604"; 1160 case CPU_SUBTYPE_POWERPC_604e: 1161 return "604e"; 1162 case CPU_SUBTYPE_POWERPC_620: 1163 return "620"; 1164 case CPU_SUBTYPE_POWERPC_750: 1165 return "750"; 1166 case CPU_SUBTYPE_POWERPC_7400: 1167 return "7400"; 1168 case CPU_SUBTYPE_POWERPC_7450: 1169 return "7450"; 1170 case CPU_SUBTYPE_POWERPC_970: 1171 return "970"; 1172 default:; 1173 } 1174 1175 return "generic"; 1176 } 1177 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1178 StringRef sys::getHostCPUName() { 1179 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1180 StringRef Content = P ? P->getBuffer() : ""; 1181 return detail::getHostCPUNameForPowerPC(Content); 1182 } 1183 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1184 StringRef sys::getHostCPUName() { 1185 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1186 StringRef Content = P ? P->getBuffer() : ""; 1187 return detail::getHostCPUNameForARM(Content); 1188 } 1189 #elif defined(__linux__) && defined(__s390x__) 1190 StringRef sys::getHostCPUName() { 1191 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1192 StringRef Content = P ? P->getBuffer() : ""; 1193 return detail::getHostCPUNameForS390x(Content); 1194 } 1195 #else 1196 StringRef sys::getHostCPUName() { return "generic"; } 1197 #endif 1198 1199 #if defined(__linux__) && defined(__x86_64__) 1200 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1201 // using the number of unique physical/core id pairs. The following 1202 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1203 static int computeHostNumPhysicalCores() { 1204 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1205 // mmapped because it appears to have 0 size. 1206 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1207 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1208 if (std::error_code EC = Text.getError()) { 1209 llvm::errs() << "Can't read " 1210 << "/proc/cpuinfo: " << EC.message() << "\n"; 1211 return -1; 1212 } 1213 SmallVector<StringRef, 8> strs; 1214 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1215 /*KeepEmpty=*/false); 1216 int CurPhysicalId = -1; 1217 int CurCoreId = -1; 1218 SmallSet<std::pair<int, int>, 32> UniqueItems; 1219 for (auto &Line : strs) { 1220 Line = Line.trim(); 1221 if (!Line.startswith("physical id") && !Line.startswith("core id")) 1222 continue; 1223 std::pair<StringRef, StringRef> Data = Line.split(':'); 1224 auto Name = Data.first.trim(); 1225 auto Val = Data.second.trim(); 1226 if (Name == "physical id") { 1227 assert(CurPhysicalId == -1 && 1228 "Expected a core id before seeing another physical id"); 1229 Val.getAsInteger(10, CurPhysicalId); 1230 } 1231 if (Name == "core id") { 1232 assert(CurCoreId == -1 && 1233 "Expected a physical id before seeing another core id"); 1234 Val.getAsInteger(10, CurCoreId); 1235 } 1236 if (CurPhysicalId != -1 && CurCoreId != -1) { 1237 UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId)); 1238 CurPhysicalId = -1; 1239 CurCoreId = -1; 1240 } 1241 } 1242 return UniqueItems.size(); 1243 } 1244 #elif defined(__APPLE__) && defined(__x86_64__) 1245 #include <sys/param.h> 1246 #include <sys/sysctl.h> 1247 1248 // Gets the number of *physical cores* on the machine. 1249 static int computeHostNumPhysicalCores() { 1250 uint32_t count; 1251 size_t len = sizeof(count); 1252 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1253 if (count < 1) { 1254 int nm[2]; 1255 nm[0] = CTL_HW; 1256 nm[1] = HW_AVAILCPU; 1257 sysctl(nm, 2, &count, &len, NULL, 0); 1258 if (count < 1) 1259 return -1; 1260 } 1261 return count; 1262 } 1263 #else 1264 // On other systems, return -1 to indicate unknown. 1265 static int computeHostNumPhysicalCores() { return -1; } 1266 #endif 1267 1268 int sys::getHostNumPhysicalCores() { 1269 static int NumCores = computeHostNumPhysicalCores(); 1270 return NumCores; 1271 } 1272 1273 #if defined(__i386__) || defined(_M_IX86) || \ 1274 defined(__x86_64__) || defined(_M_X64) 1275 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1276 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1277 unsigned MaxLevel; 1278 union { 1279 unsigned u[3]; 1280 char c[12]; 1281 } text; 1282 1283 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1284 MaxLevel < 1) 1285 return false; 1286 1287 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1288 1289 Features["cx8"] = (EDX >> 8) & 1; 1290 Features["cmov"] = (EDX >> 15) & 1; 1291 Features["mmx"] = (EDX >> 23) & 1; 1292 Features["fxsr"] = (EDX >> 24) & 1; 1293 Features["sse"] = (EDX >> 25) & 1; 1294 Features["sse2"] = (EDX >> 26) & 1; 1295 1296 Features["sse3"] = (ECX >> 0) & 1; 1297 Features["pclmul"] = (ECX >> 1) & 1; 1298 Features["ssse3"] = (ECX >> 9) & 1; 1299 Features["cx16"] = (ECX >> 13) & 1; 1300 Features["sse4.1"] = (ECX >> 19) & 1; 1301 Features["sse4.2"] = (ECX >> 20) & 1; 1302 Features["movbe"] = (ECX >> 22) & 1; 1303 Features["popcnt"] = (ECX >> 23) & 1; 1304 Features["aes"] = (ECX >> 25) & 1; 1305 Features["rdrnd"] = (ECX >> 30) & 1; 1306 1307 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1308 // indicates that the AVX registers will be saved and restored on context 1309 // switch, then we have full AVX support. 1310 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1311 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1312 // AVX512 requires additional context to be saved by the OS. 1313 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1314 1315 Features["avx"] = HasAVXSave; 1316 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave; 1317 // Only enable XSAVE if OS has enabled support for saving YMM state. 1318 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave; 1319 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave; 1320 1321 unsigned MaxExtLevel; 1322 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1323 1324 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1325 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1326 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1); 1327 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1328 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1329 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1330 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1331 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1332 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1333 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1334 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1335 1336 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1); 1337 1338 // Miscellaneous memory related features, detected by 1339 // using the 0x80000008 leaf of the CPUID instruction 1340 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1341 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX); 1342 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1343 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1); 1344 1345 bool HasLeaf7 = 1346 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1347 1348 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1349 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1350 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1351 // AVX2 is only supported if we have the OS save support from AVX. 1352 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave; 1353 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1354 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1355 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1356 Features["mpx"] = HasLeaf7 && ((EBX >> 14) & 1); 1357 // AVX512 is only supported if the OS supports the context save for it. 1358 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1359 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1360 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1361 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1362 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1363 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1364 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1365 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1366 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1367 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1368 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1369 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1370 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1371 1372 Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1); 1373 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1374 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1375 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1); 1376 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save; 1377 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1); 1378 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1); 1379 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave; 1380 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave; 1381 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save; 1382 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save; 1383 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1384 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1); 1385 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1); 1386 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1); 1387 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1); 1388 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1); 1389 1390 // There are two CPUID leafs which information associated with the pconfig 1391 // instruction: 1392 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th 1393 // bit of EDX), while the EAX=0x1b leaf returns information on the 1394 // availability of specific pconfig leafs. 1395 // The target feature here only refers to the the first of these two. 1396 // Users might need to check for the availability of specific pconfig 1397 // leaves using cpuid, since that information is ignored while 1398 // detecting features using the "-march=native" flag. 1399 // For more info, see X86 ISA docs. 1400 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1); 1401 bool HasLeaf7Subleaf1 = 1402 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1403 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save; 1404 1405 bool HasLeafD = MaxLevel >= 0xd && 1406 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1407 1408 // Only enable XSAVE if OS has enabled support for saving YMM state. 1409 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave; 1410 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave; 1411 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave; 1412 1413 bool HasLeaf14 = MaxLevel >= 0x14 && 1414 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX); 1415 1416 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1); 1417 1418 return true; 1419 } 1420 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1421 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1422 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1423 if (!P) 1424 return false; 1425 1426 SmallVector<StringRef, 32> Lines; 1427 P->getBuffer().split(Lines, "\n"); 1428 1429 SmallVector<StringRef, 32> CPUFeatures; 1430 1431 // Look for the CPU features. 1432 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1433 if (Lines[I].startswith("Features")) { 1434 Lines[I].split(CPUFeatures, ' '); 1435 break; 1436 } 1437 1438 #if defined(__aarch64__) 1439 // Keep track of which crypto features we have seen 1440 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1441 uint32_t crypto = 0; 1442 #endif 1443 1444 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1445 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1446 #if defined(__aarch64__) 1447 .Case("asimd", "neon") 1448 .Case("fp", "fp-armv8") 1449 .Case("crc32", "crc") 1450 #else 1451 .Case("half", "fp16") 1452 .Case("neon", "neon") 1453 .Case("vfpv3", "vfp3") 1454 .Case("vfpv3d16", "d16") 1455 .Case("vfpv4", "vfp4") 1456 .Case("idiva", "hwdiv-arm") 1457 .Case("idivt", "hwdiv") 1458 #endif 1459 .Default(""); 1460 1461 #if defined(__aarch64__) 1462 // We need to check crypto separately since we need all of the crypto 1463 // extensions to enable the subtarget feature 1464 if (CPUFeatures[I] == "aes") 1465 crypto |= CAP_AES; 1466 else if (CPUFeatures[I] == "pmull") 1467 crypto |= CAP_PMULL; 1468 else if (CPUFeatures[I] == "sha1") 1469 crypto |= CAP_SHA1; 1470 else if (CPUFeatures[I] == "sha2") 1471 crypto |= CAP_SHA2; 1472 #endif 1473 1474 if (LLVMFeatureStr != "") 1475 Features[LLVMFeatureStr] = true; 1476 } 1477 1478 #if defined(__aarch64__) 1479 // If we have all crypto bits we can add the feature 1480 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1481 Features["crypto"] = true; 1482 #endif 1483 1484 return true; 1485 } 1486 #else 1487 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1488 #endif 1489 1490 std::string sys::getProcessTriple() { 1491 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1492 Triple PT(Triple::normalize(TargetTripleString)); 1493 1494 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1495 PT = PT.get64BitArchVariant(); 1496 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1497 PT = PT.get32BitArchVariant(); 1498 1499 return PT.str(); 1500 } 1501