1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the operating system Host concept. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/Host.h" 14 #include "llvm/ADT/SmallSet.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringMap.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/llvm-config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/TargetParser.h" 25 #include "llvm/Support/raw_ostream.h" 26 #include <assert.h> 27 #include <string.h> 28 29 // Include the platform-specific parts of this class. 30 #ifdef LLVM_ON_UNIX 31 #include "Unix/Host.inc" 32 #include <sched.h> 33 #endif 34 #ifdef _WIN32 35 #include "Windows/Host.inc" 36 #endif 37 #ifdef _MSC_VER 38 #include <intrin.h> 39 #endif 40 #if defined(__APPLE__) && (!defined(__x86_64__)) 41 #include <mach/host_info.h> 42 #include <mach/mach.h> 43 #include <mach/mach_host.h> 44 #include <mach/machine.h> 45 #endif 46 47 #define DEBUG_TYPE "host-detection" 48 49 //===----------------------------------------------------------------------===// 50 // 51 // Implementations of the CPU detection routines 52 // 53 //===----------------------------------------------------------------------===// 54 55 using namespace llvm; 56 57 static std::unique_ptr<llvm::MemoryBuffer> 58 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 59 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 60 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 61 if (std::error_code EC = Text.getError()) { 62 llvm::errs() << "Can't read " 63 << "/proc/cpuinfo: " << EC.message() << "\n"; 64 return nullptr; 65 } 66 return std::move(*Text); 67 } 68 69 StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) { 70 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 71 // and so we must use an operating-system interface to determine the current 72 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 73 const char *generic = "generic"; 74 75 // The cpu line is second (after the 'processor: 0' line), so if this 76 // buffer is too small then something has changed (or is wrong). 77 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 78 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 79 80 StringRef::const_iterator CIP = CPUInfoStart; 81 82 StringRef::const_iterator CPUStart = 0; 83 size_t CPULen = 0; 84 85 // We need to find the first line which starts with cpu, spaces, and a colon. 86 // After the colon, there may be some additional spaces and then the cpu type. 87 while (CIP < CPUInfoEnd && CPUStart == 0) { 88 if (CIP < CPUInfoEnd && *CIP == '\n') 89 ++CIP; 90 91 if (CIP < CPUInfoEnd && *CIP == 'c') { 92 ++CIP; 93 if (CIP < CPUInfoEnd && *CIP == 'p') { 94 ++CIP; 95 if (CIP < CPUInfoEnd && *CIP == 'u') { 96 ++CIP; 97 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 98 ++CIP; 99 100 if (CIP < CPUInfoEnd && *CIP == ':') { 101 ++CIP; 102 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 103 ++CIP; 104 105 if (CIP < CPUInfoEnd) { 106 CPUStart = CIP; 107 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 108 *CIP != ',' && *CIP != '\n')) 109 ++CIP; 110 CPULen = CIP - CPUStart; 111 } 112 } 113 } 114 } 115 } 116 117 if (CPUStart == 0) 118 while (CIP < CPUInfoEnd && *CIP != '\n') 119 ++CIP; 120 } 121 122 if (CPUStart == 0) 123 return generic; 124 125 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 126 .Case("604e", "604e") 127 .Case("604", "604") 128 .Case("7400", "7400") 129 .Case("7410", "7400") 130 .Case("7447", "7400") 131 .Case("7455", "7450") 132 .Case("G4", "g4") 133 .Case("POWER4", "970") 134 .Case("PPC970FX", "970") 135 .Case("PPC970MP", "970") 136 .Case("G5", "g5") 137 .Case("POWER5", "g5") 138 .Case("A2", "a2") 139 .Case("POWER6", "pwr6") 140 .Case("POWER7", "pwr7") 141 .Case("POWER8", "pwr8") 142 .Case("POWER8E", "pwr8") 143 .Case("POWER8NVL", "pwr8") 144 .Case("POWER9", "pwr9") 145 // FIXME: If we get a simulator or machine with the capabilities of 146 // mcpu=future, we should revisit this and add the name reported by the 147 // simulator/machine. 148 .Default(generic); 149 } 150 151 StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { 152 // The cpuid register on arm is not accessible from user space. On Linux, 153 // it is exposed through the /proc/cpuinfo file. 154 155 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 156 // in all cases. 157 SmallVector<StringRef, 32> Lines; 158 ProcCpuinfoContent.split(Lines, "\n"); 159 160 // Look for the CPU implementer line. 161 StringRef Implementer; 162 StringRef Hardware; 163 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 164 if (Lines[I].startswith("CPU implementer")) 165 Implementer = Lines[I].substr(15).ltrim("\t :"); 166 if (Lines[I].startswith("Hardware")) 167 Hardware = Lines[I].substr(8).ltrim("\t :"); 168 } 169 170 if (Implementer == "0x41") { // ARM Ltd. 171 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 172 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 173 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 174 return "cortex-a53"; 175 176 177 // Look for the CPU part line. 178 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 179 if (Lines[I].startswith("CPU part")) 180 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 181 // values correspond to the "Part number" in the CP15/c0 register. The 182 // contents are specified in the various processor manuals. 183 // This corresponds to the Main ID Register in Technical Reference Manuals. 184 // and is used in programs like sys-utils 185 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 186 .Case("0x926", "arm926ej-s") 187 .Case("0xb02", "mpcore") 188 .Case("0xb36", "arm1136j-s") 189 .Case("0xb56", "arm1156t2-s") 190 .Case("0xb76", "arm1176jz-s") 191 .Case("0xc08", "cortex-a8") 192 .Case("0xc09", "cortex-a9") 193 .Case("0xc0f", "cortex-a15") 194 .Case("0xc20", "cortex-m0") 195 .Case("0xc23", "cortex-m3") 196 .Case("0xc24", "cortex-m4") 197 .Case("0xd22", "cortex-m55") 198 .Case("0xd02", "cortex-a34") 199 .Case("0xd04", "cortex-a35") 200 .Case("0xd03", "cortex-a53") 201 .Case("0xd07", "cortex-a57") 202 .Case("0xd08", "cortex-a72") 203 .Case("0xd09", "cortex-a73") 204 .Case("0xd0a", "cortex-a75") 205 .Case("0xd0b", "cortex-a76") 206 .Default("generic"); 207 } 208 209 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium. 210 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 211 if (Lines[I].startswith("CPU part")) { 212 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 213 .Case("0x516", "thunderx2t99") 214 .Case("0x0516", "thunderx2t99") 215 .Case("0xaf", "thunderx2t99") 216 .Case("0x0af", "thunderx2t99") 217 .Case("0xa1", "thunderxt88") 218 .Case("0x0a1", "thunderxt88") 219 .Default("generic"); 220 } 221 } 222 } 223 224 if (Implementer == "0x46") { // Fujitsu Ltd. 225 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 226 if (Lines[I].startswith("CPU part")) { 227 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 228 .Case("0x001", "a64fx") 229 .Default("generic"); 230 } 231 } 232 } 233 234 if (Implementer == "0x4e") { // NVIDIA Corporation 235 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 236 if (Lines[I].startswith("CPU part")) { 237 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 238 .Case("0x004", "carmel") 239 .Default("generic"); 240 } 241 } 242 } 243 244 if (Implementer == "0x48") // HiSilicon Technologies, Inc. 245 // Look for the CPU part line. 246 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 247 if (Lines[I].startswith("CPU part")) 248 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 249 // values correspond to the "Part number" in the CP15/c0 register. The 250 // contents are specified in the various processor manuals. 251 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 252 .Case("0xd01", "tsv110") 253 .Default("generic"); 254 255 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 256 // Look for the CPU part line. 257 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 258 if (Lines[I].startswith("CPU part")) 259 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 260 // values correspond to the "Part number" in the CP15/c0 register. The 261 // contents are specified in the various processor manuals. 262 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 263 .Case("0x06f", "krait") // APQ8064 264 .Case("0x201", "kryo") 265 .Case("0x205", "kryo") 266 .Case("0x211", "kryo") 267 .Case("0x800", "cortex-a73") 268 .Case("0x801", "cortex-a73") 269 .Case("0x802", "cortex-a73") 270 .Case("0x803", "cortex-a73") 271 .Case("0x804", "cortex-a73") 272 .Case("0x805", "cortex-a73") 273 .Case("0xc00", "falkor") 274 .Case("0xc01", "saphira") 275 .Default("generic"); 276 277 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. 278 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow 279 // any predictive pattern across variants and parts. 280 unsigned Variant = 0, Part = 0; 281 282 // Look for the CPU variant line, whose value is a 1 digit hexadecimal 283 // number, corresponding to the Variant bits in the CP15/C0 register. 284 for (auto I : Lines) 285 if (I.consume_front("CPU variant")) 286 I.ltrim("\t :").getAsInteger(0, Variant); 287 288 // Look for the CPU part line, whose value is a 3 digit hexadecimal 289 // number, corresponding to the PartNum bits in the CP15/C0 register. 290 for (auto I : Lines) 291 if (I.consume_front("CPU part")) 292 I.ltrim("\t :").getAsInteger(0, Part); 293 294 unsigned Exynos = (Variant << 12) | Part; 295 switch (Exynos) { 296 default: 297 // Default by falling through to Exynos M3. 298 LLVM_FALLTHROUGH; 299 case 0x1002: 300 return "exynos-m3"; 301 case 0x1003: 302 return "exynos-m4"; 303 } 304 } 305 306 return "generic"; 307 } 308 309 StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { 310 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 311 312 // The "processor 0:" line comes after a fair amount of other information, 313 // including a cache breakdown, but this should be plenty. 314 SmallVector<StringRef, 32> Lines; 315 ProcCpuinfoContent.split(Lines, "\n"); 316 317 // Look for the CPU features. 318 SmallVector<StringRef, 32> CPUFeatures; 319 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 320 if (Lines[I].startswith("features")) { 321 size_t Pos = Lines[I].find(":"); 322 if (Pos != StringRef::npos) { 323 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 324 break; 325 } 326 } 327 328 // We need to check for the presence of vector support independently of 329 // the machine type, since we may only use the vector register set when 330 // supported by the kernel (and hypervisor). 331 bool HaveVectorSupport = false; 332 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 333 if (CPUFeatures[I] == "vx") 334 HaveVectorSupport = true; 335 } 336 337 // Now check the processor machine type. 338 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 339 if (Lines[I].startswith("processor ")) { 340 size_t Pos = Lines[I].find("machine = "); 341 if (Pos != StringRef::npos) { 342 Pos += sizeof("machine = ") - 1; 343 unsigned int Id; 344 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 345 if (Id >= 8561 && HaveVectorSupport) 346 return "z15"; 347 if (Id >= 3906 && HaveVectorSupport) 348 return "z14"; 349 if (Id >= 2964 && HaveVectorSupport) 350 return "z13"; 351 if (Id >= 2827) 352 return "zEC12"; 353 if (Id >= 2817) 354 return "z196"; 355 } 356 } 357 break; 358 } 359 } 360 361 return "generic"; 362 } 363 364 StringRef sys::detail::getHostCPUNameForBPF() { 365 #if !defined(__linux__) || !defined(__x86_64__) 366 return "generic"; 367 #else 368 uint8_t v3_insns[40] __attribute__ ((aligned (8))) = 369 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 370 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 371 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 372 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 373 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 374 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 375 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 376 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 377 /* BPF_EXIT_INSN() */ 378 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 379 380 uint8_t v2_insns[40] __attribute__ ((aligned (8))) = 381 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 382 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 383 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 384 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 385 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 386 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 387 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 388 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 389 /* BPF_EXIT_INSN() */ 390 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 391 392 struct bpf_prog_load_attr { 393 uint32_t prog_type; 394 uint32_t insn_cnt; 395 uint64_t insns; 396 uint64_t license; 397 uint32_t log_level; 398 uint32_t log_size; 399 uint64_t log_buf; 400 uint32_t kern_version; 401 uint32_t prog_flags; 402 } attr = {}; 403 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 404 attr.insn_cnt = 5; 405 attr.insns = (uint64_t)v3_insns; 406 attr.license = (uint64_t)"DUMMY"; 407 408 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, 409 sizeof(attr)); 410 if (fd >= 0) { 411 close(fd); 412 return "v3"; 413 } 414 415 /* Clear the whole attr in case its content changed by syscall. */ 416 memset(&attr, 0, sizeof(attr)); 417 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 418 attr.insn_cnt = 5; 419 attr.insns = (uint64_t)v2_insns; 420 attr.license = (uint64_t)"DUMMY"; 421 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 422 if (fd >= 0) { 423 close(fd); 424 return "v2"; 425 } 426 return "v1"; 427 #endif 428 } 429 430 #if defined(__i386__) || defined(_M_IX86) || \ 431 defined(__x86_64__) || defined(_M_X64) 432 433 enum VendorSignatures { 434 SIG_INTEL = 0x756e6547 /* Genu */, 435 SIG_AMD = 0x68747541 /* Auth */ 436 }; 437 438 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 439 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 440 // support. Consequently, for i386, the presence of CPUID is checked first 441 // via the corresponding eflags bit. 442 // Removal of cpuid.h header motivated by PR30384 443 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 444 // or test-suite, but are used in external projects e.g. libstdcxx 445 static bool isCpuIdSupported() { 446 #if defined(__GNUC__) || defined(__clang__) 447 #if defined(__i386__) 448 int __cpuid_supported; 449 __asm__(" pushfl\n" 450 " popl %%eax\n" 451 " movl %%eax,%%ecx\n" 452 " xorl $0x00200000,%%eax\n" 453 " pushl %%eax\n" 454 " popfl\n" 455 " pushfl\n" 456 " popl %%eax\n" 457 " movl $0,%0\n" 458 " cmpl %%eax,%%ecx\n" 459 " je 1f\n" 460 " movl $1,%0\n" 461 "1:" 462 : "=r"(__cpuid_supported) 463 : 464 : "eax", "ecx"); 465 if (!__cpuid_supported) 466 return false; 467 #endif 468 return true; 469 #endif 470 return true; 471 } 472 473 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 474 /// the specified arguments. If we can't run cpuid on the host, return true. 475 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 476 unsigned *rECX, unsigned *rEDX) { 477 #if defined(__GNUC__) || defined(__clang__) 478 #if defined(__x86_64__) 479 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 480 // FIXME: should we save this for Clang? 481 __asm__("movq\t%%rbx, %%rsi\n\t" 482 "cpuid\n\t" 483 "xchgq\t%%rbx, %%rsi\n\t" 484 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 485 : "a"(value)); 486 return false; 487 #elif defined(__i386__) 488 __asm__("movl\t%%ebx, %%esi\n\t" 489 "cpuid\n\t" 490 "xchgl\t%%ebx, %%esi\n\t" 491 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 492 : "a"(value)); 493 return false; 494 #else 495 return true; 496 #endif 497 #elif defined(_MSC_VER) 498 // The MSVC intrinsic is portable across x86 and x64. 499 int registers[4]; 500 __cpuid(registers, value); 501 *rEAX = registers[0]; 502 *rEBX = registers[1]; 503 *rECX = registers[2]; 504 *rEDX = registers[3]; 505 return false; 506 #else 507 return true; 508 #endif 509 } 510 511 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 512 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 513 /// return true. 514 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 515 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 516 unsigned *rEDX) { 517 #if defined(__GNUC__) || defined(__clang__) 518 #if defined(__x86_64__) 519 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 520 // FIXME: should we save this for Clang? 521 __asm__("movq\t%%rbx, %%rsi\n\t" 522 "cpuid\n\t" 523 "xchgq\t%%rbx, %%rsi\n\t" 524 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 525 : "a"(value), "c"(subleaf)); 526 return false; 527 #elif defined(__i386__) 528 __asm__("movl\t%%ebx, %%esi\n\t" 529 "cpuid\n\t" 530 "xchgl\t%%ebx, %%esi\n\t" 531 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 532 : "a"(value), "c"(subleaf)); 533 return false; 534 #else 535 return true; 536 #endif 537 #elif defined(_MSC_VER) 538 int registers[4]; 539 __cpuidex(registers, value, subleaf); 540 *rEAX = registers[0]; 541 *rEBX = registers[1]; 542 *rECX = registers[2]; 543 *rEDX = registers[3]; 544 return false; 545 #else 546 return true; 547 #endif 548 } 549 550 // Read control register 0 (XCR0). Used to detect features such as AVX. 551 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 552 #if defined(__GNUC__) || defined(__clang__) 553 // Check xgetbv; this uses a .byte sequence instead of the instruction 554 // directly because older assemblers do not include support for xgetbv and 555 // there is no easy way to conditionally compile based on the assembler used. 556 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 557 return false; 558 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 559 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 560 *rEAX = Result; 561 *rEDX = Result >> 32; 562 return false; 563 #else 564 return true; 565 #endif 566 } 567 568 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 569 unsigned *Model) { 570 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 571 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 572 if (*Family == 6 || *Family == 0xf) { 573 if (*Family == 0xf) 574 // Examine extended family ID if family ID is F. 575 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 576 // Examine extended model ID if family ID is 6 or F. 577 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 578 } 579 } 580 581 static void 582 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 583 unsigned Brand_id, unsigned Features, 584 unsigned Features2, unsigned Features3, 585 unsigned *Type, unsigned *Subtype) { 586 if (Brand_id != 0) 587 return; 588 switch (Family) { 589 case 3: 590 *Type = X86::INTEL_i386; 591 break; 592 case 4: 593 *Type = X86::INTEL_i486; 594 break; 595 case 5: 596 if (Features & (1 << X86::FEATURE_MMX)) { 597 *Type = X86::INTEL_PENTIUM_MMX; 598 break; 599 } 600 *Type = X86::INTEL_PENTIUM; 601 break; 602 case 6: 603 switch (Model) { 604 case 0x01: // Pentium Pro processor 605 *Type = X86::INTEL_PENTIUM_PRO; 606 break; 607 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 608 // model 03 609 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 610 // model 05, and Intel Celeron processor, model 05 611 case 0x06: // Celeron processor, model 06 612 *Type = X86::INTEL_PENTIUM_II; 613 break; 614 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 615 // processor, model 07 616 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 617 // model 08, and Celeron processor, model 08 618 case 0x0a: // Pentium III Xeon processor, model 0Ah 619 case 0x0b: // Pentium III processor, model 0Bh 620 *Type = X86::INTEL_PENTIUM_III; 621 break; 622 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 623 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 624 // 0Dh. All processors are manufactured using the 90 nm process. 625 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 626 // Integrated Processor with Intel QuickAssist Technology 627 *Type = X86::INTEL_PENTIUM_M; 628 break; 629 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 630 // 0Eh. All processors are manufactured using the 65 nm process. 631 *Type = X86::INTEL_CORE_DUO; 632 break; // yonah 633 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 634 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 635 // mobile processor, Intel Core 2 Extreme processor, Intel 636 // Pentium Dual-Core processor, Intel Xeon processor, model 637 // 0Fh. All processors are manufactured using the 65 nm process. 638 case 0x16: // Intel Celeron processor model 16h. All processors are 639 // manufactured using the 65 nm process 640 *Type = X86::INTEL_CORE2; // "core2" 641 *Subtype = X86::INTEL_CORE2_65; 642 break; 643 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 644 // 17h. All processors are manufactured using the 45 nm process. 645 // 646 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 647 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 648 // the 45 nm process. 649 *Type = X86::INTEL_CORE2; // "penryn" 650 *Subtype = X86::INTEL_CORE2_45; 651 break; 652 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 653 // processors are manufactured using the 45 nm process. 654 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 655 // As found in a Summer 2010 model iMac. 656 case 0x1f: 657 case 0x2e: // Nehalem EX 658 *Type = X86::INTEL_COREI7; // "nehalem" 659 *Subtype = X86::INTEL_COREI7_NEHALEM; 660 break; 661 case 0x25: // Intel Core i7, laptop version. 662 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 663 // processors are manufactured using the 32 nm process. 664 case 0x2f: // Westmere EX 665 *Type = X86::INTEL_COREI7; // "westmere" 666 *Subtype = X86::INTEL_COREI7_WESTMERE; 667 break; 668 case 0x2a: // Intel Core i7 processor. All processors are manufactured 669 // using the 32 nm process. 670 case 0x2d: 671 *Type = X86::INTEL_COREI7; //"sandybridge" 672 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 673 break; 674 case 0x3a: 675 case 0x3e: // Ivy Bridge EP 676 *Type = X86::INTEL_COREI7; // "ivybridge" 677 *Subtype = X86::INTEL_COREI7_IVYBRIDGE; 678 break; 679 680 // Haswell: 681 case 0x3c: 682 case 0x3f: 683 case 0x45: 684 case 0x46: 685 *Type = X86::INTEL_COREI7; // "haswell" 686 *Subtype = X86::INTEL_COREI7_HASWELL; 687 break; 688 689 // Broadwell: 690 case 0x3d: 691 case 0x47: 692 case 0x4f: 693 case 0x56: 694 *Type = X86::INTEL_COREI7; // "broadwell" 695 *Subtype = X86::INTEL_COREI7_BROADWELL; 696 break; 697 698 // Skylake: 699 case 0x4e: // Skylake mobile 700 case 0x5e: // Skylake desktop 701 case 0x8e: // Kaby Lake mobile 702 case 0x9e: // Kaby Lake desktop 703 *Type = X86::INTEL_COREI7; // "skylake" 704 *Subtype = X86::INTEL_COREI7_SKYLAKE; 705 break; 706 707 // Skylake Xeon: 708 case 0x55: 709 *Type = X86::INTEL_COREI7; 710 if (Features2 & (1 << (X86::FEATURE_AVX512BF16 - 32))) 711 *Subtype = X86::INTEL_COREI7_COOPERLAKE; // "cooperlake" 712 else if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) 713 *Subtype = X86::INTEL_COREI7_CASCADELAKE; // "cascadelake" 714 else 715 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 716 break; 717 718 // Cannonlake: 719 case 0x66: 720 *Type = X86::INTEL_COREI7; 721 *Subtype = X86::INTEL_COREI7_CANNONLAKE; // "cannonlake" 722 break; 723 724 // Icelake: 725 case 0x7d: 726 case 0x7e: 727 *Type = X86::INTEL_COREI7; 728 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; // "icelake-client" 729 break; 730 731 // Icelake Xeon: 732 case 0x6a: 733 case 0x6c: 734 *Type = X86::INTEL_COREI7; 735 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; // "icelake-server" 736 break; 737 738 case 0x1c: // Most 45 nm Intel Atom processors 739 case 0x26: // 45 nm Atom Lincroft 740 case 0x27: // 32 nm Atom Medfield 741 case 0x35: // 32 nm Atom Midview 742 case 0x36: // 32 nm Atom Midview 743 *Type = X86::INTEL_BONNELL; 744 break; // "bonnell" 745 746 // Atom Silvermont codes from the Intel software optimization guide. 747 case 0x37: 748 case 0x4a: 749 case 0x4d: 750 case 0x5a: 751 case 0x5d: 752 case 0x4c: // really airmont 753 *Type = X86::INTEL_SILVERMONT; 754 break; // "silvermont" 755 // Goldmont: 756 case 0x5c: // Apollo Lake 757 case 0x5f: // Denverton 758 *Type = X86::INTEL_GOLDMONT; 759 break; // "goldmont" 760 case 0x7a: 761 *Type = X86::INTEL_GOLDMONT_PLUS; 762 break; 763 case 0x86: 764 *Type = X86::INTEL_TREMONT; 765 break; 766 767 case 0x57: 768 *Type = X86::INTEL_KNL; // knl 769 break; 770 771 case 0x85: 772 *Type = X86::INTEL_KNM; // knm 773 break; 774 775 default: // Unknown family 6 CPU, try to guess. 776 // TODO detect tigerlake host 777 if (Features3 & (1 << (X86::FEATURE_AVX512VP2INTERSECT - 64))) { 778 *Type = X86::INTEL_COREI7; 779 *Subtype = X86::INTEL_COREI7_TIGERLAKE; 780 break; 781 } 782 783 if (Features & (1 << X86::FEATURE_AVX512VBMI2)) { 784 *Type = X86::INTEL_COREI7; 785 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; 786 break; 787 } 788 789 if (Features & (1 << X86::FEATURE_AVX512VBMI)) { 790 *Type = X86::INTEL_COREI7; 791 *Subtype = X86::INTEL_COREI7_CANNONLAKE; 792 break; 793 } 794 795 if (Features2 & (1 << (X86::FEATURE_AVX512BF16 - 32))) { 796 *Type = X86::INTEL_COREI7; 797 *Subtype = X86::INTEL_COREI7_COOPERLAKE; 798 break; 799 } 800 801 if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) { 802 *Type = X86::INTEL_COREI7; 803 *Subtype = X86::INTEL_COREI7_CASCADELAKE; 804 break; 805 } 806 807 if (Features & (1 << X86::FEATURE_AVX512VL)) { 808 *Type = X86::INTEL_COREI7; 809 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; 810 break; 811 } 812 813 if (Features & (1 << X86::FEATURE_AVX512ER)) { 814 *Type = X86::INTEL_KNL; // knl 815 break; 816 } 817 818 if (Features3 & (1 << (X86::FEATURE_CLFLUSHOPT - 64))) { 819 if (Features3 & (1 << (X86::FEATURE_SHA - 64))) { 820 *Type = X86::INTEL_GOLDMONT; 821 } else { 822 *Type = X86::INTEL_COREI7; 823 *Subtype = X86::INTEL_COREI7_SKYLAKE; 824 } 825 break; 826 } 827 if (Features3 & (1 << (X86::FEATURE_ADX - 64))) { 828 *Type = X86::INTEL_COREI7; 829 *Subtype = X86::INTEL_COREI7_BROADWELL; 830 break; 831 } 832 if (Features & (1 << X86::FEATURE_AVX2)) { 833 *Type = X86::INTEL_COREI7; 834 *Subtype = X86::INTEL_COREI7_HASWELL; 835 break; 836 } 837 if (Features & (1 << X86::FEATURE_AVX)) { 838 *Type = X86::INTEL_COREI7; 839 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 840 break; 841 } 842 if (Features & (1 << X86::FEATURE_SSE4_2)) { 843 if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { 844 *Type = X86::INTEL_SILVERMONT; 845 } else { 846 *Type = X86::INTEL_COREI7; 847 *Subtype = X86::INTEL_COREI7_NEHALEM; 848 } 849 break; 850 } 851 if (Features & (1 << X86::FEATURE_SSE4_1)) { 852 *Type = X86::INTEL_CORE2; // "penryn" 853 *Subtype = X86::INTEL_CORE2_45; 854 break; 855 } 856 if (Features & (1 << X86::FEATURE_SSSE3)) { 857 if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { 858 *Type = X86::INTEL_BONNELL; // "bonnell" 859 } else { 860 *Type = X86::INTEL_CORE2; // "core2" 861 *Subtype = X86::INTEL_CORE2_65; 862 } 863 break; 864 } 865 if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { 866 *Type = X86::INTEL_CORE2; // "core2" 867 *Subtype = X86::INTEL_CORE2_65; 868 break; 869 } 870 if (Features & (1 << X86::FEATURE_SSE3)) { 871 *Type = X86::INTEL_CORE_DUO; 872 break; 873 } 874 if (Features & (1 << X86::FEATURE_SSE2)) { 875 *Type = X86::INTEL_PENTIUM_M; 876 break; 877 } 878 if (Features & (1 << X86::FEATURE_SSE)) { 879 *Type = X86::INTEL_PENTIUM_III; 880 break; 881 } 882 if (Features & (1 << X86::FEATURE_MMX)) { 883 *Type = X86::INTEL_PENTIUM_II; 884 break; 885 } 886 *Type = X86::INTEL_PENTIUM_PRO; 887 break; 888 } 889 break; 890 case 15: { 891 if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { 892 *Type = X86::INTEL_NOCONA; 893 break; 894 } 895 if (Features & (1 << X86::FEATURE_SSE3)) { 896 *Type = X86::INTEL_PRESCOTT; 897 break; 898 } 899 *Type = X86::INTEL_PENTIUM_IV; 900 break; 901 } 902 default: 903 break; /*"generic"*/ 904 } 905 } 906 907 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 908 unsigned Features, unsigned *Type, 909 unsigned *Subtype) { 910 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 911 // appears to be no way to generate the wide variety of AMD-specific targets 912 // from the information returned from CPUID. 913 switch (Family) { 914 case 4: 915 *Type = X86::AMD_i486; 916 break; 917 case 5: 918 *Type = X86::AMDPENTIUM; 919 switch (Model) { 920 case 6: 921 case 7: 922 *Subtype = X86::AMDPENTIUM_K6; 923 break; // "k6" 924 case 8: 925 *Subtype = X86::AMDPENTIUM_K62; 926 break; // "k6-2" 927 case 9: 928 case 13: 929 *Subtype = X86::AMDPENTIUM_K63; 930 break; // "k6-3" 931 case 10: 932 *Subtype = X86::AMDPENTIUM_GEODE; 933 break; // "geode" 934 } 935 break; 936 case 6: 937 if (Features & (1 << X86::FEATURE_SSE)) { 938 *Type = X86::AMD_ATHLON_XP; 939 break; // "athlon-xp" 940 } 941 *Type = X86::AMD_ATHLON; 942 break; // "athlon" 943 case 15: 944 if (Features & (1 << X86::FEATURE_SSE3)) { 945 *Type = X86::AMD_K8SSE3; 946 break; // "k8-sse3" 947 } 948 *Type = X86::AMD_K8; 949 break; // "k8" 950 case 16: 951 *Type = X86::AMDFAM10H; // "amdfam10" 952 switch (Model) { 953 case 2: 954 *Subtype = X86::AMDFAM10H_BARCELONA; 955 break; 956 case 4: 957 *Subtype = X86::AMDFAM10H_SHANGHAI; 958 break; 959 case 8: 960 *Subtype = X86::AMDFAM10H_ISTANBUL; 961 break; 962 } 963 break; 964 case 20: 965 *Type = X86::AMD_BTVER1; 966 break; // "btver1"; 967 case 21: 968 *Type = X86::AMDFAM15H; 969 if (Model >= 0x60 && Model <= 0x7f) { 970 *Subtype = X86::AMDFAM15H_BDVER4; 971 break; // "bdver4"; 60h-7Fh: Excavator 972 } 973 if (Model >= 0x30 && Model <= 0x3f) { 974 *Subtype = X86::AMDFAM15H_BDVER3; 975 break; // "bdver3"; 30h-3Fh: Steamroller 976 } 977 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) { 978 *Subtype = X86::AMDFAM15H_BDVER2; 979 break; // "bdver2"; 02h, 10h-1Fh: Piledriver 980 } 981 if (Model <= 0x0f) { 982 *Subtype = X86::AMDFAM15H_BDVER1; 983 break; // "bdver1"; 00h-0Fh: Bulldozer 984 } 985 break; 986 case 22: 987 *Type = X86::AMD_BTVER2; 988 break; // "btver2" 989 case 23: 990 *Type = X86::AMDFAM17H; 991 if ((Model >= 0x30 && Model <= 0x3f) || Model == 0x71) { 992 *Subtype = X86::AMDFAM17H_ZNVER2; 993 break; // "znver2"; 30h-3fh, 71h: Zen2 994 } 995 if (Model <= 0x0f) { 996 *Subtype = X86::AMDFAM17H_ZNVER1; 997 break; // "znver1"; 00h-0Fh: Zen1 998 } 999 break; 1000 default: 1001 break; // "generic" 1002 } 1003 } 1004 1005 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 1006 unsigned *FeaturesOut, unsigned *Features2Out, 1007 unsigned *Features3Out) { 1008 unsigned Features = 0; 1009 unsigned Features2 = 0; 1010 unsigned Features3 = 0; 1011 unsigned EAX, EBX; 1012 1013 auto setFeature = [&](unsigned F) { 1014 if (F < 32) 1015 Features |= 1U << (F & 0x1f); 1016 else if (F < 64) 1017 Features2 |= 1U << ((F - 32) & 0x1f); 1018 else if (F < 96) 1019 Features3 |= 1U << ((F - 64) & 0x1f); 1020 else 1021 llvm_unreachable("Unexpected FeatureBit"); 1022 }; 1023 1024 if ((EDX >> 15) & 1) 1025 setFeature(X86::FEATURE_CMOV); 1026 if ((EDX >> 23) & 1) 1027 setFeature(X86::FEATURE_MMX); 1028 if ((EDX >> 25) & 1) 1029 setFeature(X86::FEATURE_SSE); 1030 if ((EDX >> 26) & 1) 1031 setFeature(X86::FEATURE_SSE2); 1032 1033 if ((ECX >> 0) & 1) 1034 setFeature(X86::FEATURE_SSE3); 1035 if ((ECX >> 1) & 1) 1036 setFeature(X86::FEATURE_PCLMUL); 1037 if ((ECX >> 9) & 1) 1038 setFeature(X86::FEATURE_SSSE3); 1039 if ((ECX >> 12) & 1) 1040 setFeature(X86::FEATURE_FMA); 1041 if ((ECX >> 19) & 1) 1042 setFeature(X86::FEATURE_SSE4_1); 1043 if ((ECX >> 20) & 1) 1044 setFeature(X86::FEATURE_SSE4_2); 1045 if ((ECX >> 23) & 1) 1046 setFeature(X86::FEATURE_POPCNT); 1047 if ((ECX >> 25) & 1) 1048 setFeature(X86::FEATURE_AES); 1049 1050 if ((ECX >> 22) & 1) 1051 setFeature(X86::FEATURE_MOVBE); 1052 1053 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1054 // indicates that the AVX registers will be saved and restored on context 1055 // switch, then we have full AVX support. 1056 const unsigned AVXBits = (1 << 27) | (1 << 28); 1057 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 1058 ((EAX & 0x6) == 0x6); 1059 #if defined(__APPLE__) 1060 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1061 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1062 // set right now. 1063 bool HasAVX512Save = true; 1064 #else 1065 // AVX512 requires additional context to be saved by the OS. 1066 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 1067 #endif 1068 1069 if (HasAVX) 1070 setFeature(X86::FEATURE_AVX); 1071 1072 bool HasLeaf7 = 1073 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1074 1075 if (HasLeaf7 && ((EBX >> 3) & 1)) 1076 setFeature(X86::FEATURE_BMI); 1077 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 1078 setFeature(X86::FEATURE_AVX2); 1079 if (HasLeaf7 && ((EBX >> 8) & 1)) 1080 setFeature(X86::FEATURE_BMI2); 1081 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 1082 setFeature(X86::FEATURE_AVX512F); 1083 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 1084 setFeature(X86::FEATURE_AVX512DQ); 1085 if (HasLeaf7 && ((EBX >> 19) & 1)) 1086 setFeature(X86::FEATURE_ADX); 1087 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 1088 setFeature(X86::FEATURE_AVX512IFMA); 1089 if (HasLeaf7 && ((EBX >> 23) & 1)) 1090 setFeature(X86::FEATURE_CLFLUSHOPT); 1091 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 1092 setFeature(X86::FEATURE_AVX512PF); 1093 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 1094 setFeature(X86::FEATURE_AVX512ER); 1095 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 1096 setFeature(X86::FEATURE_AVX512CD); 1097 if (HasLeaf7 && ((EBX >> 29) & 1)) 1098 setFeature(X86::FEATURE_SHA); 1099 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 1100 setFeature(X86::FEATURE_AVX512BW); 1101 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 1102 setFeature(X86::FEATURE_AVX512VL); 1103 1104 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 1105 setFeature(X86::FEATURE_AVX512VBMI); 1106 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save) 1107 setFeature(X86::FEATURE_AVX512VBMI2); 1108 if (HasLeaf7 && ((ECX >> 8) & 1)) 1109 setFeature(X86::FEATURE_GFNI); 1110 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX) 1111 setFeature(X86::FEATURE_VPCLMULQDQ); 1112 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save) 1113 setFeature(X86::FEATURE_AVX512VNNI); 1114 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save) 1115 setFeature(X86::FEATURE_AVX512BITALG); 1116 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1117 setFeature(X86::FEATURE_AVX512VPOPCNTDQ); 1118 1119 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1120 setFeature(X86::FEATURE_AVX5124VNNIW); 1121 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1122 setFeature(X86::FEATURE_AVX5124FMAPS); 1123 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save) 1124 setFeature(X86::FEATURE_AVX512VP2INTERSECT); 1125 1126 bool HasLeaf7Subleaf1 = 1127 MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1128 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save) 1129 setFeature(X86::FEATURE_AVX512BF16); 1130 1131 unsigned MaxExtLevel; 1132 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1133 1134 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1135 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1136 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1137 setFeature(X86::FEATURE_SSE4_A); 1138 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1139 setFeature(X86::FEATURE_XOP); 1140 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1141 setFeature(X86::FEATURE_FMA4); 1142 1143 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1144 setFeature(X86::FEATURE_EM64T); 1145 1146 *FeaturesOut = Features; 1147 *Features2Out = Features2; 1148 *Features3Out = Features3; 1149 } 1150 1151 StringRef sys::getHostCPUName() { 1152 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1153 unsigned MaxLeaf, Vendor; 1154 1155 #if defined(__GNUC__) || defined(__clang__) 1156 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here 1157 // and simplify it to not invoke __cpuid (like cpu_model.c in 1158 // compiler-rt/lib/builtins/cpu_model.c? 1159 // Opting for the second option. 1160 if(!isCpuIdSupported()) 1161 return "generic"; 1162 #endif 1163 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) 1164 return "generic"; 1165 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1166 1167 unsigned Brand_id = EBX & 0xff; 1168 unsigned Family = 0, Model = 0; 1169 unsigned Features = 0, Features2 = 0, Features3 = 0; 1170 detectX86FamilyModel(EAX, &Family, &Model); 1171 getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2, &Features3); 1172 1173 unsigned Type = 0; 1174 unsigned Subtype = 0; 1175 1176 if (Vendor == SIG_INTEL) { 1177 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, 1178 Features2, Features3, &Type, &Subtype); 1179 } else if (Vendor == SIG_AMD) { 1180 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1181 } 1182 1183 // Check subtypes first since those are more specific. 1184 #define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \ 1185 if (Subtype == X86::ENUM) \ 1186 return ARCHNAME; 1187 #include "llvm/Support/X86TargetParser.def" 1188 1189 // Now check types. 1190 #define X86_CPU_TYPE(ARCHNAME, ENUM) \ 1191 if (Type == X86::ENUM) \ 1192 return ARCHNAME; 1193 #include "llvm/Support/X86TargetParser.def" 1194 1195 return "generic"; 1196 } 1197 1198 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1199 StringRef sys::getHostCPUName() { 1200 host_basic_info_data_t hostInfo; 1201 mach_msg_type_number_t infoCount; 1202 1203 infoCount = HOST_BASIC_INFO_COUNT; 1204 mach_port_t hostPort = mach_host_self(); 1205 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1206 &infoCount); 1207 mach_port_deallocate(mach_task_self(), hostPort); 1208 1209 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1210 return "generic"; 1211 1212 switch (hostInfo.cpu_subtype) { 1213 case CPU_SUBTYPE_POWERPC_601: 1214 return "601"; 1215 case CPU_SUBTYPE_POWERPC_602: 1216 return "602"; 1217 case CPU_SUBTYPE_POWERPC_603: 1218 return "603"; 1219 case CPU_SUBTYPE_POWERPC_603e: 1220 return "603e"; 1221 case CPU_SUBTYPE_POWERPC_603ev: 1222 return "603ev"; 1223 case CPU_SUBTYPE_POWERPC_604: 1224 return "604"; 1225 case CPU_SUBTYPE_POWERPC_604e: 1226 return "604e"; 1227 case CPU_SUBTYPE_POWERPC_620: 1228 return "620"; 1229 case CPU_SUBTYPE_POWERPC_750: 1230 return "750"; 1231 case CPU_SUBTYPE_POWERPC_7400: 1232 return "7400"; 1233 case CPU_SUBTYPE_POWERPC_7450: 1234 return "7450"; 1235 case CPU_SUBTYPE_POWERPC_970: 1236 return "970"; 1237 default:; 1238 } 1239 1240 return "generic"; 1241 } 1242 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1243 StringRef sys::getHostCPUName() { 1244 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1245 StringRef Content = P ? P->getBuffer() : ""; 1246 return detail::getHostCPUNameForPowerPC(Content); 1247 } 1248 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1249 StringRef sys::getHostCPUName() { 1250 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1251 StringRef Content = P ? P->getBuffer() : ""; 1252 return detail::getHostCPUNameForARM(Content); 1253 } 1254 #elif defined(__linux__) && defined(__s390x__) 1255 StringRef sys::getHostCPUName() { 1256 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1257 StringRef Content = P ? P->getBuffer() : ""; 1258 return detail::getHostCPUNameForS390x(Content); 1259 } 1260 #elif defined(__APPLE__) && defined(__aarch64__) 1261 StringRef sys::getHostCPUName() { 1262 return "cyclone"; 1263 } 1264 #elif defined(__APPLE__) && defined(__arm__) 1265 StringRef sys::getHostCPUName() { 1266 host_basic_info_data_t hostInfo; 1267 mach_msg_type_number_t infoCount; 1268 1269 infoCount = HOST_BASIC_INFO_COUNT; 1270 mach_port_t hostPort = mach_host_self(); 1271 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1272 &infoCount); 1273 mach_port_deallocate(mach_task_self(), hostPort); 1274 1275 if (hostInfo.cpu_type != CPU_TYPE_ARM) { 1276 assert(false && "CPUType not equal to ARM should not be possible on ARM"); 1277 return "generic"; 1278 } 1279 switch (hostInfo.cpu_subtype) { 1280 case CPU_SUBTYPE_ARM_V7S: 1281 return "swift"; 1282 default:; 1283 } 1284 1285 return "generic"; 1286 } 1287 #else 1288 StringRef sys::getHostCPUName() { return "generic"; } 1289 #endif 1290 1291 #if defined(__linux__) && (defined(__i386__) || defined(__x86_64__)) 1292 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1293 // using the number of unique physical/core id pairs. The following 1294 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1295 int computeHostNumPhysicalCores() { 1296 // Enabled represents the number of physical id/core id pairs with at least 1297 // one processor id enabled by the CPU affinity mask. 1298 cpu_set_t Affinity, Enabled; 1299 if (sched_getaffinity(0, sizeof(Affinity), &Affinity) != 0) 1300 return -1; 1301 CPU_ZERO(&Enabled); 1302 1303 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1304 // mmapped because it appears to have 0 size. 1305 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1306 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1307 if (std::error_code EC = Text.getError()) { 1308 llvm::errs() << "Can't read " 1309 << "/proc/cpuinfo: " << EC.message() << "\n"; 1310 return -1; 1311 } 1312 SmallVector<StringRef, 8> strs; 1313 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1314 /*KeepEmpty=*/false); 1315 int CurProcessor = -1; 1316 int CurPhysicalId = -1; 1317 int CurSiblings = -1; 1318 int CurCoreId = -1; 1319 for (StringRef Line : strs) { 1320 std::pair<StringRef, StringRef> Data = Line.split(':'); 1321 auto Name = Data.first.trim(); 1322 auto Val = Data.second.trim(); 1323 // These fields are available if the kernel is configured with CONFIG_SMP. 1324 if (Name == "processor") 1325 Val.getAsInteger(10, CurProcessor); 1326 else if (Name == "physical id") 1327 Val.getAsInteger(10, CurPhysicalId); 1328 else if (Name == "siblings") 1329 Val.getAsInteger(10, CurSiblings); 1330 else if (Name == "core id") { 1331 Val.getAsInteger(10, CurCoreId); 1332 // The processor id corresponds to an index into cpu_set_t. 1333 if (CPU_ISSET(CurProcessor, &Affinity)) 1334 CPU_SET(CurPhysicalId * CurSiblings + CurCoreId, &Enabled); 1335 } 1336 } 1337 return CPU_COUNT(&Enabled); 1338 } 1339 #elif defined(__APPLE__) && defined(__x86_64__) 1340 #include <sys/param.h> 1341 #include <sys/sysctl.h> 1342 1343 // Gets the number of *physical cores* on the machine. 1344 int computeHostNumPhysicalCores() { 1345 uint32_t count; 1346 size_t len = sizeof(count); 1347 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1348 if (count < 1) { 1349 int nm[2]; 1350 nm[0] = CTL_HW; 1351 nm[1] = HW_AVAILCPU; 1352 sysctl(nm, 2, &count, &len, NULL, 0); 1353 if (count < 1) 1354 return -1; 1355 } 1356 return count; 1357 } 1358 #elif defined(_WIN32) && LLVM_ENABLE_THREADS != 0 1359 // Defined in llvm/lib/Support/Windows/Threading.inc 1360 int computeHostNumPhysicalCores(); 1361 #else 1362 // On other systems, return -1 to indicate unknown. 1363 static int computeHostNumPhysicalCores() { return -1; } 1364 #endif 1365 1366 int sys::getHostNumPhysicalCores() { 1367 static int NumCores = computeHostNumPhysicalCores(); 1368 return NumCores; 1369 } 1370 1371 #if defined(__i386__) || defined(_M_IX86) || \ 1372 defined(__x86_64__) || defined(_M_X64) 1373 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1374 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1375 unsigned MaxLevel; 1376 union { 1377 unsigned u[3]; 1378 char c[12]; 1379 } text; 1380 1381 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1382 MaxLevel < 1) 1383 return false; 1384 1385 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1386 1387 Features["cx8"] = (EDX >> 8) & 1; 1388 Features["cmov"] = (EDX >> 15) & 1; 1389 Features["mmx"] = (EDX >> 23) & 1; 1390 Features["fxsr"] = (EDX >> 24) & 1; 1391 Features["sse"] = (EDX >> 25) & 1; 1392 Features["sse2"] = (EDX >> 26) & 1; 1393 1394 Features["sse3"] = (ECX >> 0) & 1; 1395 Features["pclmul"] = (ECX >> 1) & 1; 1396 Features["ssse3"] = (ECX >> 9) & 1; 1397 Features["cx16"] = (ECX >> 13) & 1; 1398 Features["sse4.1"] = (ECX >> 19) & 1; 1399 Features["sse4.2"] = (ECX >> 20) & 1; 1400 Features["movbe"] = (ECX >> 22) & 1; 1401 Features["popcnt"] = (ECX >> 23) & 1; 1402 Features["aes"] = (ECX >> 25) & 1; 1403 Features["rdrnd"] = (ECX >> 30) & 1; 1404 1405 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1406 // indicates that the AVX registers will be saved and restored on context 1407 // switch, then we have full AVX support. 1408 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1409 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1410 #if defined(__APPLE__) 1411 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1412 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1413 // set right now. 1414 bool HasAVX512Save = true; 1415 #else 1416 // AVX512 requires additional context to be saved by the OS. 1417 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1418 #endif 1419 1420 Features["avx"] = HasAVXSave; 1421 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave; 1422 // Only enable XSAVE if OS has enabled support for saving YMM state. 1423 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave; 1424 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave; 1425 1426 unsigned MaxExtLevel; 1427 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1428 1429 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1430 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1431 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1); 1432 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1433 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1434 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1435 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1436 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1437 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1438 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1439 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1440 1441 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1); 1442 1443 // Miscellaneous memory related features, detected by 1444 // using the 0x80000008 leaf of the CPUID instruction 1445 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1446 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX); 1447 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1448 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1); 1449 1450 bool HasLeaf7 = 1451 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1452 1453 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1454 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1455 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1456 // AVX2 is only supported if we have the OS save support from AVX. 1457 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave; 1458 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1459 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1460 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1461 // AVX512 is only supported if the OS supports the context save for it. 1462 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1463 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1464 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1465 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1466 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1467 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1468 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1469 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1470 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1471 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1472 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1473 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1474 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1475 1476 Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1); 1477 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1478 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1479 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1); 1480 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save; 1481 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1); 1482 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1); 1483 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave; 1484 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave; 1485 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save; 1486 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save; 1487 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1488 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1); 1489 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1); 1490 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1); 1491 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1); 1492 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1); 1493 1494 Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1); 1495 Features["tsxldtrk"] = HasLeaf7 && ((EDX >> 16) & 1); 1496 // There are two CPUID leafs which information associated with the pconfig 1497 // instruction: 1498 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th 1499 // bit of EDX), while the EAX=0x1b leaf returns information on the 1500 // availability of specific pconfig leafs. 1501 // The target feature here only refers to the the first of these two. 1502 // Users might need to check for the availability of specific pconfig 1503 // leaves using cpuid, since that information is ignored while 1504 // detecting features using the "-march=native" flag. 1505 // For more info, see X86 ISA docs. 1506 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1); 1507 bool HasLeaf7Subleaf1 = 1508 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1509 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save; 1510 1511 bool HasLeafD = MaxLevel >= 0xd && 1512 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1513 1514 // Only enable XSAVE if OS has enabled support for saving YMM state. 1515 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave; 1516 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave; 1517 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave; 1518 1519 bool HasLeaf14 = MaxLevel >= 0x14 && 1520 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX); 1521 1522 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1); 1523 1524 return true; 1525 } 1526 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1527 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1528 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1529 if (!P) 1530 return false; 1531 1532 SmallVector<StringRef, 32> Lines; 1533 P->getBuffer().split(Lines, "\n"); 1534 1535 SmallVector<StringRef, 32> CPUFeatures; 1536 1537 // Look for the CPU features. 1538 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1539 if (Lines[I].startswith("Features")) { 1540 Lines[I].split(CPUFeatures, ' '); 1541 break; 1542 } 1543 1544 #if defined(__aarch64__) 1545 // Keep track of which crypto features we have seen 1546 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1547 uint32_t crypto = 0; 1548 #endif 1549 1550 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1551 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1552 #if defined(__aarch64__) 1553 .Case("asimd", "neon") 1554 .Case("fp", "fp-armv8") 1555 .Case("crc32", "crc") 1556 #else 1557 .Case("half", "fp16") 1558 .Case("neon", "neon") 1559 .Case("vfpv3", "vfp3") 1560 .Case("vfpv3d16", "d16") 1561 .Case("vfpv4", "vfp4") 1562 .Case("idiva", "hwdiv-arm") 1563 .Case("idivt", "hwdiv") 1564 #endif 1565 .Default(""); 1566 1567 #if defined(__aarch64__) 1568 // We need to check crypto separately since we need all of the crypto 1569 // extensions to enable the subtarget feature 1570 if (CPUFeatures[I] == "aes") 1571 crypto |= CAP_AES; 1572 else if (CPUFeatures[I] == "pmull") 1573 crypto |= CAP_PMULL; 1574 else if (CPUFeatures[I] == "sha1") 1575 crypto |= CAP_SHA1; 1576 else if (CPUFeatures[I] == "sha2") 1577 crypto |= CAP_SHA2; 1578 #endif 1579 1580 if (LLVMFeatureStr != "") 1581 Features[LLVMFeatureStr] = true; 1582 } 1583 1584 #if defined(__aarch64__) 1585 // If we have all crypto bits we can add the feature 1586 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1587 Features["crypto"] = true; 1588 #endif 1589 1590 return true; 1591 } 1592 #elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64)) 1593 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1594 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE)) 1595 Features["neon"] = true; 1596 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE)) 1597 Features["crc"] = true; 1598 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) 1599 Features["crypto"] = true; 1600 1601 return true; 1602 } 1603 #else 1604 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1605 #endif 1606 1607 std::string sys::getProcessTriple() { 1608 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1609 Triple PT(Triple::normalize(TargetTripleString)); 1610 1611 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1612 PT = PT.get64BitArchVariant(); 1613 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1614 PT = PT.get32BitArchVariant(); 1615 1616 return PT.str(); 1617 } 1618