1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the operating system Host concept. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Support/Host.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringRef.h" 17 #include "llvm/ADT/StringSwitch.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/Config/config.h" 20 #include "llvm/Support/Debug.h" 21 #include "llvm/Support/FileSystem.h" 22 #include "llvm/Support/raw_ostream.h" 23 #include <string.h> 24 25 // Include the platform-specific parts of this class. 26 #ifdef LLVM_ON_UNIX 27 #include "Unix/Host.inc" 28 #endif 29 #ifdef LLVM_ON_WIN32 30 #include "Windows/Host.inc" 31 #endif 32 #ifdef _MSC_VER 33 #include <intrin.h> 34 #endif 35 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 36 #include <mach/mach.h> 37 #include <mach/mach_host.h> 38 #include <mach/host_info.h> 39 #include <mach/machine.h> 40 #endif 41 42 #define DEBUG_TYPE "host-detection" 43 44 //===----------------------------------------------------------------------===// 45 // 46 // Implementations of the CPU detection routines 47 // 48 //===----------------------------------------------------------------------===// 49 50 using namespace llvm; 51 52 #if defined(__linux__) 53 static ssize_t LLVM_ATTRIBUTE_UNUSED readCpuInfo(void *Buf, size_t Size) { 54 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting 55 // memory buffer because the 'file' has 0 size (it can be read from only 56 // as a stream). 57 58 int FD; 59 std::error_code EC = sys::fs::openFileForRead("/proc/cpuinfo", FD); 60 if (EC) { 61 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << EC.message() << "\n"); 62 return -1; 63 } 64 int Ret = read(FD, Buf, Size); 65 int CloseStatus = close(FD); 66 if (CloseStatus) 67 return -1; 68 return Ret; 69 } 70 #endif 71 72 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\ 73 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) 74 75 /// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in the 76 /// specified arguments. If we can't run cpuid on the host, return true. 77 static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 78 unsigned *rECX, unsigned *rEDX) { 79 #if defined(__GNUC__) || defined(__clang__) 80 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) 81 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. 82 asm ("movq\t%%rbx, %%rsi\n\t" 83 "cpuid\n\t" 84 "xchgq\t%%rbx, %%rsi\n\t" 85 : "=a" (*rEAX), 86 "=S" (*rEBX), 87 "=c" (*rECX), 88 "=d" (*rEDX) 89 : "a" (value)); 90 return false; 91 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) 92 asm ("movl\t%%ebx, %%esi\n\t" 93 "cpuid\n\t" 94 "xchgl\t%%ebx, %%esi\n\t" 95 : "=a" (*rEAX), 96 "=S" (*rEBX), 97 "=c" (*rECX), 98 "=d" (*rEDX) 99 : "a" (value)); 100 return false; 101 // pedantic #else returns to appease -Wunreachable-code (so we don't generate 102 // postprocessed code that looks like "return true; return false;") 103 #else 104 return true; 105 #endif 106 #elif defined(_MSC_VER) 107 // The MSVC intrinsic is portable across x86 and x64. 108 int registers[4]; 109 __cpuid(registers, value); 110 *rEAX = registers[0]; 111 *rEBX = registers[1]; 112 *rECX = registers[2]; 113 *rEDX = registers[3]; 114 return false; 115 #else 116 return true; 117 #endif 118 } 119 120 /// GetX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the 121 /// 4 values in the specified arguments. If we can't run cpuid on the host, 122 /// return true. 123 static bool GetX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 124 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 125 unsigned *rEDX) { 126 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) 127 #if defined(__GNUC__) 128 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. 129 asm ("movq\t%%rbx, %%rsi\n\t" 130 "cpuid\n\t" 131 "xchgq\t%%rbx, %%rsi\n\t" 132 : "=a" (*rEAX), 133 "=S" (*rEBX), 134 "=c" (*rECX), 135 "=d" (*rEDX) 136 : "a" (value), 137 "c" (subleaf)); 138 return false; 139 #elif defined(_MSC_VER) 140 int registers[4]; 141 __cpuidex(registers, value, subleaf); 142 *rEAX = registers[0]; 143 *rEBX = registers[1]; 144 *rECX = registers[2]; 145 *rEDX = registers[3]; 146 return false; 147 #else 148 return true; 149 #endif 150 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) 151 #if defined(__GNUC__) 152 asm ("movl\t%%ebx, %%esi\n\t" 153 "cpuid\n\t" 154 "xchgl\t%%ebx, %%esi\n\t" 155 : "=a" (*rEAX), 156 "=S" (*rEBX), 157 "=c" (*rECX), 158 "=d" (*rEDX) 159 : "a" (value), 160 "c" (subleaf)); 161 return false; 162 #elif defined(_MSC_VER) 163 __asm { 164 mov eax,value 165 mov ecx,subleaf 166 cpuid 167 mov esi,rEAX 168 mov dword ptr [esi],eax 169 mov esi,rEBX 170 mov dword ptr [esi],ebx 171 mov esi,rECX 172 mov dword ptr [esi],ecx 173 mov esi,rEDX 174 mov dword ptr [esi],edx 175 } 176 return false; 177 #else 178 return true; 179 #endif 180 #else 181 return true; 182 #endif 183 } 184 185 static bool GetX86XCR0(unsigned *rEAX, unsigned *rEDX) { 186 #if defined(__GNUC__) 187 // Check xgetbv; this uses a .byte sequence instead of the instruction 188 // directly because older assemblers do not include support for xgetbv and 189 // there is no easy way to conditionally compile based on the assembler used. 190 __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (*rEAX), "=d" (*rEDX) : "c" (0)); 191 return false; 192 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 193 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 194 *rEAX = Result; 195 *rEDX = Result >> 32; 196 return false; 197 #else 198 return true; 199 #endif 200 } 201 202 static void DetectX86FamilyModel(unsigned EAX, unsigned &Family, 203 unsigned &Model) { 204 Family = (EAX >> 8) & 0xf; // Bits 8 - 11 205 Model = (EAX >> 4) & 0xf; // Bits 4 - 7 206 if (Family == 6 || Family == 0xf) { 207 if (Family == 0xf) 208 // Examine extended family ID if family ID is F. 209 Family += (EAX >> 20) & 0xff; // Bits 20 - 27 210 // Examine extended model ID if family ID is 6 or F. 211 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 212 } 213 } 214 215 StringRef sys::getHostCPUName() { 216 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 217 if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX)) 218 return "generic"; 219 unsigned Family = 0; 220 unsigned Model = 0; 221 DetectX86FamilyModel(EAX, Family, Model); 222 223 union { 224 unsigned u[3]; 225 char c[12]; 226 } text; 227 228 unsigned MaxLeaf; 229 GetX86CpuIDAndInfo(0, &MaxLeaf, text.u+0, text.u+2, text.u+1); 230 231 bool HasMMX = (EDX >> 23) & 1; 232 bool HasSSE = (EDX >> 25) & 1; 233 bool HasSSE2 = (EDX >> 26) & 1; 234 bool HasSSE3 = (ECX >> 0) & 1; 235 bool HasSSSE3 = (ECX >> 9) & 1; 236 bool HasSSE41 = (ECX >> 19) & 1; 237 bool HasSSE42 = (ECX >> 20) & 1; 238 bool HasMOVBE = (ECX >> 22) & 1; 239 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 240 // indicates that the AVX registers will be saved and restored on context 241 // switch, then we have full AVX support. 242 const unsigned AVXBits = (1 << 27) | (1 << 28); 243 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !GetX86XCR0(&EAX, &EDX) && 244 ((EAX & 0x6) == 0x6); 245 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 246 bool HasLeaf7 = MaxLeaf >= 0x7 && 247 !GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 248 bool HasADX = HasLeaf7 && ((EBX >> 19) & 1); 249 bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20); 250 bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1); 251 252 GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 253 bool Em64T = (EDX >> 29) & 0x1; 254 bool HasTBM = (ECX >> 21) & 0x1; 255 256 if (memcmp(text.c, "GenuineIntel", 12) == 0) { 257 switch (Family) { 258 case 3: 259 return "i386"; 260 case 4: 261 switch (Model) { 262 case 0: // Intel486 DX processors 263 case 1: // Intel486 DX processors 264 case 2: // Intel486 SX processors 265 case 3: // Intel487 processors, IntelDX2 OverDrive processors, 266 // IntelDX2 processors 267 case 4: // Intel486 SL processor 268 case 5: // IntelSX2 processors 269 case 7: // Write-Back Enhanced IntelDX2 processors 270 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors 271 default: return "i486"; 272 } 273 case 5: 274 switch (Model) { 275 case 1: // Pentium OverDrive processor for Pentium processor (60, 66), 276 // Pentium processors (60, 66) 277 case 2: // Pentium OverDrive processor for Pentium processor (75, 90, 278 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133, 279 // 150, 166, 200) 280 case 3: // Pentium OverDrive processors for Intel486 processor-based 281 // systems 282 return "pentium"; 283 284 case 4: // Pentium OverDrive processor with MMX technology for Pentium 285 // processor (75, 90, 100, 120, 133), Pentium processor with 286 // MMX technology (166, 200) 287 return "pentium-mmx"; 288 289 default: return "pentium"; 290 } 291 case 6: 292 switch (Model) { 293 case 0x01: // Pentium Pro processor 294 return "pentiumpro"; 295 296 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 297 // model 03 298 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 299 // model 05, and Intel Celeron processor, model 05 300 case 0x06: // Celeron processor, model 06 301 return "pentium2"; 302 303 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 304 // processor, model 07 305 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 306 // model 08, and Celeron processor, model 08 307 case 0x0a: // Pentium III Xeon processor, model 0Ah 308 case 0x0b: // Pentium III processor, model 0Bh 309 return "pentium3"; 310 311 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 312 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 313 // 0Dh. All processors are manufactured using the 90 nm process. 314 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 315 // Integrated Processor with Intel QuickAssist Technology 316 return "pentium-m"; 317 318 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 319 // 0Eh. All processors are manufactured using the 65 nm process. 320 return "yonah"; 321 322 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 323 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 324 // mobile processor, Intel Core 2 Extreme processor, Intel 325 // Pentium Dual-Core processor, Intel Xeon processor, model 326 // 0Fh. All processors are manufactured using the 65 nm process. 327 case 0x16: // Intel Celeron processor model 16h. All processors are 328 // manufactured using the 65 nm process 329 return "core2"; 330 331 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 332 // 17h. All processors are manufactured using the 45 nm process. 333 // 334 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 335 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 336 // the 45 nm process. 337 return "penryn"; 338 339 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 340 // processors are manufactured using the 45 nm process. 341 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 342 // As found in a Summer 2010 model iMac. 343 case 0x2e: // Nehalem EX 344 return "nehalem"; 345 case 0x25: // Intel Core i7, laptop version. 346 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 347 // processors are manufactured using the 32 nm process. 348 case 0x2f: // Westmere EX 349 return "westmere"; 350 351 case 0x2a: // Intel Core i7 processor. All processors are manufactured 352 // using the 32 nm process. 353 case 0x2d: 354 return "sandybridge"; 355 356 case 0x3a: 357 case 0x3e: // Ivy Bridge EP 358 return "ivybridge"; 359 360 // Haswell: 361 case 0x3c: 362 case 0x3f: 363 case 0x45: 364 case 0x46: 365 return "haswell"; 366 367 // Broadwell: 368 case 0x3d: 369 case 0x47: 370 case 0x4f: 371 case 0x56: 372 return "broadwell"; 373 374 // Skylake: 375 case 0x4e: 376 return "skylake-avx512"; 377 case 0x5e: 378 return "skylake"; 379 380 case 0x1c: // Most 45 nm Intel Atom processors 381 case 0x26: // 45 nm Atom Lincroft 382 case 0x27: // 32 nm Atom Medfield 383 case 0x35: // 32 nm Atom Midview 384 case 0x36: // 32 nm Atom Midview 385 return "bonnell"; 386 387 // Atom Silvermont codes from the Intel software optimization guide. 388 case 0x37: 389 case 0x4a: 390 case 0x4d: 391 case 0x5a: 392 case 0x5d: 393 case 0x4c: // really airmont 394 return "silvermont"; 395 396 case 0x57: 397 return "knl"; 398 399 default: // Unknown family 6 CPU, try to guess. 400 if (HasAVX512) 401 return "knl"; 402 if (HasADX) 403 return "broadwell"; 404 if (HasAVX2) 405 return "haswell"; 406 if (HasAVX) 407 return "sandybridge"; 408 if (HasSSE42) 409 return HasMOVBE ? "silvermont" : "nehalem"; 410 if (HasSSE41) 411 return "penryn"; 412 if (HasSSSE3) 413 return HasMOVBE ? "bonnell" : "core2"; 414 if (Em64T) 415 return "x86-64"; 416 if (HasSSE2) 417 return "pentium-m"; 418 if (HasSSE) 419 return "pentium3"; 420 if (HasMMX) 421 return "pentium2"; 422 return "pentiumpro"; 423 } 424 case 15: { 425 switch (Model) { 426 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are 427 // model 00h and manufactured using the 0.18 micron process. 428 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon 429 // processor MP, and Intel Celeron processor. All processors are 430 // model 01h and manufactured using the 0.18 micron process. 431 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M, 432 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron 433 // processor, and Mobile Intel Celeron processor. All processors 434 // are model 02h and manufactured using the 0.13 micron process. 435 return (Em64T) ? "x86-64" : "pentium4"; 436 437 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D 438 // processor. All processors are model 03h and manufactured using 439 // the 90 nm process. 440 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition, 441 // Pentium D processor, Intel Xeon processor, Intel Xeon 442 // processor MP, Intel Celeron D processor. All processors are 443 // model 04h and manufactured using the 90 nm process. 444 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor 445 // Extreme Edition, Intel Xeon processor, Intel Xeon processor 446 // MP, Intel Celeron D processor. All processors are model 06h 447 // and manufactured using the 65 nm process. 448 return (Em64T) ? "nocona" : "prescott"; 449 450 default: 451 return (Em64T) ? "x86-64" : "pentium4"; 452 } 453 } 454 455 default: 456 return "generic"; 457 } 458 } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) { 459 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 460 // appears to be no way to generate the wide variety of AMD-specific targets 461 // from the information returned from CPUID. 462 switch (Family) { 463 case 4: 464 return "i486"; 465 case 5: 466 switch (Model) { 467 case 6: 468 case 7: return "k6"; 469 case 8: return "k6-2"; 470 case 9: 471 case 13: return "k6-3"; 472 case 10: return "geode"; 473 default: return "pentium"; 474 } 475 case 6: 476 switch (Model) { 477 case 4: return "athlon-tbird"; 478 case 6: 479 case 7: 480 case 8: return "athlon-mp"; 481 case 10: return "athlon-xp"; 482 default: return "athlon"; 483 } 484 case 15: 485 if (HasSSE3) 486 return "k8-sse3"; 487 switch (Model) { 488 case 1: return "opteron"; 489 case 5: return "athlon-fx"; // also opteron 490 default: return "athlon64"; 491 } 492 case 16: 493 return "amdfam10"; 494 case 20: 495 return "btver1"; 496 case 21: 497 if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback. 498 return "btver1"; 499 if (Model >= 0x50) 500 return "bdver4"; // 50h-6Fh: Excavator 501 if (Model >= 0x30) 502 return "bdver3"; // 30h-3Fh: Steamroller 503 if (Model >= 0x10 || HasTBM) 504 return "bdver2"; // 10h-1Fh: Piledriver 505 return "bdver1"; // 00h-0Fh: Bulldozer 506 case 22: 507 if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback. 508 return "btver1"; 509 return "btver2"; 510 default: 511 return "generic"; 512 } 513 } 514 return "generic"; 515 } 516 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 517 StringRef sys::getHostCPUName() { 518 host_basic_info_data_t hostInfo; 519 mach_msg_type_number_t infoCount; 520 521 infoCount = HOST_BASIC_INFO_COUNT; 522 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo, 523 &infoCount); 524 525 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) return "generic"; 526 527 switch(hostInfo.cpu_subtype) { 528 case CPU_SUBTYPE_POWERPC_601: return "601"; 529 case CPU_SUBTYPE_POWERPC_602: return "602"; 530 case CPU_SUBTYPE_POWERPC_603: return "603"; 531 case CPU_SUBTYPE_POWERPC_603e: return "603e"; 532 case CPU_SUBTYPE_POWERPC_603ev: return "603ev"; 533 case CPU_SUBTYPE_POWERPC_604: return "604"; 534 case CPU_SUBTYPE_POWERPC_604e: return "604e"; 535 case CPU_SUBTYPE_POWERPC_620: return "620"; 536 case CPU_SUBTYPE_POWERPC_750: return "750"; 537 case CPU_SUBTYPE_POWERPC_7400: return "7400"; 538 case CPU_SUBTYPE_POWERPC_7450: return "7450"; 539 case CPU_SUBTYPE_POWERPC_970: return "970"; 540 default: ; 541 } 542 543 return "generic"; 544 } 545 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 546 StringRef sys::getHostCPUName() { 547 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 548 // and so we must use an operating-system interface to determine the current 549 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 550 const char *generic = "generic"; 551 552 // The cpu line is second (after the 'processor: 0' line), so if this 553 // buffer is too small then something has changed (or is wrong). 554 char buffer[1024]; 555 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer)); 556 if (CPUInfoSize == -1) 557 return generic; 558 559 const char *CPUInfoStart = buffer; 560 const char *CPUInfoEnd = buffer + CPUInfoSize; 561 562 const char *CIP = CPUInfoStart; 563 564 const char *CPUStart = 0; 565 size_t CPULen = 0; 566 567 // We need to find the first line which starts with cpu, spaces, and a colon. 568 // After the colon, there may be some additional spaces and then the cpu type. 569 while (CIP < CPUInfoEnd && CPUStart == 0) { 570 if (CIP < CPUInfoEnd && *CIP == '\n') 571 ++CIP; 572 573 if (CIP < CPUInfoEnd && *CIP == 'c') { 574 ++CIP; 575 if (CIP < CPUInfoEnd && *CIP == 'p') { 576 ++CIP; 577 if (CIP < CPUInfoEnd && *CIP == 'u') { 578 ++CIP; 579 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 580 ++CIP; 581 582 if (CIP < CPUInfoEnd && *CIP == ':') { 583 ++CIP; 584 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 585 ++CIP; 586 587 if (CIP < CPUInfoEnd) { 588 CPUStart = CIP; 589 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 590 *CIP != ',' && *CIP != '\n')) 591 ++CIP; 592 CPULen = CIP - CPUStart; 593 } 594 } 595 } 596 } 597 } 598 599 if (CPUStart == 0) 600 while (CIP < CPUInfoEnd && *CIP != '\n') 601 ++CIP; 602 } 603 604 if (CPUStart == 0) 605 return generic; 606 607 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 608 .Case("604e", "604e") 609 .Case("604", "604") 610 .Case("7400", "7400") 611 .Case("7410", "7400") 612 .Case("7447", "7400") 613 .Case("7455", "7450") 614 .Case("G4", "g4") 615 .Case("POWER4", "970") 616 .Case("PPC970FX", "970") 617 .Case("PPC970MP", "970") 618 .Case("G5", "g5") 619 .Case("POWER5", "g5") 620 .Case("A2", "a2") 621 .Case("POWER6", "pwr6") 622 .Case("POWER7", "pwr7") 623 .Case("POWER8", "pwr8") 624 .Case("POWER8E", "pwr8") 625 .Default(generic); 626 } 627 #elif defined(__linux__) && defined(__arm__) 628 StringRef sys::getHostCPUName() { 629 // The cpuid register on arm is not accessible from user space. On Linux, 630 // it is exposed through the /proc/cpuinfo file. 631 632 // Read 1024 bytes from /proc/cpuinfo, which should contain the CPU part line 633 // in all cases. 634 char buffer[1024]; 635 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer)); 636 if (CPUInfoSize == -1) 637 return "generic"; 638 639 StringRef Str(buffer, CPUInfoSize); 640 641 SmallVector<StringRef, 32> Lines; 642 Str.split(Lines, "\n"); 643 644 // Look for the CPU implementer line. 645 StringRef Implementer; 646 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 647 if (Lines[I].startswith("CPU implementer")) 648 Implementer = Lines[I].substr(15).ltrim("\t :"); 649 650 if (Implementer == "0x41") // ARM Ltd. 651 // Look for the CPU part line. 652 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 653 if (Lines[I].startswith("CPU part")) 654 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 655 // values correspond to the "Part number" in the CP15/c0 register. The 656 // contents are specified in the various processor manuals. 657 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 658 .Case("0x926", "arm926ej-s") 659 .Case("0xb02", "mpcore") 660 .Case("0xb36", "arm1136j-s") 661 .Case("0xb56", "arm1156t2-s") 662 .Case("0xb76", "arm1176jz-s") 663 .Case("0xc08", "cortex-a8") 664 .Case("0xc09", "cortex-a9") 665 .Case("0xc0f", "cortex-a15") 666 .Case("0xc20", "cortex-m0") 667 .Case("0xc23", "cortex-m3") 668 .Case("0xc24", "cortex-m4") 669 .Default("generic"); 670 671 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 672 // Look for the CPU part line. 673 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 674 if (Lines[I].startswith("CPU part")) 675 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 676 // values correspond to the "Part number" in the CP15/c0 register. The 677 // contents are specified in the various processor manuals. 678 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 679 .Case("0x06f", "krait") // APQ8064 680 .Default("generic"); 681 682 return "generic"; 683 } 684 #elif defined(__linux__) && defined(__s390x__) 685 StringRef sys::getHostCPUName() { 686 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 687 688 // The "processor 0:" line comes after a fair amount of other information, 689 // including a cache breakdown, but this should be plenty. 690 char buffer[2048]; 691 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer)); 692 if (CPUInfoSize == -1) 693 return "generic"; 694 695 StringRef Str(buffer, CPUInfoSize); 696 SmallVector<StringRef, 32> Lines; 697 Str.split(Lines, "\n"); 698 699 // Look for the CPU features. 700 SmallVector<StringRef, 32> CPUFeatures; 701 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 702 if (Lines[I].startswith("features")) { 703 size_t Pos = Lines[I].find(":"); 704 if (Pos != StringRef::npos) { 705 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 706 break; 707 } 708 } 709 710 // We need to check for the presence of vector support independently of 711 // the machine type, since we may only use the vector register set when 712 // supported by the kernel (and hypervisor). 713 bool HaveVectorSupport = false; 714 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 715 if (CPUFeatures[I] == "vx") 716 HaveVectorSupport = true; 717 } 718 719 // Now check the processor machine type. 720 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 721 if (Lines[I].startswith("processor ")) { 722 size_t Pos = Lines[I].find("machine = "); 723 if (Pos != StringRef::npos) { 724 Pos += sizeof("machine = ") - 1; 725 unsigned int Id; 726 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 727 if (Id >= 2964 && HaveVectorSupport) 728 return "z13"; 729 if (Id >= 2827) 730 return "zEC12"; 731 if (Id >= 2817) 732 return "z196"; 733 } 734 } 735 break; 736 } 737 } 738 739 return "generic"; 740 } 741 #else 742 StringRef sys::getHostCPUName() { 743 return "generic"; 744 } 745 #endif 746 747 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\ 748 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) 749 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 750 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 751 unsigned MaxLevel; 752 union { 753 unsigned u[3]; 754 char c[12]; 755 } text; 756 757 if (GetX86CpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) || 758 MaxLevel < 1) 759 return false; 760 761 GetX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 762 763 Features["cmov"] = (EDX >> 15) & 1; 764 Features["mmx"] = (EDX >> 23) & 1; 765 Features["sse"] = (EDX >> 25) & 1; 766 Features["sse2"] = (EDX >> 26) & 1; 767 Features["sse3"] = (ECX >> 0) & 1; 768 Features["ssse3"] = (ECX >> 9) & 1; 769 Features["sse4.1"] = (ECX >> 19) & 1; 770 Features["sse4.2"] = (ECX >> 20) & 1; 771 772 Features["pclmul"] = (ECX >> 1) & 1; 773 Features["cx16"] = (ECX >> 13) & 1; 774 Features["movbe"] = (ECX >> 22) & 1; 775 Features["popcnt"] = (ECX >> 23) & 1; 776 Features["aes"] = (ECX >> 25) & 1; 777 Features["rdrnd"] = (ECX >> 30) & 1; 778 779 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 780 // indicates that the AVX registers will be saved and restored on context 781 // switch, then we have full AVX support. 782 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 783 !GetX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 784 Features["avx"] = HasAVXSave; 785 Features["fma"] = HasAVXSave && (ECX >> 12) & 1; 786 Features["f16c"] = HasAVXSave && (ECX >> 29) & 1; 787 788 // Only enable XSAVE if OS has enabled support for saving YMM state. 789 Features["xsave"] = HasAVXSave && (ECX >> 26) & 1; 790 791 // AVX512 requires additional context to be saved by the OS. 792 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 793 794 unsigned MaxExtLevel; 795 GetX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 796 797 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 798 !GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 799 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 800 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 801 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 802 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 803 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 804 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 805 806 bool HasLeaf7 = MaxLevel >= 7 && 807 !GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 808 809 // AVX2 is only supported if we have the OS save support from AVX. 810 Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1); 811 812 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 813 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 814 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 815 Features["hle"] = HasLeaf7 && ((EBX >> 4) & 1); 816 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 817 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 818 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 819 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 820 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 821 Features["smap"] = HasLeaf7 && ((EBX >> 20) & 1); 822 Features["pcommit"] = HasLeaf7 && ((EBX >> 22) & 1); 823 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 824 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 825 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 826 827 // AVX512 is only supported if the OS supports the context save for it. 828 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 829 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 830 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 831 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 832 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 833 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 834 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 835 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 836 837 Features["prefetchwt1"] = HasLeaf7 && (ECX & 1); 838 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 839 // Enable protection keys 840 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 841 842 bool HasLeafD = MaxLevel >= 0xd && 843 !GetX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 844 845 // Only enable XSAVE if OS has enabled support for saving YMM state. 846 Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1); 847 Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1); 848 Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1); 849 850 return true; 851 } 852 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 853 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 854 // Read 1024 bytes from /proc/cpuinfo, which should contain the Features line 855 // in all cases. 856 char buffer[1024]; 857 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer)); 858 if (CPUInfoSize == -1) 859 return false; 860 861 StringRef Str(buffer, CPUInfoSize); 862 863 SmallVector<StringRef, 32> Lines; 864 Str.split(Lines, "\n"); 865 866 SmallVector<StringRef, 32> CPUFeatures; 867 868 // Look for the CPU features. 869 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 870 if (Lines[I].startswith("Features")) { 871 Lines[I].split(CPUFeatures, ' '); 872 break; 873 } 874 875 #if defined(__aarch64__) 876 // Keep track of which crypto features we have seen 877 enum { 878 CAP_AES = 0x1, 879 CAP_PMULL = 0x2, 880 CAP_SHA1 = 0x4, 881 CAP_SHA2 = 0x8 882 }; 883 uint32_t crypto = 0; 884 #endif 885 886 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 887 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 888 #if defined(__aarch64__) 889 .Case("asimd", "neon") 890 .Case("fp", "fp-armv8") 891 .Case("crc32", "crc") 892 #else 893 .Case("half", "fp16") 894 .Case("neon", "neon") 895 .Case("vfpv3", "vfp3") 896 .Case("vfpv3d16", "d16") 897 .Case("vfpv4", "vfp4") 898 .Case("idiva", "hwdiv-arm") 899 .Case("idivt", "hwdiv") 900 #endif 901 .Default(""); 902 903 #if defined(__aarch64__) 904 // We need to check crypto separately since we need all of the crypto 905 // extensions to enable the subtarget feature 906 if (CPUFeatures[I] == "aes") 907 crypto |= CAP_AES; 908 else if (CPUFeatures[I] == "pmull") 909 crypto |= CAP_PMULL; 910 else if (CPUFeatures[I] == "sha1") 911 crypto |= CAP_SHA1; 912 else if (CPUFeatures[I] == "sha2") 913 crypto |= CAP_SHA2; 914 #endif 915 916 if (LLVMFeatureStr != "") 917 Features[LLVMFeatureStr] = true; 918 } 919 920 #if defined(__aarch64__) 921 // If we have all crypto bits we can add the feature 922 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 923 Features["crypto"] = true; 924 #endif 925 926 return true; 927 } 928 #else 929 bool sys::getHostCPUFeatures(StringMap<bool> &Features){ 930 return false; 931 } 932 #endif 933 934 std::string sys::getProcessTriple() { 935 Triple PT(Triple::normalize(LLVM_HOST_TRIPLE)); 936 937 if (sizeof(void *) == 8 && PT.isArch32Bit()) 938 PT = PT.get64BitArchVariant(); 939 if (sizeof(void *) == 4 && PT.isArch64Bit()) 940 PT = PT.get32BitArchVariant(); 941 942 return PT.str(); 943 } 944