1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the operating system Host concept. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/Host.h" 14 #include "llvm/ADT/SmallSet.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringMap.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/llvm-config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/TargetParser.h" 25 #include "llvm/Support/raw_ostream.h" 26 #include <assert.h> 27 #include <string.h> 28 29 // Include the platform-specific parts of this class. 30 #ifdef LLVM_ON_UNIX 31 #include "Unix/Host.inc" 32 #include <sched.h> 33 #endif 34 #ifdef _WIN32 35 #include "Windows/Host.inc" 36 #endif 37 #ifdef _MSC_VER 38 #include <intrin.h> 39 #endif 40 #if defined(__APPLE__) && (!defined(__x86_64__)) 41 #include <mach/host_info.h> 42 #include <mach/mach.h> 43 #include <mach/mach_host.h> 44 #include <mach/machine.h> 45 #endif 46 47 #define DEBUG_TYPE "host-detection" 48 49 //===----------------------------------------------------------------------===// 50 // 51 // Implementations of the CPU detection routines 52 // 53 //===----------------------------------------------------------------------===// 54 55 using namespace llvm; 56 57 static std::unique_ptr<llvm::MemoryBuffer> 58 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 59 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 60 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 61 if (std::error_code EC = Text.getError()) { 62 llvm::errs() << "Can't read " 63 << "/proc/cpuinfo: " << EC.message() << "\n"; 64 return nullptr; 65 } 66 return std::move(*Text); 67 } 68 69 StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) { 70 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 71 // and so we must use an operating-system interface to determine the current 72 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 73 const char *generic = "generic"; 74 75 // The cpu line is second (after the 'processor: 0' line), so if this 76 // buffer is too small then something has changed (or is wrong). 77 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 78 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 79 80 StringRef::const_iterator CIP = CPUInfoStart; 81 82 StringRef::const_iterator CPUStart = 0; 83 size_t CPULen = 0; 84 85 // We need to find the first line which starts with cpu, spaces, and a colon. 86 // After the colon, there may be some additional spaces and then the cpu type. 87 while (CIP < CPUInfoEnd && CPUStart == 0) { 88 if (CIP < CPUInfoEnd && *CIP == '\n') 89 ++CIP; 90 91 if (CIP < CPUInfoEnd && *CIP == 'c') { 92 ++CIP; 93 if (CIP < CPUInfoEnd && *CIP == 'p') { 94 ++CIP; 95 if (CIP < CPUInfoEnd && *CIP == 'u') { 96 ++CIP; 97 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 98 ++CIP; 99 100 if (CIP < CPUInfoEnd && *CIP == ':') { 101 ++CIP; 102 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 103 ++CIP; 104 105 if (CIP < CPUInfoEnd) { 106 CPUStart = CIP; 107 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 108 *CIP != ',' && *CIP != '\n')) 109 ++CIP; 110 CPULen = CIP - CPUStart; 111 } 112 } 113 } 114 } 115 } 116 117 if (CPUStart == 0) 118 while (CIP < CPUInfoEnd && *CIP != '\n') 119 ++CIP; 120 } 121 122 if (CPUStart == 0) 123 return generic; 124 125 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 126 .Case("604e", "604e") 127 .Case("604", "604") 128 .Case("7400", "7400") 129 .Case("7410", "7400") 130 .Case("7447", "7400") 131 .Case("7455", "7450") 132 .Case("G4", "g4") 133 .Case("POWER4", "970") 134 .Case("PPC970FX", "970") 135 .Case("PPC970MP", "970") 136 .Case("G5", "g5") 137 .Case("POWER5", "g5") 138 .Case("A2", "a2") 139 .Case("POWER6", "pwr6") 140 .Case("POWER7", "pwr7") 141 .Case("POWER8", "pwr8") 142 .Case("POWER8E", "pwr8") 143 .Case("POWER8NVL", "pwr8") 144 .Case("POWER9", "pwr9") 145 // FIXME: If we get a simulator or machine with the capabilities of 146 // mcpu=future, we should revisit this and add the name reported by the 147 // simulator/machine. 148 .Default(generic); 149 } 150 151 StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { 152 // The cpuid register on arm is not accessible from user space. On Linux, 153 // it is exposed through the /proc/cpuinfo file. 154 155 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 156 // in all cases. 157 SmallVector<StringRef, 32> Lines; 158 ProcCpuinfoContent.split(Lines, "\n"); 159 160 // Look for the CPU implementer line. 161 StringRef Implementer; 162 StringRef Hardware; 163 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 164 if (Lines[I].startswith("CPU implementer")) 165 Implementer = Lines[I].substr(15).ltrim("\t :"); 166 if (Lines[I].startswith("Hardware")) 167 Hardware = Lines[I].substr(8).ltrim("\t :"); 168 } 169 170 if (Implementer == "0x41") { // ARM Ltd. 171 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 172 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 173 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 174 return "cortex-a53"; 175 176 177 // Look for the CPU part line. 178 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 179 if (Lines[I].startswith("CPU part")) 180 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 181 // values correspond to the "Part number" in the CP15/c0 register. The 182 // contents are specified in the various processor manuals. 183 // This corresponds to the Main ID Register in Technical Reference Manuals. 184 // and is used in programs like sys-utils 185 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 186 .Case("0x926", "arm926ej-s") 187 .Case("0xb02", "mpcore") 188 .Case("0xb36", "arm1136j-s") 189 .Case("0xb56", "arm1156t2-s") 190 .Case("0xb76", "arm1176jz-s") 191 .Case("0xc08", "cortex-a8") 192 .Case("0xc09", "cortex-a9") 193 .Case("0xc0f", "cortex-a15") 194 .Case("0xc20", "cortex-m0") 195 .Case("0xc23", "cortex-m3") 196 .Case("0xc24", "cortex-m4") 197 .Case("0xd22", "cortex-m55") 198 .Case("0xd02", "cortex-a34") 199 .Case("0xd04", "cortex-a35") 200 .Case("0xd03", "cortex-a53") 201 .Case("0xd07", "cortex-a57") 202 .Case("0xd08", "cortex-a72") 203 .Case("0xd09", "cortex-a73") 204 .Case("0xd0a", "cortex-a75") 205 .Case("0xd0b", "cortex-a76") 206 .Default("generic"); 207 } 208 209 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium. 210 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 211 if (Lines[I].startswith("CPU part")) { 212 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 213 .Case("0x516", "thunderx2t99") 214 .Case("0x0516", "thunderx2t99") 215 .Case("0xaf", "thunderx2t99") 216 .Case("0x0af", "thunderx2t99") 217 .Case("0xa1", "thunderxt88") 218 .Case("0x0a1", "thunderxt88") 219 .Default("generic"); 220 } 221 } 222 } 223 224 if (Implementer == "0x46") { // Fujitsu Ltd. 225 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 226 if (Lines[I].startswith("CPU part")) { 227 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 228 .Case("0x001", "a64fx") 229 .Default("generic"); 230 } 231 } 232 } 233 234 if (Implementer == "0x4e") { // NVIDIA Corporation 235 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 236 if (Lines[I].startswith("CPU part")) { 237 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 238 .Case("0x004", "carmel") 239 .Default("generic"); 240 } 241 } 242 } 243 244 if (Implementer == "0x48") // HiSilicon Technologies, Inc. 245 // Look for the CPU part line. 246 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 247 if (Lines[I].startswith("CPU part")) 248 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 249 // values correspond to the "Part number" in the CP15/c0 register. The 250 // contents are specified in the various processor manuals. 251 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 252 .Case("0xd01", "tsv110") 253 .Default("generic"); 254 255 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 256 // Look for the CPU part line. 257 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 258 if (Lines[I].startswith("CPU part")) 259 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 260 // values correspond to the "Part number" in the CP15/c0 register. The 261 // contents are specified in the various processor manuals. 262 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 263 .Case("0x06f", "krait") // APQ8064 264 .Case("0x201", "kryo") 265 .Case("0x205", "kryo") 266 .Case("0x211", "kryo") 267 .Case("0x800", "cortex-a73") 268 .Case("0x801", "cortex-a73") 269 .Case("0x802", "cortex-a73") 270 .Case("0x803", "cortex-a73") 271 .Case("0x804", "cortex-a73") 272 .Case("0x805", "cortex-a73") 273 .Case("0xc00", "falkor") 274 .Case("0xc01", "saphira") 275 .Default("generic"); 276 277 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. 278 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow 279 // any predictive pattern across variants and parts. 280 unsigned Variant = 0, Part = 0; 281 282 // Look for the CPU variant line, whose value is a 1 digit hexadecimal 283 // number, corresponding to the Variant bits in the CP15/C0 register. 284 for (auto I : Lines) 285 if (I.consume_front("CPU variant")) 286 I.ltrim("\t :").getAsInteger(0, Variant); 287 288 // Look for the CPU part line, whose value is a 3 digit hexadecimal 289 // number, corresponding to the PartNum bits in the CP15/C0 register. 290 for (auto I : Lines) 291 if (I.consume_front("CPU part")) 292 I.ltrim("\t :").getAsInteger(0, Part); 293 294 unsigned Exynos = (Variant << 12) | Part; 295 switch (Exynos) { 296 default: 297 // Default by falling through to Exynos M3. 298 LLVM_FALLTHROUGH; 299 case 0x1002: 300 return "exynos-m3"; 301 case 0x1003: 302 return "exynos-m4"; 303 } 304 } 305 306 return "generic"; 307 } 308 309 StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { 310 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 311 312 // The "processor 0:" line comes after a fair amount of other information, 313 // including a cache breakdown, but this should be plenty. 314 SmallVector<StringRef, 32> Lines; 315 ProcCpuinfoContent.split(Lines, "\n"); 316 317 // Look for the CPU features. 318 SmallVector<StringRef, 32> CPUFeatures; 319 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 320 if (Lines[I].startswith("features")) { 321 size_t Pos = Lines[I].find(":"); 322 if (Pos != StringRef::npos) { 323 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 324 break; 325 } 326 } 327 328 // We need to check for the presence of vector support independently of 329 // the machine type, since we may only use the vector register set when 330 // supported by the kernel (and hypervisor). 331 bool HaveVectorSupport = false; 332 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 333 if (CPUFeatures[I] == "vx") 334 HaveVectorSupport = true; 335 } 336 337 // Now check the processor machine type. 338 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 339 if (Lines[I].startswith("processor ")) { 340 size_t Pos = Lines[I].find("machine = "); 341 if (Pos != StringRef::npos) { 342 Pos += sizeof("machine = ") - 1; 343 unsigned int Id; 344 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 345 if (Id >= 8561 && HaveVectorSupport) 346 return "z15"; 347 if (Id >= 3906 && HaveVectorSupport) 348 return "z14"; 349 if (Id >= 2964 && HaveVectorSupport) 350 return "z13"; 351 if (Id >= 2827) 352 return "zEC12"; 353 if (Id >= 2817) 354 return "z196"; 355 } 356 } 357 break; 358 } 359 } 360 361 return "generic"; 362 } 363 364 StringRef sys::detail::getHostCPUNameForBPF() { 365 #if !defined(__linux__) || !defined(__x86_64__) 366 return "generic"; 367 #else 368 uint8_t v3_insns[40] __attribute__ ((aligned (8))) = 369 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 370 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 371 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 372 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 373 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 374 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 375 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 376 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 377 /* BPF_EXIT_INSN() */ 378 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 379 380 uint8_t v2_insns[40] __attribute__ ((aligned (8))) = 381 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 382 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 383 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 384 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 385 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 386 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 387 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 388 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 389 /* BPF_EXIT_INSN() */ 390 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 391 392 struct bpf_prog_load_attr { 393 uint32_t prog_type; 394 uint32_t insn_cnt; 395 uint64_t insns; 396 uint64_t license; 397 uint32_t log_level; 398 uint32_t log_size; 399 uint64_t log_buf; 400 uint32_t kern_version; 401 uint32_t prog_flags; 402 } attr = {}; 403 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 404 attr.insn_cnt = 5; 405 attr.insns = (uint64_t)v3_insns; 406 attr.license = (uint64_t)"DUMMY"; 407 408 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, 409 sizeof(attr)); 410 if (fd >= 0) { 411 close(fd); 412 return "v3"; 413 } 414 415 /* Clear the whole attr in case its content changed by syscall. */ 416 memset(&attr, 0, sizeof(attr)); 417 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 418 attr.insn_cnt = 5; 419 attr.insns = (uint64_t)v2_insns; 420 attr.license = (uint64_t)"DUMMY"; 421 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 422 if (fd >= 0) { 423 close(fd); 424 return "v2"; 425 } 426 return "v1"; 427 #endif 428 } 429 430 #if defined(__i386__) || defined(_M_IX86) || \ 431 defined(__x86_64__) || defined(_M_X64) 432 433 enum VendorSignatures { 434 SIG_INTEL = 0x756e6547 /* Genu */, 435 SIG_AMD = 0x68747541 /* Auth */ 436 }; 437 438 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 439 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 440 // support. Consequently, for i386, the presence of CPUID is checked first 441 // via the corresponding eflags bit. 442 // Removal of cpuid.h header motivated by PR30384 443 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 444 // or test-suite, but are used in external projects e.g. libstdcxx 445 static bool isCpuIdSupported() { 446 #if defined(__GNUC__) || defined(__clang__) 447 #if defined(__i386__) 448 int __cpuid_supported; 449 __asm__(" pushfl\n" 450 " popl %%eax\n" 451 " movl %%eax,%%ecx\n" 452 " xorl $0x00200000,%%eax\n" 453 " pushl %%eax\n" 454 " popfl\n" 455 " pushfl\n" 456 " popl %%eax\n" 457 " movl $0,%0\n" 458 " cmpl %%eax,%%ecx\n" 459 " je 1f\n" 460 " movl $1,%0\n" 461 "1:" 462 : "=r"(__cpuid_supported) 463 : 464 : "eax", "ecx"); 465 if (!__cpuid_supported) 466 return false; 467 #endif 468 return true; 469 #endif 470 return true; 471 } 472 473 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 474 /// the specified arguments. If we can't run cpuid on the host, return true. 475 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 476 unsigned *rECX, unsigned *rEDX) { 477 #if defined(__GNUC__) || defined(__clang__) 478 #if defined(__x86_64__) 479 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 480 // FIXME: should we save this for Clang? 481 __asm__("movq\t%%rbx, %%rsi\n\t" 482 "cpuid\n\t" 483 "xchgq\t%%rbx, %%rsi\n\t" 484 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 485 : "a"(value)); 486 return false; 487 #elif defined(__i386__) 488 __asm__("movl\t%%ebx, %%esi\n\t" 489 "cpuid\n\t" 490 "xchgl\t%%ebx, %%esi\n\t" 491 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 492 : "a"(value)); 493 return false; 494 #else 495 return true; 496 #endif 497 #elif defined(_MSC_VER) 498 // The MSVC intrinsic is portable across x86 and x64. 499 int registers[4]; 500 __cpuid(registers, value); 501 *rEAX = registers[0]; 502 *rEBX = registers[1]; 503 *rECX = registers[2]; 504 *rEDX = registers[3]; 505 return false; 506 #else 507 return true; 508 #endif 509 } 510 511 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 512 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 513 /// return true. 514 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 515 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 516 unsigned *rEDX) { 517 #if defined(__GNUC__) || defined(__clang__) 518 #if defined(__x86_64__) 519 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 520 // FIXME: should we save this for Clang? 521 __asm__("movq\t%%rbx, %%rsi\n\t" 522 "cpuid\n\t" 523 "xchgq\t%%rbx, %%rsi\n\t" 524 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 525 : "a"(value), "c"(subleaf)); 526 return false; 527 #elif defined(__i386__) 528 __asm__("movl\t%%ebx, %%esi\n\t" 529 "cpuid\n\t" 530 "xchgl\t%%ebx, %%esi\n\t" 531 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 532 : "a"(value), "c"(subleaf)); 533 return false; 534 #else 535 return true; 536 #endif 537 #elif defined(_MSC_VER) 538 int registers[4]; 539 __cpuidex(registers, value, subleaf); 540 *rEAX = registers[0]; 541 *rEBX = registers[1]; 542 *rECX = registers[2]; 543 *rEDX = registers[3]; 544 return false; 545 #else 546 return true; 547 #endif 548 } 549 550 // Read control register 0 (XCR0). Used to detect features such as AVX. 551 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 552 #if defined(__GNUC__) || defined(__clang__) 553 // Check xgetbv; this uses a .byte sequence instead of the instruction 554 // directly because older assemblers do not include support for xgetbv and 555 // there is no easy way to conditionally compile based on the assembler used. 556 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 557 return false; 558 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 559 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 560 *rEAX = Result; 561 *rEDX = Result >> 32; 562 return false; 563 #else 564 return true; 565 #endif 566 } 567 568 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 569 unsigned *Model) { 570 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 571 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 572 if (*Family == 6 || *Family == 0xf) { 573 if (*Family == 0xf) 574 // Examine extended family ID if family ID is F. 575 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 576 // Examine extended model ID if family ID is 6 or F. 577 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 578 } 579 } 580 581 static void 582 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 583 unsigned Brand_id, unsigned Features, 584 unsigned Features2, unsigned Features3, 585 unsigned *Type, unsigned *Subtype) { 586 if (Brand_id != 0) 587 return; 588 switch (Family) { 589 case 3: 590 *Type = X86::INTEL_i386; 591 break; 592 case 4: 593 *Type = X86::INTEL_i486; 594 break; 595 case 5: 596 if (Features & (1 << X86::FEATURE_MMX)) { 597 *Type = X86::INTEL_PENTIUM_MMX; 598 break; 599 } 600 *Type = X86::INTEL_PENTIUM; 601 break; 602 case 6: 603 switch (Model) { 604 case 0x01: // Pentium Pro processor 605 *Type = X86::INTEL_PENTIUM_PRO; 606 break; 607 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 608 // model 03 609 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 610 // model 05, and Intel Celeron processor, model 05 611 case 0x06: // Celeron processor, model 06 612 *Type = X86::INTEL_PENTIUM_II; 613 break; 614 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 615 // processor, model 07 616 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 617 // model 08, and Celeron processor, model 08 618 case 0x0a: // Pentium III Xeon processor, model 0Ah 619 case 0x0b: // Pentium III processor, model 0Bh 620 *Type = X86::INTEL_PENTIUM_III; 621 break; 622 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 623 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 624 // 0Dh. All processors are manufactured using the 90 nm process. 625 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 626 // Integrated Processor with Intel QuickAssist Technology 627 *Type = X86::INTEL_PENTIUM_M; 628 break; 629 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 630 // 0Eh. All processors are manufactured using the 65 nm process. 631 *Type = X86::INTEL_CORE_DUO; 632 break; // yonah 633 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 634 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 635 // mobile processor, Intel Core 2 Extreme processor, Intel 636 // Pentium Dual-Core processor, Intel Xeon processor, model 637 // 0Fh. All processors are manufactured using the 65 nm process. 638 case 0x16: // Intel Celeron processor model 16h. All processors are 639 // manufactured using the 65 nm process 640 *Type = X86::INTEL_CORE2; // "core2" 641 *Subtype = X86::INTEL_CORE2_65; 642 break; 643 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 644 // 17h. All processors are manufactured using the 45 nm process. 645 // 646 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 647 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 648 // the 45 nm process. 649 *Type = X86::INTEL_CORE2; // "penryn" 650 *Subtype = X86::INTEL_CORE2_45; 651 break; 652 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 653 // processors are manufactured using the 45 nm process. 654 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 655 // As found in a Summer 2010 model iMac. 656 case 0x1f: 657 case 0x2e: // Nehalem EX 658 *Type = X86::INTEL_COREI7; // "nehalem" 659 *Subtype = X86::INTEL_COREI7_NEHALEM; 660 break; 661 case 0x25: // Intel Core i7, laptop version. 662 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 663 // processors are manufactured using the 32 nm process. 664 case 0x2f: // Westmere EX 665 *Type = X86::INTEL_COREI7; // "westmere" 666 *Subtype = X86::INTEL_COREI7_WESTMERE; 667 break; 668 case 0x2a: // Intel Core i7 processor. All processors are manufactured 669 // using the 32 nm process. 670 case 0x2d: 671 *Type = X86::INTEL_COREI7; //"sandybridge" 672 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 673 break; 674 case 0x3a: 675 case 0x3e: // Ivy Bridge EP 676 *Type = X86::INTEL_COREI7; // "ivybridge" 677 *Subtype = X86::INTEL_COREI7_IVYBRIDGE; 678 break; 679 680 // Haswell: 681 case 0x3c: 682 case 0x3f: 683 case 0x45: 684 case 0x46: 685 *Type = X86::INTEL_COREI7; // "haswell" 686 *Subtype = X86::INTEL_COREI7_HASWELL; 687 break; 688 689 // Broadwell: 690 case 0x3d: 691 case 0x47: 692 case 0x4f: 693 case 0x56: 694 *Type = X86::INTEL_COREI7; // "broadwell" 695 *Subtype = X86::INTEL_COREI7_BROADWELL; 696 break; 697 698 // Skylake: 699 case 0x4e: // Skylake mobile 700 case 0x5e: // Skylake desktop 701 case 0x8e: // Kaby Lake mobile 702 case 0x9e: // Kaby Lake desktop 703 case 0xa5: // Comet Lake-H/S 704 case 0xa6: // Comet Lake-U 705 *Type = X86::INTEL_COREI7; // "skylake" 706 *Subtype = X86::INTEL_COREI7_SKYLAKE; 707 break; 708 709 // Skylake Xeon: 710 case 0x55: 711 *Type = X86::INTEL_COREI7; 712 if (Features2 & (1 << (X86::FEATURE_AVX512BF16 - 32))) 713 *Subtype = X86::INTEL_COREI7_COOPERLAKE; // "cooperlake" 714 else if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) 715 *Subtype = X86::INTEL_COREI7_CASCADELAKE; // "cascadelake" 716 else 717 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 718 break; 719 720 // Cannonlake: 721 case 0x66: 722 *Type = X86::INTEL_COREI7; 723 *Subtype = X86::INTEL_COREI7_CANNONLAKE; // "cannonlake" 724 break; 725 726 // Icelake: 727 case 0x7d: 728 case 0x7e: 729 *Type = X86::INTEL_COREI7; 730 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; // "icelake-client" 731 break; 732 733 // Icelake Xeon: 734 case 0x6a: 735 case 0x6c: 736 *Type = X86::INTEL_COREI7; 737 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; // "icelake-server" 738 break; 739 740 case 0x1c: // Most 45 nm Intel Atom processors 741 case 0x26: // 45 nm Atom Lincroft 742 case 0x27: // 32 nm Atom Medfield 743 case 0x35: // 32 nm Atom Midview 744 case 0x36: // 32 nm Atom Midview 745 *Type = X86::INTEL_BONNELL; 746 break; // "bonnell" 747 748 // Atom Silvermont codes from the Intel software optimization guide. 749 case 0x37: 750 case 0x4a: 751 case 0x4d: 752 case 0x5a: 753 case 0x5d: 754 case 0x4c: // really airmont 755 *Type = X86::INTEL_SILVERMONT; 756 break; // "silvermont" 757 // Goldmont: 758 case 0x5c: // Apollo Lake 759 case 0x5f: // Denverton 760 *Type = X86::INTEL_GOLDMONT; 761 break; // "goldmont" 762 case 0x7a: 763 *Type = X86::INTEL_GOLDMONT_PLUS; 764 break; 765 case 0x86: 766 *Type = X86::INTEL_TREMONT; 767 break; 768 769 case 0x57: 770 *Type = X86::INTEL_KNL; // knl 771 break; 772 773 case 0x85: 774 *Type = X86::INTEL_KNM; // knm 775 break; 776 777 default: // Unknown family 6 CPU, try to guess. 778 // TODO detect tigerlake host 779 if (Features2 & (1 << (X86::FEATURE_AVX512VP2INTERSECT - 32))) { 780 *Type = X86::INTEL_COREI7; 781 *Subtype = X86::INTEL_COREI7_TIGERLAKE; 782 break; 783 } 784 785 if (Features & (1 << X86::FEATURE_AVX512VBMI2)) { 786 *Type = X86::INTEL_COREI7; 787 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; 788 break; 789 } 790 791 if (Features & (1 << X86::FEATURE_AVX512VBMI)) { 792 *Type = X86::INTEL_COREI7; 793 *Subtype = X86::INTEL_COREI7_CANNONLAKE; 794 break; 795 } 796 797 if (Features2 & (1 << (X86::FEATURE_AVX512BF16 - 32))) { 798 *Type = X86::INTEL_COREI7; 799 *Subtype = X86::INTEL_COREI7_COOPERLAKE; 800 break; 801 } 802 803 if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) { 804 *Type = X86::INTEL_COREI7; 805 *Subtype = X86::INTEL_COREI7_CASCADELAKE; 806 break; 807 } 808 809 if (Features & (1 << X86::FEATURE_AVX512VL)) { 810 *Type = X86::INTEL_COREI7; 811 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; 812 break; 813 } 814 815 if (Features & (1 << X86::FEATURE_AVX512ER)) { 816 *Type = X86::INTEL_KNL; // knl 817 break; 818 } 819 820 if (Features3 & (1 << (X86::FEATURE_CLFLUSHOPT - 64))) { 821 if (Features3 & (1 << (X86::FEATURE_SHA - 64))) { 822 *Type = X86::INTEL_GOLDMONT; 823 } else { 824 *Type = X86::INTEL_COREI7; 825 *Subtype = X86::INTEL_COREI7_SKYLAKE; 826 } 827 break; 828 } 829 if (Features3 & (1 << (X86::FEATURE_ADX - 64))) { 830 *Type = X86::INTEL_COREI7; 831 *Subtype = X86::INTEL_COREI7_BROADWELL; 832 break; 833 } 834 if (Features & (1 << X86::FEATURE_AVX2)) { 835 *Type = X86::INTEL_COREI7; 836 *Subtype = X86::INTEL_COREI7_HASWELL; 837 break; 838 } 839 if (Features & (1 << X86::FEATURE_AVX)) { 840 *Type = X86::INTEL_COREI7; 841 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 842 break; 843 } 844 if (Features & (1 << X86::FEATURE_SSE4_2)) { 845 if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { 846 *Type = X86::INTEL_SILVERMONT; 847 } else { 848 *Type = X86::INTEL_COREI7; 849 *Subtype = X86::INTEL_COREI7_NEHALEM; 850 } 851 break; 852 } 853 if (Features & (1 << X86::FEATURE_SSE4_1)) { 854 *Type = X86::INTEL_CORE2; // "penryn" 855 *Subtype = X86::INTEL_CORE2_45; 856 break; 857 } 858 if (Features & (1 << X86::FEATURE_SSSE3)) { 859 if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { 860 *Type = X86::INTEL_BONNELL; // "bonnell" 861 } else { 862 *Type = X86::INTEL_CORE2; // "core2" 863 *Subtype = X86::INTEL_CORE2_65; 864 } 865 break; 866 } 867 if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { 868 *Type = X86::INTEL_CORE2; // "core2" 869 *Subtype = X86::INTEL_CORE2_65; 870 break; 871 } 872 if (Features & (1 << X86::FEATURE_SSE3)) { 873 *Type = X86::INTEL_CORE_DUO; 874 break; 875 } 876 if (Features & (1 << X86::FEATURE_SSE2)) { 877 *Type = X86::INTEL_PENTIUM_M; 878 break; 879 } 880 if (Features & (1 << X86::FEATURE_SSE)) { 881 *Type = X86::INTEL_PENTIUM_III; 882 break; 883 } 884 if (Features & (1 << X86::FEATURE_MMX)) { 885 *Type = X86::INTEL_PENTIUM_II; 886 break; 887 } 888 *Type = X86::INTEL_PENTIUM_PRO; 889 break; 890 } 891 break; 892 case 15: { 893 if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { 894 *Type = X86::INTEL_NOCONA; 895 break; 896 } 897 if (Features & (1 << X86::FEATURE_SSE3)) { 898 *Type = X86::INTEL_PRESCOTT; 899 break; 900 } 901 *Type = X86::INTEL_PENTIUM_IV; 902 break; 903 } 904 default: 905 break; /*"generic"*/ 906 } 907 } 908 909 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 910 unsigned Features, unsigned *Type, 911 unsigned *Subtype) { 912 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 913 // appears to be no way to generate the wide variety of AMD-specific targets 914 // from the information returned from CPUID. 915 switch (Family) { 916 case 4: 917 *Type = X86::AMD_i486; 918 break; 919 case 5: 920 *Type = X86::AMDPENTIUM; 921 switch (Model) { 922 case 6: 923 case 7: 924 *Subtype = X86::AMDPENTIUM_K6; 925 break; // "k6" 926 case 8: 927 *Subtype = X86::AMDPENTIUM_K62; 928 break; // "k6-2" 929 case 9: 930 case 13: 931 *Subtype = X86::AMDPENTIUM_K63; 932 break; // "k6-3" 933 case 10: 934 *Subtype = X86::AMDPENTIUM_GEODE; 935 break; // "geode" 936 } 937 break; 938 case 6: 939 if (Features & (1 << X86::FEATURE_SSE)) { 940 *Type = X86::AMD_ATHLON_XP; 941 break; // "athlon-xp" 942 } 943 *Type = X86::AMD_ATHLON; 944 break; // "athlon" 945 case 15: 946 if (Features & (1 << X86::FEATURE_SSE3)) { 947 *Type = X86::AMD_K8SSE3; 948 break; // "k8-sse3" 949 } 950 *Type = X86::AMD_K8; 951 break; // "k8" 952 case 16: 953 *Type = X86::AMDFAM10H; // "amdfam10" 954 switch (Model) { 955 case 2: 956 *Subtype = X86::AMDFAM10H_BARCELONA; 957 break; 958 case 4: 959 *Subtype = X86::AMDFAM10H_SHANGHAI; 960 break; 961 case 8: 962 *Subtype = X86::AMDFAM10H_ISTANBUL; 963 break; 964 } 965 break; 966 case 20: 967 *Type = X86::AMD_BTVER1; 968 break; // "btver1"; 969 case 21: 970 *Type = X86::AMDFAM15H; 971 if (Model >= 0x60 && Model <= 0x7f) { 972 *Subtype = X86::AMDFAM15H_BDVER4; 973 break; // "bdver4"; 60h-7Fh: Excavator 974 } 975 if (Model >= 0x30 && Model <= 0x3f) { 976 *Subtype = X86::AMDFAM15H_BDVER3; 977 break; // "bdver3"; 30h-3Fh: Steamroller 978 } 979 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) { 980 *Subtype = X86::AMDFAM15H_BDVER2; 981 break; // "bdver2"; 02h, 10h-1Fh: Piledriver 982 } 983 if (Model <= 0x0f) { 984 *Subtype = X86::AMDFAM15H_BDVER1; 985 break; // "bdver1"; 00h-0Fh: Bulldozer 986 } 987 break; 988 case 22: 989 *Type = X86::AMD_BTVER2; 990 break; // "btver2" 991 case 23: 992 *Type = X86::AMDFAM17H; 993 if ((Model >= 0x30 && Model <= 0x3f) || Model == 0x71) { 994 *Subtype = X86::AMDFAM17H_ZNVER2; 995 break; // "znver2"; 30h-3fh, 71h: Zen2 996 } 997 if (Model <= 0x0f) { 998 *Subtype = X86::AMDFAM17H_ZNVER1; 999 break; // "znver1"; 00h-0Fh: Zen1 1000 } 1001 break; 1002 default: 1003 break; // "generic" 1004 } 1005 } 1006 1007 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 1008 unsigned *FeaturesOut, unsigned *Features2Out, 1009 unsigned *Features3Out) { 1010 unsigned Features = 0; 1011 unsigned Features2 = 0; 1012 unsigned Features3 = 0; 1013 unsigned EAX, EBX; 1014 1015 auto setFeature = [&](unsigned F) { 1016 if (F < 32) 1017 Features |= 1U << (F & 0x1f); 1018 else if (F < 64) 1019 Features2 |= 1U << ((F - 32) & 0x1f); 1020 else if (F < 96) 1021 Features3 |= 1U << ((F - 64) & 0x1f); 1022 else 1023 llvm_unreachable("Unexpected FeatureBit"); 1024 }; 1025 1026 if ((EDX >> 15) & 1) 1027 setFeature(X86::FEATURE_CMOV); 1028 if ((EDX >> 23) & 1) 1029 setFeature(X86::FEATURE_MMX); 1030 if ((EDX >> 25) & 1) 1031 setFeature(X86::FEATURE_SSE); 1032 if ((EDX >> 26) & 1) 1033 setFeature(X86::FEATURE_SSE2); 1034 1035 if ((ECX >> 0) & 1) 1036 setFeature(X86::FEATURE_SSE3); 1037 if ((ECX >> 1) & 1) 1038 setFeature(X86::FEATURE_PCLMUL); 1039 if ((ECX >> 9) & 1) 1040 setFeature(X86::FEATURE_SSSE3); 1041 if ((ECX >> 12) & 1) 1042 setFeature(X86::FEATURE_FMA); 1043 if ((ECX >> 19) & 1) 1044 setFeature(X86::FEATURE_SSE4_1); 1045 if ((ECX >> 20) & 1) 1046 setFeature(X86::FEATURE_SSE4_2); 1047 if ((ECX >> 23) & 1) 1048 setFeature(X86::FEATURE_POPCNT); 1049 if ((ECX >> 25) & 1) 1050 setFeature(X86::FEATURE_AES); 1051 1052 if ((ECX >> 22) & 1) 1053 setFeature(X86::FEATURE_MOVBE); 1054 1055 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1056 // indicates that the AVX registers will be saved and restored on context 1057 // switch, then we have full AVX support. 1058 const unsigned AVXBits = (1 << 27) | (1 << 28); 1059 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 1060 ((EAX & 0x6) == 0x6); 1061 #if defined(__APPLE__) 1062 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1063 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1064 // set right now. 1065 bool HasAVX512Save = true; 1066 #else 1067 // AVX512 requires additional context to be saved by the OS. 1068 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 1069 #endif 1070 1071 if (HasAVX) 1072 setFeature(X86::FEATURE_AVX); 1073 1074 bool HasLeaf7 = 1075 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1076 1077 if (HasLeaf7 && ((EBX >> 3) & 1)) 1078 setFeature(X86::FEATURE_BMI); 1079 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 1080 setFeature(X86::FEATURE_AVX2); 1081 if (HasLeaf7 && ((EBX >> 8) & 1)) 1082 setFeature(X86::FEATURE_BMI2); 1083 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 1084 setFeature(X86::FEATURE_AVX512F); 1085 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 1086 setFeature(X86::FEATURE_AVX512DQ); 1087 if (HasLeaf7 && ((EBX >> 19) & 1)) 1088 setFeature(X86::FEATURE_ADX); 1089 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 1090 setFeature(X86::FEATURE_AVX512IFMA); 1091 if (HasLeaf7 && ((EBX >> 23) & 1)) 1092 setFeature(X86::FEATURE_CLFLUSHOPT); 1093 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 1094 setFeature(X86::FEATURE_AVX512PF); 1095 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 1096 setFeature(X86::FEATURE_AVX512ER); 1097 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 1098 setFeature(X86::FEATURE_AVX512CD); 1099 if (HasLeaf7 && ((EBX >> 29) & 1)) 1100 setFeature(X86::FEATURE_SHA); 1101 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 1102 setFeature(X86::FEATURE_AVX512BW); 1103 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 1104 setFeature(X86::FEATURE_AVX512VL); 1105 1106 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 1107 setFeature(X86::FEATURE_AVX512VBMI); 1108 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save) 1109 setFeature(X86::FEATURE_AVX512VBMI2); 1110 if (HasLeaf7 && ((ECX >> 8) & 1)) 1111 setFeature(X86::FEATURE_GFNI); 1112 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX) 1113 setFeature(X86::FEATURE_VPCLMULQDQ); 1114 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save) 1115 setFeature(X86::FEATURE_AVX512VNNI); 1116 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save) 1117 setFeature(X86::FEATURE_AVX512BITALG); 1118 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1119 setFeature(X86::FEATURE_AVX512VPOPCNTDQ); 1120 1121 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1122 setFeature(X86::FEATURE_AVX5124VNNIW); 1123 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1124 setFeature(X86::FEATURE_AVX5124FMAPS); 1125 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save) 1126 setFeature(X86::FEATURE_AVX512VP2INTERSECT); 1127 1128 bool HasLeaf7Subleaf1 = 1129 MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1130 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save) 1131 setFeature(X86::FEATURE_AVX512BF16); 1132 1133 unsigned MaxExtLevel; 1134 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1135 1136 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1137 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1138 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1139 setFeature(X86::FEATURE_SSE4_A); 1140 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1141 setFeature(X86::FEATURE_XOP); 1142 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1143 setFeature(X86::FEATURE_FMA4); 1144 1145 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1146 setFeature(X86::FEATURE_EM64T); 1147 1148 *FeaturesOut = Features; 1149 *Features2Out = Features2; 1150 *Features3Out = Features3; 1151 } 1152 1153 StringRef sys::getHostCPUName() { 1154 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1155 unsigned MaxLeaf, Vendor; 1156 1157 #if defined(__GNUC__) || defined(__clang__) 1158 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here 1159 // and simplify it to not invoke __cpuid (like cpu_model.c in 1160 // compiler-rt/lib/builtins/cpu_model.c? 1161 // Opting for the second option. 1162 if(!isCpuIdSupported()) 1163 return "generic"; 1164 #endif 1165 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) 1166 return "generic"; 1167 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1168 1169 unsigned Brand_id = EBX & 0xff; 1170 unsigned Family = 0, Model = 0; 1171 unsigned Features = 0, Features2 = 0, Features3 = 0; 1172 detectX86FamilyModel(EAX, &Family, &Model); 1173 getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2, &Features3); 1174 1175 unsigned Type = 0; 1176 unsigned Subtype = 0; 1177 1178 if (Vendor == SIG_INTEL) { 1179 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, 1180 Features2, Features3, &Type, &Subtype); 1181 } else if (Vendor == SIG_AMD) { 1182 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1183 } 1184 1185 // Check subtypes first since those are more specific. 1186 #define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \ 1187 if (Subtype == X86::ENUM) \ 1188 return ARCHNAME; 1189 #include "llvm/Support/X86TargetParser.def" 1190 1191 // Now check types. 1192 #define X86_CPU_TYPE(ARCHNAME, ENUM) \ 1193 if (Type == X86::ENUM) \ 1194 return ARCHNAME; 1195 #include "llvm/Support/X86TargetParser.def" 1196 1197 return "generic"; 1198 } 1199 1200 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1201 StringRef sys::getHostCPUName() { 1202 host_basic_info_data_t hostInfo; 1203 mach_msg_type_number_t infoCount; 1204 1205 infoCount = HOST_BASIC_INFO_COUNT; 1206 mach_port_t hostPort = mach_host_self(); 1207 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1208 &infoCount); 1209 mach_port_deallocate(mach_task_self(), hostPort); 1210 1211 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1212 return "generic"; 1213 1214 switch (hostInfo.cpu_subtype) { 1215 case CPU_SUBTYPE_POWERPC_601: 1216 return "601"; 1217 case CPU_SUBTYPE_POWERPC_602: 1218 return "602"; 1219 case CPU_SUBTYPE_POWERPC_603: 1220 return "603"; 1221 case CPU_SUBTYPE_POWERPC_603e: 1222 return "603e"; 1223 case CPU_SUBTYPE_POWERPC_603ev: 1224 return "603ev"; 1225 case CPU_SUBTYPE_POWERPC_604: 1226 return "604"; 1227 case CPU_SUBTYPE_POWERPC_604e: 1228 return "604e"; 1229 case CPU_SUBTYPE_POWERPC_620: 1230 return "620"; 1231 case CPU_SUBTYPE_POWERPC_750: 1232 return "750"; 1233 case CPU_SUBTYPE_POWERPC_7400: 1234 return "7400"; 1235 case CPU_SUBTYPE_POWERPC_7450: 1236 return "7450"; 1237 case CPU_SUBTYPE_POWERPC_970: 1238 return "970"; 1239 default:; 1240 } 1241 1242 return "generic"; 1243 } 1244 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1245 StringRef sys::getHostCPUName() { 1246 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1247 StringRef Content = P ? P->getBuffer() : ""; 1248 return detail::getHostCPUNameForPowerPC(Content); 1249 } 1250 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1251 StringRef sys::getHostCPUName() { 1252 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1253 StringRef Content = P ? P->getBuffer() : ""; 1254 return detail::getHostCPUNameForARM(Content); 1255 } 1256 #elif defined(__linux__) && defined(__s390x__) 1257 StringRef sys::getHostCPUName() { 1258 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1259 StringRef Content = P ? P->getBuffer() : ""; 1260 return detail::getHostCPUNameForS390x(Content); 1261 } 1262 #elif defined(__APPLE__) && defined(__aarch64__) 1263 StringRef sys::getHostCPUName() { 1264 return "cyclone"; 1265 } 1266 #elif defined(__APPLE__) && defined(__arm__) 1267 StringRef sys::getHostCPUName() { 1268 host_basic_info_data_t hostInfo; 1269 mach_msg_type_number_t infoCount; 1270 1271 infoCount = HOST_BASIC_INFO_COUNT; 1272 mach_port_t hostPort = mach_host_self(); 1273 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1274 &infoCount); 1275 mach_port_deallocate(mach_task_self(), hostPort); 1276 1277 if (hostInfo.cpu_type != CPU_TYPE_ARM) { 1278 assert(false && "CPUType not equal to ARM should not be possible on ARM"); 1279 return "generic"; 1280 } 1281 switch (hostInfo.cpu_subtype) { 1282 case CPU_SUBTYPE_ARM_V7S: 1283 return "swift"; 1284 default:; 1285 } 1286 1287 return "generic"; 1288 } 1289 #else 1290 StringRef sys::getHostCPUName() { return "generic"; } 1291 #endif 1292 1293 #if defined(__linux__) && (defined(__i386__) || defined(__x86_64__)) 1294 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1295 // using the number of unique physical/core id pairs. The following 1296 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1297 int computeHostNumPhysicalCores() { 1298 // Enabled represents the number of physical id/core id pairs with at least 1299 // one processor id enabled by the CPU affinity mask. 1300 cpu_set_t Affinity, Enabled; 1301 if (sched_getaffinity(0, sizeof(Affinity), &Affinity) != 0) 1302 return -1; 1303 CPU_ZERO(&Enabled); 1304 1305 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1306 // mmapped because it appears to have 0 size. 1307 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1308 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1309 if (std::error_code EC = Text.getError()) { 1310 llvm::errs() << "Can't read " 1311 << "/proc/cpuinfo: " << EC.message() << "\n"; 1312 return -1; 1313 } 1314 SmallVector<StringRef, 8> strs; 1315 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1316 /*KeepEmpty=*/false); 1317 int CurProcessor = -1; 1318 int CurPhysicalId = -1; 1319 int CurSiblings = -1; 1320 int CurCoreId = -1; 1321 for (StringRef Line : strs) { 1322 std::pair<StringRef, StringRef> Data = Line.split(':'); 1323 auto Name = Data.first.trim(); 1324 auto Val = Data.second.trim(); 1325 // These fields are available if the kernel is configured with CONFIG_SMP. 1326 if (Name == "processor") 1327 Val.getAsInteger(10, CurProcessor); 1328 else if (Name == "physical id") 1329 Val.getAsInteger(10, CurPhysicalId); 1330 else if (Name == "siblings") 1331 Val.getAsInteger(10, CurSiblings); 1332 else if (Name == "core id") { 1333 Val.getAsInteger(10, CurCoreId); 1334 // The processor id corresponds to an index into cpu_set_t. 1335 if (CPU_ISSET(CurProcessor, &Affinity)) 1336 CPU_SET(CurPhysicalId * CurSiblings + CurCoreId, &Enabled); 1337 } 1338 } 1339 return CPU_COUNT(&Enabled); 1340 } 1341 #elif defined(__APPLE__) && defined(__x86_64__) 1342 #include <sys/param.h> 1343 #include <sys/sysctl.h> 1344 1345 // Gets the number of *physical cores* on the machine. 1346 int computeHostNumPhysicalCores() { 1347 uint32_t count; 1348 size_t len = sizeof(count); 1349 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1350 if (count < 1) { 1351 int nm[2]; 1352 nm[0] = CTL_HW; 1353 nm[1] = HW_AVAILCPU; 1354 sysctl(nm, 2, &count, &len, NULL, 0); 1355 if (count < 1) 1356 return -1; 1357 } 1358 return count; 1359 } 1360 #elif defined(_WIN32) && LLVM_ENABLE_THREADS != 0 1361 // Defined in llvm/lib/Support/Windows/Threading.inc 1362 int computeHostNumPhysicalCores(); 1363 #else 1364 // On other systems, return -1 to indicate unknown. 1365 static int computeHostNumPhysicalCores() { return -1; } 1366 #endif 1367 1368 int sys::getHostNumPhysicalCores() { 1369 static int NumCores = computeHostNumPhysicalCores(); 1370 return NumCores; 1371 } 1372 1373 #if defined(__i386__) || defined(_M_IX86) || \ 1374 defined(__x86_64__) || defined(_M_X64) 1375 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1376 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1377 unsigned MaxLevel; 1378 union { 1379 unsigned u[3]; 1380 char c[12]; 1381 } text; 1382 1383 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1384 MaxLevel < 1) 1385 return false; 1386 1387 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1388 1389 Features["cx8"] = (EDX >> 8) & 1; 1390 Features["cmov"] = (EDX >> 15) & 1; 1391 Features["mmx"] = (EDX >> 23) & 1; 1392 Features["fxsr"] = (EDX >> 24) & 1; 1393 Features["sse"] = (EDX >> 25) & 1; 1394 Features["sse2"] = (EDX >> 26) & 1; 1395 1396 Features["sse3"] = (ECX >> 0) & 1; 1397 Features["pclmul"] = (ECX >> 1) & 1; 1398 Features["ssse3"] = (ECX >> 9) & 1; 1399 Features["cx16"] = (ECX >> 13) & 1; 1400 Features["sse4.1"] = (ECX >> 19) & 1; 1401 Features["sse4.2"] = (ECX >> 20) & 1; 1402 Features["movbe"] = (ECX >> 22) & 1; 1403 Features["popcnt"] = (ECX >> 23) & 1; 1404 Features["aes"] = (ECX >> 25) & 1; 1405 Features["rdrnd"] = (ECX >> 30) & 1; 1406 1407 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1408 // indicates that the AVX registers will be saved and restored on context 1409 // switch, then we have full AVX support. 1410 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1411 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1412 #if defined(__APPLE__) 1413 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1414 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1415 // set right now. 1416 bool HasAVX512Save = true; 1417 #else 1418 // AVX512 requires additional context to be saved by the OS. 1419 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1420 #endif 1421 1422 Features["avx"] = HasAVXSave; 1423 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave; 1424 // Only enable XSAVE if OS has enabled support for saving YMM state. 1425 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave; 1426 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave; 1427 1428 unsigned MaxExtLevel; 1429 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1430 1431 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1432 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1433 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1); 1434 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1435 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1436 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1437 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1438 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1439 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1440 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1441 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1442 1443 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1); 1444 1445 // Miscellaneous memory related features, detected by 1446 // using the 0x80000008 leaf of the CPUID instruction 1447 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1448 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX); 1449 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1450 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1); 1451 1452 bool HasLeaf7 = 1453 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1454 1455 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1456 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1457 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1458 // AVX2 is only supported if we have the OS save support from AVX. 1459 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave; 1460 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1461 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1462 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1463 // AVX512 is only supported if the OS supports the context save for it. 1464 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1465 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1466 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1467 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1468 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1469 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1470 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1471 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1472 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1473 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1474 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1475 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1476 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1477 1478 Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1); 1479 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1480 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1481 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1); 1482 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save; 1483 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1); 1484 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1); 1485 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave; 1486 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave; 1487 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save; 1488 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save; 1489 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1490 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1); 1491 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1); 1492 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1); 1493 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1); 1494 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1); 1495 1496 Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1); 1497 Features["tsxldtrk"] = HasLeaf7 && ((EDX >> 16) & 1); 1498 // There are two CPUID leafs which information associated with the pconfig 1499 // instruction: 1500 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th 1501 // bit of EDX), while the EAX=0x1b leaf returns information on the 1502 // availability of specific pconfig leafs. 1503 // The target feature here only refers to the the first of these two. 1504 // Users might need to check for the availability of specific pconfig 1505 // leaves using cpuid, since that information is ignored while 1506 // detecting features using the "-march=native" flag. 1507 // For more info, see X86 ISA docs. 1508 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1); 1509 bool HasLeaf7Subleaf1 = 1510 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1511 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save; 1512 1513 bool HasLeafD = MaxLevel >= 0xd && 1514 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1515 1516 // Only enable XSAVE if OS has enabled support for saving YMM state. 1517 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave; 1518 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave; 1519 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave; 1520 1521 bool HasLeaf14 = MaxLevel >= 0x14 && 1522 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX); 1523 1524 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1); 1525 1526 return true; 1527 } 1528 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1529 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1530 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1531 if (!P) 1532 return false; 1533 1534 SmallVector<StringRef, 32> Lines; 1535 P->getBuffer().split(Lines, "\n"); 1536 1537 SmallVector<StringRef, 32> CPUFeatures; 1538 1539 // Look for the CPU features. 1540 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1541 if (Lines[I].startswith("Features")) { 1542 Lines[I].split(CPUFeatures, ' '); 1543 break; 1544 } 1545 1546 #if defined(__aarch64__) 1547 // Keep track of which crypto features we have seen 1548 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1549 uint32_t crypto = 0; 1550 #endif 1551 1552 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1553 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1554 #if defined(__aarch64__) 1555 .Case("asimd", "neon") 1556 .Case("fp", "fp-armv8") 1557 .Case("crc32", "crc") 1558 #else 1559 .Case("half", "fp16") 1560 .Case("neon", "neon") 1561 .Case("vfpv3", "vfp3") 1562 .Case("vfpv3d16", "d16") 1563 .Case("vfpv4", "vfp4") 1564 .Case("idiva", "hwdiv-arm") 1565 .Case("idivt", "hwdiv") 1566 #endif 1567 .Default(""); 1568 1569 #if defined(__aarch64__) 1570 // We need to check crypto separately since we need all of the crypto 1571 // extensions to enable the subtarget feature 1572 if (CPUFeatures[I] == "aes") 1573 crypto |= CAP_AES; 1574 else if (CPUFeatures[I] == "pmull") 1575 crypto |= CAP_PMULL; 1576 else if (CPUFeatures[I] == "sha1") 1577 crypto |= CAP_SHA1; 1578 else if (CPUFeatures[I] == "sha2") 1579 crypto |= CAP_SHA2; 1580 #endif 1581 1582 if (LLVMFeatureStr != "") 1583 Features[LLVMFeatureStr] = true; 1584 } 1585 1586 #if defined(__aarch64__) 1587 // If we have all crypto bits we can add the feature 1588 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1589 Features["crypto"] = true; 1590 #endif 1591 1592 return true; 1593 } 1594 #elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64)) 1595 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1596 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE)) 1597 Features["neon"] = true; 1598 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE)) 1599 Features["crc"] = true; 1600 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) 1601 Features["crypto"] = true; 1602 1603 return true; 1604 } 1605 #else 1606 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1607 #endif 1608 1609 std::string sys::getProcessTriple() { 1610 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1611 Triple PT(Triple::normalize(TargetTripleString)); 1612 1613 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1614 PT = PT.get64BitArchVariant(); 1615 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1616 PT = PT.get32BitArchVariant(); 1617 1618 return PT.str(); 1619 } 1620