1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the operating system Host concept. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Support/Host.h" 15 #include "llvm/ADT/SmallSet.h" 16 #include "llvm/ADT/SmallVector.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include <assert.h> 26 #include <string.h> 27 28 // Include the platform-specific parts of this class. 29 #ifdef LLVM_ON_UNIX 30 #include "Unix/Host.inc" 31 #endif 32 #ifdef LLVM_ON_WIN32 33 #include "Windows/Host.inc" 34 #endif 35 #ifdef _MSC_VER 36 #include <intrin.h> 37 #endif 38 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 39 #include <mach/host_info.h> 40 #include <mach/mach.h> 41 #include <mach/mach_host.h> 42 #include <mach/machine.h> 43 #endif 44 45 #define DEBUG_TYPE "host-detection" 46 47 //===----------------------------------------------------------------------===// 48 // 49 // Implementations of the CPU detection routines 50 // 51 //===----------------------------------------------------------------------===// 52 53 using namespace llvm; 54 55 static std::unique_ptr<llvm::MemoryBuffer> 56 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 57 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 58 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 59 if (std::error_code EC = Text.getError()) { 60 llvm::errs() << "Can't read " 61 << "/proc/cpuinfo: " << EC.message() << "\n"; 62 return nullptr; 63 } 64 return std::move(*Text); 65 } 66 67 StringRef sys::detail::getHostCPUNameForPowerPC( 68 const StringRef &ProcCpuinfoContent) { 69 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 70 // and so we must use an operating-system interface to determine the current 71 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 72 const char *generic = "generic"; 73 74 // The cpu line is second (after the 'processor: 0' line), so if this 75 // buffer is too small then something has changed (or is wrong). 76 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 77 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 78 79 StringRef::const_iterator CIP = CPUInfoStart; 80 81 StringRef::const_iterator CPUStart = 0; 82 size_t CPULen = 0; 83 84 // We need to find the first line which starts with cpu, spaces, and a colon. 85 // After the colon, there may be some additional spaces and then the cpu type. 86 while (CIP < CPUInfoEnd && CPUStart == 0) { 87 if (CIP < CPUInfoEnd && *CIP == '\n') 88 ++CIP; 89 90 if (CIP < CPUInfoEnd && *CIP == 'c') { 91 ++CIP; 92 if (CIP < CPUInfoEnd && *CIP == 'p') { 93 ++CIP; 94 if (CIP < CPUInfoEnd && *CIP == 'u') { 95 ++CIP; 96 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 97 ++CIP; 98 99 if (CIP < CPUInfoEnd && *CIP == ':') { 100 ++CIP; 101 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 102 ++CIP; 103 104 if (CIP < CPUInfoEnd) { 105 CPUStart = CIP; 106 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 107 *CIP != ',' && *CIP != '\n')) 108 ++CIP; 109 CPULen = CIP - CPUStart; 110 } 111 } 112 } 113 } 114 } 115 116 if (CPUStart == 0) 117 while (CIP < CPUInfoEnd && *CIP != '\n') 118 ++CIP; 119 } 120 121 if (CPUStart == 0) 122 return generic; 123 124 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 125 .Case("604e", "604e") 126 .Case("604", "604") 127 .Case("7400", "7400") 128 .Case("7410", "7400") 129 .Case("7447", "7400") 130 .Case("7455", "7450") 131 .Case("G4", "g4") 132 .Case("POWER4", "970") 133 .Case("PPC970FX", "970") 134 .Case("PPC970MP", "970") 135 .Case("G5", "g5") 136 .Case("POWER5", "g5") 137 .Case("A2", "a2") 138 .Case("POWER6", "pwr6") 139 .Case("POWER7", "pwr7") 140 .Case("POWER8", "pwr8") 141 .Case("POWER8E", "pwr8") 142 .Case("POWER8NVL", "pwr8") 143 .Case("POWER9", "pwr9") 144 .Default(generic); 145 } 146 147 StringRef sys::detail::getHostCPUNameForARM( 148 const StringRef &ProcCpuinfoContent) { 149 // The cpuid register on arm is not accessible from user space. On Linux, 150 // it is exposed through the /proc/cpuinfo file. 151 152 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 153 // in all cases. 154 SmallVector<StringRef, 32> Lines; 155 ProcCpuinfoContent.split(Lines, "\n"); 156 157 // Look for the CPU implementer line. 158 StringRef Implementer; 159 StringRef Hardware; 160 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 161 if (Lines[I].startswith("CPU implementer")) 162 Implementer = Lines[I].substr(15).ltrim("\t :"); 163 if (Lines[I].startswith("Hardware")) 164 Hardware = Lines[I].substr(8).ltrim("\t :"); 165 } 166 167 if (Implementer == "0x41") { // ARM Ltd. 168 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 169 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 170 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 171 return "cortex-a53"; 172 173 174 // Look for the CPU part line. 175 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 176 if (Lines[I].startswith("CPU part")) 177 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 178 // values correspond to the "Part number" in the CP15/c0 register. The 179 // contents are specified in the various processor manuals. 180 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 181 .Case("0x926", "arm926ej-s") 182 .Case("0xb02", "mpcore") 183 .Case("0xb36", "arm1136j-s") 184 .Case("0xb56", "arm1156t2-s") 185 .Case("0xb76", "arm1176jz-s") 186 .Case("0xc08", "cortex-a8") 187 .Case("0xc09", "cortex-a9") 188 .Case("0xc0f", "cortex-a15") 189 .Case("0xc20", "cortex-m0") 190 .Case("0xc23", "cortex-m3") 191 .Case("0xc24", "cortex-m4") 192 .Case("0xd04", "cortex-a35") 193 .Case("0xd03", "cortex-a53") 194 .Case("0xd07", "cortex-a57") 195 .Case("0xd08", "cortex-a72") 196 .Case("0xd09", "cortex-a73") 197 .Default("generic"); 198 } 199 200 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 201 // Look for the CPU part line. 202 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 203 if (Lines[I].startswith("CPU part")) 204 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 205 // values correspond to the "Part number" in the CP15/c0 register. The 206 // contents are specified in the various processor manuals. 207 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 208 .Case("0x06f", "krait") // APQ8064 209 .Case("0x201", "kryo") 210 .Case("0x205", "kryo") 211 .Default("generic"); 212 213 return "generic"; 214 } 215 216 StringRef sys::detail::getHostCPUNameForS390x( 217 const StringRef &ProcCpuinfoContent) { 218 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 219 220 // The "processor 0:" line comes after a fair amount of other information, 221 // including a cache breakdown, but this should be plenty. 222 SmallVector<StringRef, 32> Lines; 223 ProcCpuinfoContent.split(Lines, "\n"); 224 225 // Look for the CPU features. 226 SmallVector<StringRef, 32> CPUFeatures; 227 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 228 if (Lines[I].startswith("features")) { 229 size_t Pos = Lines[I].find(":"); 230 if (Pos != StringRef::npos) { 231 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 232 break; 233 } 234 } 235 236 // We need to check for the presence of vector support independently of 237 // the machine type, since we may only use the vector register set when 238 // supported by the kernel (and hypervisor). 239 bool HaveVectorSupport = false; 240 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 241 if (CPUFeatures[I] == "vx") 242 HaveVectorSupport = true; 243 } 244 245 // Now check the processor machine type. 246 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 247 if (Lines[I].startswith("processor ")) { 248 size_t Pos = Lines[I].find("machine = "); 249 if (Pos != StringRef::npos) { 250 Pos += sizeof("machine = ") - 1; 251 unsigned int Id; 252 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 253 if (Id >= 2964 && HaveVectorSupport) 254 return "z13"; 255 if (Id >= 2827) 256 return "zEC12"; 257 if (Id >= 2817) 258 return "z196"; 259 } 260 } 261 break; 262 } 263 } 264 265 return "generic"; 266 } 267 268 #if defined(__i386__) || defined(_M_IX86) || \ 269 defined(__x86_64__) || defined(_M_X64) 270 271 enum VendorSignatures { 272 SIG_INTEL = 0x756e6547 /* Genu */, 273 SIG_AMD = 0x68747541 /* Auth */ 274 }; 275 276 enum ProcessorVendors { 277 VENDOR_INTEL = 1, 278 VENDOR_AMD, 279 VENDOR_OTHER, 280 VENDOR_MAX 281 }; 282 283 enum ProcessorTypes { 284 INTEL_BONNELL = 1, 285 INTEL_CORE2, 286 INTEL_COREI7, 287 AMDFAM10H, 288 AMDFAM15H, 289 INTEL_SILVERMONT, 290 INTEL_KNL, 291 AMD_BTVER1, 292 AMD_BTVER2, 293 AMDFAM17H, 294 // Entries below this are not in libgcc/compiler-rt. 295 INTEL_i386, 296 INTEL_i486, 297 INTEL_PENTIUM, 298 INTEL_PENTIUM_PRO, 299 INTEL_PENTIUM_II, 300 INTEL_PENTIUM_III, 301 INTEL_PENTIUM_IV, 302 INTEL_PENTIUM_M, 303 INTEL_CORE_DUO, 304 INTEL_X86_64, 305 INTEL_NOCONA, 306 INTEL_PRESCOTT, 307 AMD_i486, 308 AMDPENTIUM, 309 AMDATHLON, 310 INTEL_GOLDMONT, 311 CPU_TYPE_MAX 312 }; 313 314 enum ProcessorSubtypes { 315 INTEL_COREI7_NEHALEM = 1, 316 INTEL_COREI7_WESTMERE, 317 INTEL_COREI7_SANDYBRIDGE, 318 AMDFAM10H_BARCELONA, 319 AMDFAM10H_SHANGHAI, 320 AMDFAM10H_ISTANBUL, 321 AMDFAM15H_BDVER1, 322 AMDFAM15H_BDVER2, 323 AMDFAM15H_BDVER3, 324 AMDFAM15H_BDVER4, 325 AMDFAM17H_ZNVER1, 326 INTEL_COREI7_IVYBRIDGE, 327 INTEL_COREI7_HASWELL, 328 INTEL_COREI7_BROADWELL, 329 INTEL_COREI7_SKYLAKE, 330 INTEL_COREI7_SKYLAKE_AVX512, 331 // Entries below this are not in libgcc/compiler-rt. 332 INTEL_PENTIUM_MMX, 333 INTEL_CORE2_65, 334 INTEL_CORE2_45, 335 AMDPENTIUM_K6, 336 AMDPENTIUM_K62, 337 AMDPENTIUM_K63, 338 AMDPENTIUM_GEODE, 339 AMDATHLON_TBIRD, 340 AMDATHLON_MP, 341 AMDATHLON_XP, 342 AMDATHLON_K8SSE3, 343 AMDATHLON_OPTERON, 344 AMDATHLON_FX, 345 AMDATHLON_64, 346 CPU_SUBTYPE_MAX 347 }; 348 349 enum ProcessorFeatures { 350 FEATURE_CMOV = 0, 351 FEATURE_MMX, 352 FEATURE_POPCNT, 353 FEATURE_SSE, 354 FEATURE_SSE2, 355 FEATURE_SSE3, 356 FEATURE_SSSE3, 357 FEATURE_SSE4_1, 358 FEATURE_SSE4_2, 359 FEATURE_AVX, 360 FEATURE_AVX2, 361 FEATURE_SSE4_A, 362 FEATURE_FMA4, 363 FEATURE_XOP, 364 FEATURE_FMA, 365 FEATURE_AVX512F, 366 FEATURE_BMI, 367 FEATURE_BMI2, 368 FEATURE_AES, 369 FEATURE_PCLMUL, 370 FEATURE_AVX512VL, 371 FEATURE_AVX512BW, 372 FEATURE_AVX512DQ, 373 FEATURE_AVX512CD, 374 FEATURE_AVX512ER, 375 FEATURE_AVX512PF, 376 FEATURE_AVX512VBMI, 377 FEATURE_AVX512IFMA, 378 FEATURE_AVX5124VNNIW, 379 FEATURE_AVX5124FMAPS, 380 FEATURE_AVX512VPOPCNTDQ, 381 // Only one bit free left in the first 32 features. 382 FEATURE_MOVBE = 32, 383 FEATURE_ADX, 384 FEATURE_EM64T 385 }; 386 387 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 388 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 389 // support. Consequently, for i386, the presence of CPUID is checked first 390 // via the corresponding eflags bit. 391 // Removal of cpuid.h header motivated by PR30384 392 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 393 // or test-suite, but are used in external projects e.g. libstdcxx 394 static bool isCpuIdSupported() { 395 #if defined(__GNUC__) || defined(__clang__) 396 #if defined(__i386__) 397 int __cpuid_supported; 398 __asm__(" pushfl\n" 399 " popl %%eax\n" 400 " movl %%eax,%%ecx\n" 401 " xorl $0x00200000,%%eax\n" 402 " pushl %%eax\n" 403 " popfl\n" 404 " pushfl\n" 405 " popl %%eax\n" 406 " movl $0,%0\n" 407 " cmpl %%eax,%%ecx\n" 408 " je 1f\n" 409 " movl $1,%0\n" 410 "1:" 411 : "=r"(__cpuid_supported) 412 : 413 : "eax", "ecx"); 414 if (!__cpuid_supported) 415 return false; 416 #endif 417 return true; 418 #endif 419 return true; 420 } 421 422 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 423 /// the specified arguments. If we can't run cpuid on the host, return true. 424 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 425 unsigned *rECX, unsigned *rEDX) { 426 #if defined(__GNUC__) || defined(__clang__) 427 #if defined(__x86_64__) 428 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 429 // FIXME: should we save this for Clang? 430 __asm__("movq\t%%rbx, %%rsi\n\t" 431 "cpuid\n\t" 432 "xchgq\t%%rbx, %%rsi\n\t" 433 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 434 : "a"(value)); 435 return false; 436 #elif defined(__i386__) 437 __asm__("movl\t%%ebx, %%esi\n\t" 438 "cpuid\n\t" 439 "xchgl\t%%ebx, %%esi\n\t" 440 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 441 : "a"(value)); 442 return false; 443 #else 444 return true; 445 #endif 446 #elif defined(_MSC_VER) 447 // The MSVC intrinsic is portable across x86 and x64. 448 int registers[4]; 449 __cpuid(registers, value); 450 *rEAX = registers[0]; 451 *rEBX = registers[1]; 452 *rECX = registers[2]; 453 *rEDX = registers[3]; 454 return false; 455 #else 456 return true; 457 #endif 458 } 459 460 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 461 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 462 /// return true. 463 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 464 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 465 unsigned *rEDX) { 466 #if defined(__x86_64__) || defined(_M_X64) 467 #if defined(__GNUC__) || defined(__clang__) 468 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 469 // FIXME: should we save this for Clang? 470 __asm__("movq\t%%rbx, %%rsi\n\t" 471 "cpuid\n\t" 472 "xchgq\t%%rbx, %%rsi\n\t" 473 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 474 : "a"(value), "c"(subleaf)); 475 return false; 476 #elif defined(_MSC_VER) 477 int registers[4]; 478 __cpuidex(registers, value, subleaf); 479 *rEAX = registers[0]; 480 *rEBX = registers[1]; 481 *rECX = registers[2]; 482 *rEDX = registers[3]; 483 return false; 484 #else 485 return true; 486 #endif 487 #elif defined(__i386__) || defined(_M_IX86) 488 #if defined(__GNUC__) || defined(__clang__) 489 __asm__("movl\t%%ebx, %%esi\n\t" 490 "cpuid\n\t" 491 "xchgl\t%%ebx, %%esi\n\t" 492 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 493 : "a"(value), "c"(subleaf)); 494 return false; 495 #elif defined(_MSC_VER) 496 __asm { 497 mov eax,value 498 mov ecx,subleaf 499 cpuid 500 mov esi,rEAX 501 mov dword ptr [esi],eax 502 mov esi,rEBX 503 mov dword ptr [esi],ebx 504 mov esi,rECX 505 mov dword ptr [esi],ecx 506 mov esi,rEDX 507 mov dword ptr [esi],edx 508 } 509 return false; 510 #else 511 return true; 512 #endif 513 #else 514 return true; 515 #endif 516 } 517 518 // Read control register 0 (XCR0). Used to detect features such as AVX. 519 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 520 #if defined(__GNUC__) || defined(__clang__) 521 // Check xgetbv; this uses a .byte sequence instead of the instruction 522 // directly because older assemblers do not include support for xgetbv and 523 // there is no easy way to conditionally compile based on the assembler used. 524 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 525 return false; 526 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 527 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 528 *rEAX = Result; 529 *rEDX = Result >> 32; 530 return false; 531 #else 532 return true; 533 #endif 534 } 535 536 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 537 unsigned *Model) { 538 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 539 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 540 if (*Family == 6 || *Family == 0xf) { 541 if (*Family == 0xf) 542 // Examine extended family ID if family ID is F. 543 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 544 // Examine extended model ID if family ID is 6 or F. 545 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 546 } 547 } 548 549 static void 550 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 551 unsigned Brand_id, unsigned Features, 552 unsigned Features2, unsigned *Type, 553 unsigned *Subtype) { 554 if (Brand_id != 0) 555 return; 556 switch (Family) { 557 case 3: 558 *Type = INTEL_i386; 559 break; 560 case 4: 561 switch (Model) { 562 case 0: // Intel486 DX processors 563 case 1: // Intel486 DX processors 564 case 2: // Intel486 SX processors 565 case 3: // Intel487 processors, IntelDX2 OverDrive processors, 566 // IntelDX2 processors 567 case 4: // Intel486 SL processor 568 case 5: // IntelSX2 processors 569 case 7: // Write-Back Enhanced IntelDX2 processors 570 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors 571 default: 572 *Type = INTEL_i486; 573 break; 574 } 575 break; 576 case 5: 577 switch (Model) { 578 case 1: // Pentium OverDrive processor for Pentium processor (60, 66), 579 // Pentium processors (60, 66) 580 case 2: // Pentium OverDrive processor for Pentium processor (75, 90, 581 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133, 582 // 150, 166, 200) 583 case 3: // Pentium OverDrive processors for Intel486 processor-based 584 // systems 585 *Type = INTEL_PENTIUM; 586 break; 587 case 4: // Pentium OverDrive processor with MMX technology for Pentium 588 // processor (75, 90, 100, 120, 133), Pentium processor with 589 // MMX technology (166, 200) 590 *Type = INTEL_PENTIUM; 591 *Subtype = INTEL_PENTIUM_MMX; 592 break; 593 default: 594 *Type = INTEL_PENTIUM; 595 break; 596 } 597 break; 598 case 6: 599 switch (Model) { 600 case 0x01: // Pentium Pro processor 601 *Type = INTEL_PENTIUM_PRO; 602 break; 603 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 604 // model 03 605 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 606 // model 05, and Intel Celeron processor, model 05 607 case 0x06: // Celeron processor, model 06 608 *Type = INTEL_PENTIUM_II; 609 break; 610 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 611 // processor, model 07 612 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 613 // model 08, and Celeron processor, model 08 614 case 0x0a: // Pentium III Xeon processor, model 0Ah 615 case 0x0b: // Pentium III processor, model 0Bh 616 *Type = INTEL_PENTIUM_III; 617 break; 618 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 619 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 620 // 0Dh. All processors are manufactured using the 90 nm process. 621 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 622 // Integrated Processor with Intel QuickAssist Technology 623 *Type = INTEL_PENTIUM_M; 624 break; 625 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 626 // 0Eh. All processors are manufactured using the 65 nm process. 627 *Type = INTEL_CORE_DUO; 628 break; // yonah 629 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 630 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 631 // mobile processor, Intel Core 2 Extreme processor, Intel 632 // Pentium Dual-Core processor, Intel Xeon processor, model 633 // 0Fh. All processors are manufactured using the 65 nm process. 634 case 0x16: // Intel Celeron processor model 16h. All processors are 635 // manufactured using the 65 nm process 636 *Type = INTEL_CORE2; // "core2" 637 *Subtype = INTEL_CORE2_65; 638 break; 639 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 640 // 17h. All processors are manufactured using the 45 nm process. 641 // 642 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 643 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 644 // the 45 nm process. 645 *Type = INTEL_CORE2; // "penryn" 646 *Subtype = INTEL_CORE2_45; 647 break; 648 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 649 // processors are manufactured using the 45 nm process. 650 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 651 // As found in a Summer 2010 model iMac. 652 case 0x1f: 653 case 0x2e: // Nehalem EX 654 *Type = INTEL_COREI7; // "nehalem" 655 *Subtype = INTEL_COREI7_NEHALEM; 656 break; 657 case 0x25: // Intel Core i7, laptop version. 658 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 659 // processors are manufactured using the 32 nm process. 660 case 0x2f: // Westmere EX 661 *Type = INTEL_COREI7; // "westmere" 662 *Subtype = INTEL_COREI7_WESTMERE; 663 break; 664 case 0x2a: // Intel Core i7 processor. All processors are manufactured 665 // using the 32 nm process. 666 case 0x2d: 667 *Type = INTEL_COREI7; //"sandybridge" 668 *Subtype = INTEL_COREI7_SANDYBRIDGE; 669 break; 670 case 0x3a: 671 case 0x3e: // Ivy Bridge EP 672 *Type = INTEL_COREI7; // "ivybridge" 673 *Subtype = INTEL_COREI7_IVYBRIDGE; 674 break; 675 676 // Haswell: 677 case 0x3c: 678 case 0x3f: 679 case 0x45: 680 case 0x46: 681 *Type = INTEL_COREI7; // "haswell" 682 *Subtype = INTEL_COREI7_HASWELL; 683 break; 684 685 // Broadwell: 686 case 0x3d: 687 case 0x47: 688 case 0x4f: 689 case 0x56: 690 *Type = INTEL_COREI7; // "broadwell" 691 *Subtype = INTEL_COREI7_BROADWELL; 692 break; 693 694 // Skylake: 695 case 0x4e: // Skylake mobile 696 case 0x5e: // Skylake desktop 697 case 0x8e: // Kaby Lake mobile 698 case 0x9e: // Kaby Lake desktop 699 *Type = INTEL_COREI7; // "skylake" 700 *Subtype = INTEL_COREI7_SKYLAKE; 701 break; 702 703 // Skylake Xeon: 704 case 0x55: 705 *Type = INTEL_COREI7; 706 *Subtype = INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 707 break; 708 709 case 0x1c: // Most 45 nm Intel Atom processors 710 case 0x26: // 45 nm Atom Lincroft 711 case 0x27: // 32 nm Atom Medfield 712 case 0x35: // 32 nm Atom Midview 713 case 0x36: // 32 nm Atom Midview 714 *Type = INTEL_BONNELL; 715 break; // "bonnell" 716 717 // Atom Silvermont codes from the Intel software optimization guide. 718 case 0x37: 719 case 0x4a: 720 case 0x4d: 721 case 0x5a: 722 case 0x5d: 723 case 0x4c: // really airmont 724 *Type = INTEL_SILVERMONT; 725 break; // "silvermont" 726 // Goldmont: 727 case 0x5c: 728 case 0x5f: 729 *Type = INTEL_GOLDMONT; 730 break; // "goldmont" 731 case 0x57: 732 *Type = INTEL_KNL; // knl 733 break; 734 735 default: // Unknown family 6 CPU, try to guess. 736 if (Features & (1 << FEATURE_AVX512F)) { 737 *Type = INTEL_KNL; // knl 738 break; 739 } 740 if (Features2 & (1 << (FEATURE_ADX - 32))) { 741 *Type = INTEL_COREI7; 742 *Subtype = INTEL_COREI7_BROADWELL; 743 break; 744 } 745 if (Features & (1 << FEATURE_AVX2)) { 746 *Type = INTEL_COREI7; 747 *Subtype = INTEL_COREI7_HASWELL; 748 break; 749 } 750 if (Features & (1 << FEATURE_AVX)) { 751 *Type = INTEL_COREI7; 752 *Subtype = INTEL_COREI7_SANDYBRIDGE; 753 break; 754 } 755 if (Features & (1 << FEATURE_SSE4_2)) { 756 if (Features2 & (1 << (FEATURE_MOVBE - 32))) { 757 *Type = INTEL_SILVERMONT; 758 } else { 759 *Type = INTEL_COREI7; 760 *Subtype = INTEL_COREI7_NEHALEM; 761 } 762 break; 763 } 764 if (Features & (1 << FEATURE_SSE4_1)) { 765 *Type = INTEL_CORE2; // "penryn" 766 *Subtype = INTEL_CORE2_45; 767 break; 768 } 769 if (Features & (1 << FEATURE_SSSE3)) { 770 if (Features2 & (1 << (FEATURE_MOVBE - 32))) { 771 *Type = INTEL_BONNELL; // "bonnell" 772 } else { 773 *Type = INTEL_CORE2; // "core2" 774 *Subtype = INTEL_CORE2_65; 775 } 776 break; 777 } 778 if (Features2 & (1 << (FEATURE_EM64T - 32))) { 779 *Type = INTEL_X86_64; 780 break; // x86-64 781 } 782 if (Features & (1 << FEATURE_SSE2)) { 783 *Type = INTEL_PENTIUM_M; 784 break; 785 } 786 if (Features & (1 << FEATURE_SSE)) { 787 *Type = INTEL_PENTIUM_III; 788 break; 789 } 790 if (Features & (1 << FEATURE_MMX)) { 791 *Type = INTEL_PENTIUM_II; 792 break; 793 } 794 *Type = INTEL_PENTIUM_PRO; 795 break; 796 } 797 break; 798 case 15: { 799 switch (Model) { 800 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are 801 // model 00h and manufactured using the 0.18 micron process. 802 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon 803 // processor MP, and Intel Celeron processor. All processors are 804 // model 01h and manufactured using the 0.18 micron process. 805 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M, 806 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron 807 // processor, and Mobile Intel Celeron processor. All processors 808 // are model 02h and manufactured using the 0.13 micron process. 809 *Type = ((Features2 & (1 << (FEATURE_EM64T - 32))) ? INTEL_X86_64 810 : INTEL_PENTIUM_IV); 811 break; 812 813 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D 814 // processor. All processors are model 03h and manufactured using 815 // the 90 nm process. 816 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition, 817 // Pentium D processor, Intel Xeon processor, Intel Xeon 818 // processor MP, Intel Celeron D processor. All processors are 819 // model 04h and manufactured using the 90 nm process. 820 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor 821 // Extreme Edition, Intel Xeon processor, Intel Xeon processor 822 // MP, Intel Celeron D processor. All processors are model 06h 823 // and manufactured using the 65 nm process. 824 *Type = ((Features2 & (1 << (FEATURE_EM64T - 32))) ? INTEL_NOCONA 825 : INTEL_PRESCOTT); 826 break; 827 828 default: 829 *Type = ((Features2 & (1 << (FEATURE_EM64T - 32))) ? INTEL_X86_64 830 : INTEL_PENTIUM_IV); 831 break; 832 } 833 break; 834 } 835 default: 836 break; /*"generic"*/ 837 } 838 } 839 840 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 841 unsigned Features, unsigned *Type, 842 unsigned *Subtype) { 843 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 844 // appears to be no way to generate the wide variety of AMD-specific targets 845 // from the information returned from CPUID. 846 switch (Family) { 847 case 4: 848 *Type = AMD_i486; 849 break; 850 case 5: 851 *Type = AMDPENTIUM; 852 switch (Model) { 853 case 6: 854 case 7: 855 *Subtype = AMDPENTIUM_K6; 856 break; // "k6" 857 case 8: 858 *Subtype = AMDPENTIUM_K62; 859 break; // "k6-2" 860 case 9: 861 case 13: 862 *Subtype = AMDPENTIUM_K63; 863 break; // "k6-3" 864 case 10: 865 *Subtype = AMDPENTIUM_GEODE; 866 break; // "geode" 867 } 868 break; 869 case 6: 870 *Type = AMDATHLON; 871 switch (Model) { 872 case 4: 873 *Subtype = AMDATHLON_TBIRD; 874 break; // "athlon-tbird" 875 case 6: 876 case 7: 877 case 8: 878 *Subtype = AMDATHLON_MP; 879 break; // "athlon-mp" 880 case 10: 881 *Subtype = AMDATHLON_XP; 882 break; // "athlon-xp" 883 } 884 break; 885 case 15: 886 *Type = AMDATHLON; 887 if (Features & (1 << FEATURE_SSE3)) { 888 *Subtype = AMDATHLON_K8SSE3; 889 break; // "k8-sse3" 890 } 891 switch (Model) { 892 case 1: 893 *Subtype = AMDATHLON_OPTERON; 894 break; // "opteron" 895 case 5: 896 *Subtype = AMDATHLON_FX; 897 break; // "athlon-fx"; also opteron 898 default: 899 *Subtype = AMDATHLON_64; 900 break; // "athlon64" 901 } 902 break; 903 case 16: 904 *Type = AMDFAM10H; // "amdfam10" 905 switch (Model) { 906 case 2: 907 *Subtype = AMDFAM10H_BARCELONA; 908 break; 909 case 4: 910 *Subtype = AMDFAM10H_SHANGHAI; 911 break; 912 case 8: 913 *Subtype = AMDFAM10H_ISTANBUL; 914 break; 915 } 916 break; 917 case 20: 918 *Type = AMD_BTVER1; 919 break; // "btver1"; 920 case 21: 921 *Type = AMDFAM15H; 922 if (Model >= 0x60 && Model <= 0x7f) { 923 *Subtype = AMDFAM15H_BDVER4; 924 break; // "bdver4"; 60h-7Fh: Excavator 925 } 926 if (Model >= 0x30 && Model <= 0x3f) { 927 *Subtype = AMDFAM15H_BDVER3; 928 break; // "bdver3"; 30h-3Fh: Steamroller 929 } 930 if (Model >= 0x10 && Model <= 0x1f) { 931 *Subtype = AMDFAM15H_BDVER2; 932 break; // "bdver2"; 10h-1Fh: Piledriver 933 } 934 if (Model <= 0x0f) { 935 *Subtype = AMDFAM15H_BDVER1; 936 break; // "bdver1"; 00h-0Fh: Bulldozer 937 } 938 break; 939 case 22: 940 *Type = AMD_BTVER2; 941 break; // "btver2" 942 case 23: 943 *Type = AMDFAM17H; 944 *Subtype = AMDFAM17H_ZNVER1; 945 break; 946 default: 947 break; // "generic" 948 } 949 } 950 951 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 952 unsigned *FeaturesOut, 953 unsigned *Features2Out) { 954 unsigned Features = 0; 955 unsigned Features2 = 0; 956 unsigned EAX, EBX; 957 958 if ((EDX >> 15) & 1) 959 Features |= 1 << FEATURE_CMOV; 960 if ((EDX >> 23) & 1) 961 Features |= 1 << FEATURE_MMX; 962 if ((EDX >> 25) & 1) 963 Features |= 1 << FEATURE_SSE; 964 if ((EDX >> 26) & 1) 965 Features |= 1 << FEATURE_SSE2; 966 967 if ((ECX >> 0) & 1) 968 Features |= 1 << FEATURE_SSE3; 969 if ((ECX >> 1) & 1) 970 Features |= 1 << FEATURE_PCLMUL; 971 if ((ECX >> 9) & 1) 972 Features |= 1 << FEATURE_SSSE3; 973 if ((ECX >> 12) & 1) 974 Features |= 1 << FEATURE_FMA; 975 if ((ECX >> 19) & 1) 976 Features |= 1 << FEATURE_SSE4_1; 977 if ((ECX >> 20) & 1) 978 Features |= 1 << FEATURE_SSE4_2; 979 if ((ECX >> 23) & 1) 980 Features |= 1 << FEATURE_POPCNT; 981 if ((ECX >> 25) & 1) 982 Features |= 1 << FEATURE_AES; 983 984 if ((ECX >> 22) & 1) 985 Features2 |= 1 << (FEATURE_MOVBE - 32); 986 987 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 988 // indicates that the AVX registers will be saved and restored on context 989 // switch, then we have full AVX support. 990 const unsigned AVXBits = (1 << 27) | (1 << 28); 991 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 992 ((EAX & 0x6) == 0x6); 993 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 994 995 if (HasAVX) 996 Features |= 1 << FEATURE_AVX; 997 998 bool HasLeaf7 = 999 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1000 1001 if (HasLeaf7 && ((EBX >> 3) & 1)) 1002 Features |= 1 << FEATURE_BMI; 1003 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 1004 Features |= 1 << FEATURE_AVX2; 1005 if (HasLeaf7 && ((EBX >> 9) & 1)) 1006 Features |= 1 << FEATURE_BMI2; 1007 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 1008 Features |= 1 << FEATURE_AVX512F; 1009 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 1010 Features |= 1 << FEATURE_AVX512DQ; 1011 if (HasLeaf7 && ((EBX >> 19) & 1)) 1012 Features2 |= 1 << (FEATURE_ADX - 32); 1013 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 1014 Features |= 1 << FEATURE_AVX512IFMA; 1015 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 1016 Features |= 1 << FEATURE_AVX512PF; 1017 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 1018 Features |= 1 << FEATURE_AVX512ER; 1019 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 1020 Features |= 1 << FEATURE_AVX512CD; 1021 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 1022 Features |= 1 << FEATURE_AVX512BW; 1023 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 1024 Features |= 1 << FEATURE_AVX512VL; 1025 1026 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 1027 Features |= 1 << FEATURE_AVX512VBMI; 1028 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1029 Features |= 1 << FEATURE_AVX512VPOPCNTDQ; 1030 1031 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1032 Features |= 1 << FEATURE_AVX5124VNNIW; 1033 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1034 Features |= 1 << FEATURE_AVX5124FMAPS; 1035 1036 unsigned MaxExtLevel; 1037 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1038 1039 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1040 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1041 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1042 Features |= 1 << FEATURE_SSE4_A; 1043 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1044 Features |= 1 << FEATURE_XOP; 1045 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1046 Features |= 1 << FEATURE_FMA4; 1047 1048 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1049 Features2 |= 1 << (FEATURE_EM64T - 32); 1050 1051 *FeaturesOut = Features; 1052 *Features2Out = Features2; 1053 } 1054 1055 StringRef sys::getHostCPUName() { 1056 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1057 unsigned MaxLeaf, Vendor; 1058 1059 #if defined(__GNUC__) || defined(__clang__) 1060 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here 1061 // and simplify it to not invoke __cpuid (like cpu_model.c in 1062 // compiler-rt/lib/builtins/cpu_model.c? 1063 // Opting for the second option. 1064 if(!isCpuIdSupported()) 1065 return "generic"; 1066 #endif 1067 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) 1068 return "generic"; 1069 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1070 1071 unsigned Brand_id = EBX & 0xff; 1072 unsigned Family = 0, Model = 0; 1073 unsigned Features = 0, Features2 = 0; 1074 detectX86FamilyModel(EAX, &Family, &Model); 1075 getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2); 1076 1077 unsigned Type; 1078 unsigned Subtype; 1079 1080 if (Vendor == SIG_INTEL) { 1081 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, 1082 Features2, &Type, &Subtype); 1083 switch (Type) { 1084 case INTEL_i386: 1085 return "i386"; 1086 case INTEL_i486: 1087 return "i486"; 1088 case INTEL_PENTIUM: 1089 if (Subtype == INTEL_PENTIUM_MMX) 1090 return "pentium-mmx"; 1091 return "pentium"; 1092 case INTEL_PENTIUM_PRO: 1093 return "pentiumpro"; 1094 case INTEL_PENTIUM_II: 1095 return "pentium2"; 1096 case INTEL_PENTIUM_III: 1097 return "pentium3"; 1098 case INTEL_PENTIUM_IV: 1099 return "pentium4"; 1100 case INTEL_PENTIUM_M: 1101 return "pentium-m"; 1102 case INTEL_CORE_DUO: 1103 return "yonah"; 1104 case INTEL_CORE2: 1105 switch (Subtype) { 1106 case INTEL_CORE2_65: 1107 return "core2"; 1108 case INTEL_CORE2_45: 1109 return "penryn"; 1110 default: 1111 llvm_unreachable("Unexpected subtype!"); 1112 } 1113 case INTEL_COREI7: 1114 switch (Subtype) { 1115 case INTEL_COREI7_NEHALEM: 1116 return "nehalem"; 1117 case INTEL_COREI7_WESTMERE: 1118 return "westmere"; 1119 case INTEL_COREI7_SANDYBRIDGE: 1120 return "sandybridge"; 1121 case INTEL_COREI7_IVYBRIDGE: 1122 return "ivybridge"; 1123 case INTEL_COREI7_HASWELL: 1124 return "haswell"; 1125 case INTEL_COREI7_BROADWELL: 1126 return "broadwell"; 1127 case INTEL_COREI7_SKYLAKE: 1128 return "skylake"; 1129 case INTEL_COREI7_SKYLAKE_AVX512: 1130 return "skylake-avx512"; 1131 default: 1132 llvm_unreachable("Unexpected subtype!"); 1133 } 1134 case INTEL_BONNELL: 1135 return "bonnell"; 1136 case INTEL_SILVERMONT: 1137 return "silvermont"; 1138 case INTEL_GOLDMONT: 1139 return "goldmont"; 1140 case INTEL_KNL: 1141 return "knl"; 1142 case INTEL_X86_64: 1143 return "x86-64"; 1144 case INTEL_NOCONA: 1145 return "nocona"; 1146 case INTEL_PRESCOTT: 1147 return "prescott"; 1148 default: 1149 break; 1150 } 1151 } else if (Vendor == SIG_AMD) { 1152 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1153 switch (Type) { 1154 case AMD_i486: 1155 return "i486"; 1156 case AMDPENTIUM: 1157 switch (Subtype) { 1158 case AMDPENTIUM_K6: 1159 return "k6"; 1160 case AMDPENTIUM_K62: 1161 return "k6-2"; 1162 case AMDPENTIUM_K63: 1163 return "k6-3"; 1164 case AMDPENTIUM_GEODE: 1165 return "geode"; 1166 default: 1167 return "pentium"; 1168 } 1169 case AMDATHLON: 1170 switch (Subtype) { 1171 case AMDATHLON_TBIRD: 1172 return "athlon-tbird"; 1173 case AMDATHLON_MP: 1174 return "athlon-mp"; 1175 case AMDATHLON_XP: 1176 return "athlon-xp"; 1177 case AMDATHLON_K8SSE3: 1178 return "k8-sse3"; 1179 case AMDATHLON_OPTERON: 1180 return "opteron"; 1181 case AMDATHLON_FX: 1182 return "athlon-fx"; 1183 case AMDATHLON_64: 1184 return "athlon64"; 1185 default: 1186 llvm_unreachable("Unexpected subtype!"); 1187 } 1188 case AMDFAM10H: 1189 return "amdfam10"; 1190 case AMD_BTVER1: 1191 return "btver1"; 1192 case AMDFAM15H: 1193 switch (Subtype) { 1194 default: // There are gaps in the subtype detection. 1195 case AMDFAM15H_BDVER1: 1196 return "bdver1"; 1197 case AMDFAM15H_BDVER2: 1198 return "bdver2"; 1199 case AMDFAM15H_BDVER3: 1200 return "bdver3"; 1201 case AMDFAM15H_BDVER4: 1202 return "bdver4"; 1203 } 1204 case AMD_BTVER2: 1205 return "btver2"; 1206 case AMDFAM17H: 1207 return "znver1"; 1208 default: 1209 break; 1210 } 1211 } 1212 return "generic"; 1213 } 1214 1215 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1216 StringRef sys::getHostCPUName() { 1217 host_basic_info_data_t hostInfo; 1218 mach_msg_type_number_t infoCount; 1219 1220 infoCount = HOST_BASIC_INFO_COUNT; 1221 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo, 1222 &infoCount); 1223 1224 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1225 return "generic"; 1226 1227 switch (hostInfo.cpu_subtype) { 1228 case CPU_SUBTYPE_POWERPC_601: 1229 return "601"; 1230 case CPU_SUBTYPE_POWERPC_602: 1231 return "602"; 1232 case CPU_SUBTYPE_POWERPC_603: 1233 return "603"; 1234 case CPU_SUBTYPE_POWERPC_603e: 1235 return "603e"; 1236 case CPU_SUBTYPE_POWERPC_603ev: 1237 return "603ev"; 1238 case CPU_SUBTYPE_POWERPC_604: 1239 return "604"; 1240 case CPU_SUBTYPE_POWERPC_604e: 1241 return "604e"; 1242 case CPU_SUBTYPE_POWERPC_620: 1243 return "620"; 1244 case CPU_SUBTYPE_POWERPC_750: 1245 return "750"; 1246 case CPU_SUBTYPE_POWERPC_7400: 1247 return "7400"; 1248 case CPU_SUBTYPE_POWERPC_7450: 1249 return "7450"; 1250 case CPU_SUBTYPE_POWERPC_970: 1251 return "970"; 1252 default:; 1253 } 1254 1255 return "generic"; 1256 } 1257 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1258 StringRef sys::getHostCPUName() { 1259 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1260 const StringRef& Content = P ? P->getBuffer() : ""; 1261 return detail::getHostCPUNameForPowerPC(Content); 1262 } 1263 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1264 StringRef sys::getHostCPUName() { 1265 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1266 const StringRef& Content = P ? P->getBuffer() : ""; 1267 return detail::getHostCPUNameForARM(Content); 1268 } 1269 #elif defined(__linux__) && defined(__s390x__) 1270 StringRef sys::getHostCPUName() { 1271 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1272 const StringRef& Content = P ? P->getBuffer() : ""; 1273 return detail::getHostCPUNameForS390x(Content); 1274 } 1275 #else 1276 StringRef sys::getHostCPUName() { return "generic"; } 1277 #endif 1278 1279 #if defined(__linux__) && defined(__x86_64__) 1280 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1281 // using the number of unique physical/core id pairs. The following 1282 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1283 static int computeHostNumPhysicalCores() { 1284 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1285 // mmapped because it appears to have 0 size. 1286 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1287 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1288 if (std::error_code EC = Text.getError()) { 1289 llvm::errs() << "Can't read " 1290 << "/proc/cpuinfo: " << EC.message() << "\n"; 1291 return -1; 1292 } 1293 SmallVector<StringRef, 8> strs; 1294 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1295 /*KeepEmpty=*/false); 1296 int CurPhysicalId = -1; 1297 int CurCoreId = -1; 1298 SmallSet<std::pair<int, int>, 32> UniqueItems; 1299 for (auto &Line : strs) { 1300 Line = Line.trim(); 1301 if (!Line.startswith("physical id") && !Line.startswith("core id")) 1302 continue; 1303 std::pair<StringRef, StringRef> Data = Line.split(':'); 1304 auto Name = Data.first.trim(); 1305 auto Val = Data.second.trim(); 1306 if (Name == "physical id") { 1307 assert(CurPhysicalId == -1 && 1308 "Expected a core id before seeing another physical id"); 1309 Val.getAsInteger(10, CurPhysicalId); 1310 } 1311 if (Name == "core id") { 1312 assert(CurCoreId == -1 && 1313 "Expected a physical id before seeing another core id"); 1314 Val.getAsInteger(10, CurCoreId); 1315 } 1316 if (CurPhysicalId != -1 && CurCoreId != -1) { 1317 UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId)); 1318 CurPhysicalId = -1; 1319 CurCoreId = -1; 1320 } 1321 } 1322 return UniqueItems.size(); 1323 } 1324 #elif defined(__APPLE__) && defined(__x86_64__) 1325 #include <sys/param.h> 1326 #include <sys/sysctl.h> 1327 1328 // Gets the number of *physical cores* on the machine. 1329 static int computeHostNumPhysicalCores() { 1330 uint32_t count; 1331 size_t len = sizeof(count); 1332 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1333 if (count < 1) { 1334 int nm[2]; 1335 nm[0] = CTL_HW; 1336 nm[1] = HW_AVAILCPU; 1337 sysctl(nm, 2, &count, &len, NULL, 0); 1338 if (count < 1) 1339 return -1; 1340 } 1341 return count; 1342 } 1343 #else 1344 // On other systems, return -1 to indicate unknown. 1345 static int computeHostNumPhysicalCores() { return -1; } 1346 #endif 1347 1348 int sys::getHostNumPhysicalCores() { 1349 static int NumCores = computeHostNumPhysicalCores(); 1350 return NumCores; 1351 } 1352 1353 #if defined(__i386__) || defined(_M_IX86) || \ 1354 defined(__x86_64__) || defined(_M_X64) 1355 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1356 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1357 unsigned MaxLevel; 1358 union { 1359 unsigned u[3]; 1360 char c[12]; 1361 } text; 1362 1363 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1364 MaxLevel < 1) 1365 return false; 1366 1367 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1368 1369 Features["cmov"] = (EDX >> 15) & 1; 1370 Features["mmx"] = (EDX >> 23) & 1; 1371 Features["sse"] = (EDX >> 25) & 1; 1372 Features["sse2"] = (EDX >> 26) & 1; 1373 Features["sse3"] = (ECX >> 0) & 1; 1374 Features["ssse3"] = (ECX >> 9) & 1; 1375 Features["sse4.1"] = (ECX >> 19) & 1; 1376 Features["sse4.2"] = (ECX >> 20) & 1; 1377 1378 Features["pclmul"] = (ECX >> 1) & 1; 1379 Features["cx16"] = (ECX >> 13) & 1; 1380 Features["movbe"] = (ECX >> 22) & 1; 1381 Features["popcnt"] = (ECX >> 23) & 1; 1382 Features["aes"] = (ECX >> 25) & 1; 1383 Features["rdrnd"] = (ECX >> 30) & 1; 1384 1385 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1386 // indicates that the AVX registers will be saved and restored on context 1387 // switch, then we have full AVX support. 1388 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1389 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1390 Features["avx"] = HasAVXSave; 1391 Features["fma"] = HasAVXSave && (ECX >> 12) & 1; 1392 Features["f16c"] = HasAVXSave && (ECX >> 29) & 1; 1393 1394 // Only enable XSAVE if OS has enabled support for saving YMM state. 1395 Features["xsave"] = HasAVXSave && (ECX >> 26) & 1; 1396 1397 // AVX512 requires additional context to be saved by the OS. 1398 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1399 1400 unsigned MaxExtLevel; 1401 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1402 1403 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1404 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1405 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1406 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1407 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1408 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1409 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1410 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1411 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1412 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1413 1414 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1415 !getX86CpuIDAndInfoEx(0x80000008,0x0, &EAX, &EBX, &ECX, &EDX); 1416 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1417 1418 bool HasLeaf7 = 1419 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1420 1421 // AVX2 is only supported if we have the OS save support from AVX. 1422 Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1); 1423 1424 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1425 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1426 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1427 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1428 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1429 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1430 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1431 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1432 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1433 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1434 1435 // AVX512 is only supported if the OS supports the context save for it. 1436 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1437 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1438 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1439 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1440 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1441 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1442 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1443 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1444 1445 Features["prefetchwt1"] = HasLeaf7 && (ECX & 1); 1446 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1447 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1448 // Enable protection keys 1449 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1450 1451 bool HasLeafD = MaxLevel >= 0xd && 1452 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1453 1454 // Only enable XSAVE if OS has enabled support for saving YMM state. 1455 Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1); 1456 Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1); 1457 Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1); 1458 1459 return true; 1460 } 1461 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1462 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1463 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1464 if (!P) 1465 return false; 1466 1467 SmallVector<StringRef, 32> Lines; 1468 P->getBuffer().split(Lines, "\n"); 1469 1470 SmallVector<StringRef, 32> CPUFeatures; 1471 1472 // Look for the CPU features. 1473 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1474 if (Lines[I].startswith("Features")) { 1475 Lines[I].split(CPUFeatures, ' '); 1476 break; 1477 } 1478 1479 #if defined(__aarch64__) 1480 // Keep track of which crypto features we have seen 1481 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1482 uint32_t crypto = 0; 1483 #endif 1484 1485 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1486 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1487 #if defined(__aarch64__) 1488 .Case("asimd", "neon") 1489 .Case("fp", "fp-armv8") 1490 .Case("crc32", "crc") 1491 #else 1492 .Case("half", "fp16") 1493 .Case("neon", "neon") 1494 .Case("vfpv3", "vfp3") 1495 .Case("vfpv3d16", "d16") 1496 .Case("vfpv4", "vfp4") 1497 .Case("idiva", "hwdiv-arm") 1498 .Case("idivt", "hwdiv") 1499 #endif 1500 .Default(""); 1501 1502 #if defined(__aarch64__) 1503 // We need to check crypto separately since we need all of the crypto 1504 // extensions to enable the subtarget feature 1505 if (CPUFeatures[I] == "aes") 1506 crypto |= CAP_AES; 1507 else if (CPUFeatures[I] == "pmull") 1508 crypto |= CAP_PMULL; 1509 else if (CPUFeatures[I] == "sha1") 1510 crypto |= CAP_SHA1; 1511 else if (CPUFeatures[I] == "sha2") 1512 crypto |= CAP_SHA2; 1513 #endif 1514 1515 if (LLVMFeatureStr != "") 1516 Features[LLVMFeatureStr] = true; 1517 } 1518 1519 #if defined(__aarch64__) 1520 // If we have all crypto bits we can add the feature 1521 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1522 Features["crypto"] = true; 1523 #endif 1524 1525 return true; 1526 } 1527 #else 1528 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1529 #endif 1530 1531 std::string sys::getProcessTriple() { 1532 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1533 Triple PT(Triple::normalize(TargetTripleString)); 1534 1535 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1536 PT = PT.get64BitArchVariant(); 1537 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1538 PT = PT.get32BitArchVariant(); 1539 1540 return PT.str(); 1541 } 1542