1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the operating system Host concept. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Support/Host.h" 15 #include "llvm/ADT/SmallSet.h" 16 #include "llvm/ADT/SmallVector.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include <assert.h> 26 #include <string.h> 27 28 // Include the platform-specific parts of this class. 29 #ifdef LLVM_ON_UNIX 30 #include "Unix/Host.inc" 31 #endif 32 #ifdef LLVM_ON_WIN32 33 #include "Windows/Host.inc" 34 #endif 35 #ifdef _MSC_VER 36 #include <intrin.h> 37 #endif 38 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 39 #include <mach/host_info.h> 40 #include <mach/mach.h> 41 #include <mach/mach_host.h> 42 #include <mach/machine.h> 43 #endif 44 45 #define DEBUG_TYPE "host-detection" 46 47 //===----------------------------------------------------------------------===// 48 // 49 // Implementations of the CPU detection routines 50 // 51 //===----------------------------------------------------------------------===// 52 53 using namespace llvm; 54 55 static std::unique_ptr<llvm::MemoryBuffer> 56 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 57 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 58 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 59 if (std::error_code EC = Text.getError()) { 60 llvm::errs() << "Can't read " 61 << "/proc/cpuinfo: " << EC.message() << "\n"; 62 return nullptr; 63 } 64 return std::move(*Text); 65 } 66 67 StringRef sys::detail::getHostCPUNameForPowerPC( 68 const StringRef &ProcCpuinfoContent) { 69 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 70 // and so we must use an operating-system interface to determine the current 71 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 72 const char *generic = "generic"; 73 74 // The cpu line is second (after the 'processor: 0' line), so if this 75 // buffer is too small then something has changed (or is wrong). 76 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 77 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 78 79 StringRef::const_iterator CIP = CPUInfoStart; 80 81 StringRef::const_iterator CPUStart = 0; 82 size_t CPULen = 0; 83 84 // We need to find the first line which starts with cpu, spaces, and a colon. 85 // After the colon, there may be some additional spaces and then the cpu type. 86 while (CIP < CPUInfoEnd && CPUStart == 0) { 87 if (CIP < CPUInfoEnd && *CIP == '\n') 88 ++CIP; 89 90 if (CIP < CPUInfoEnd && *CIP == 'c') { 91 ++CIP; 92 if (CIP < CPUInfoEnd && *CIP == 'p') { 93 ++CIP; 94 if (CIP < CPUInfoEnd && *CIP == 'u') { 95 ++CIP; 96 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 97 ++CIP; 98 99 if (CIP < CPUInfoEnd && *CIP == ':') { 100 ++CIP; 101 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 102 ++CIP; 103 104 if (CIP < CPUInfoEnd) { 105 CPUStart = CIP; 106 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 107 *CIP != ',' && *CIP != '\n')) 108 ++CIP; 109 CPULen = CIP - CPUStart; 110 } 111 } 112 } 113 } 114 } 115 116 if (CPUStart == 0) 117 while (CIP < CPUInfoEnd && *CIP != '\n') 118 ++CIP; 119 } 120 121 if (CPUStart == 0) 122 return generic; 123 124 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 125 .Case("604e", "604e") 126 .Case("604", "604") 127 .Case("7400", "7400") 128 .Case("7410", "7400") 129 .Case("7447", "7400") 130 .Case("7455", "7450") 131 .Case("G4", "g4") 132 .Case("POWER4", "970") 133 .Case("PPC970FX", "970") 134 .Case("PPC970MP", "970") 135 .Case("G5", "g5") 136 .Case("POWER5", "g5") 137 .Case("A2", "a2") 138 .Case("POWER6", "pwr6") 139 .Case("POWER7", "pwr7") 140 .Case("POWER8", "pwr8") 141 .Case("POWER8E", "pwr8") 142 .Case("POWER8NVL", "pwr8") 143 .Case("POWER9", "pwr9") 144 .Default(generic); 145 } 146 147 StringRef sys::detail::getHostCPUNameForARM( 148 const StringRef &ProcCpuinfoContent) { 149 // The cpuid register on arm is not accessible from user space. On Linux, 150 // it is exposed through the /proc/cpuinfo file. 151 152 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 153 // in all cases. 154 SmallVector<StringRef, 32> Lines; 155 ProcCpuinfoContent.split(Lines, "\n"); 156 157 // Look for the CPU implementer line. 158 StringRef Implementer; 159 StringRef Hardware; 160 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 161 if (Lines[I].startswith("CPU implementer")) 162 Implementer = Lines[I].substr(15).ltrim("\t :"); 163 if (Lines[I].startswith("Hardware")) 164 Hardware = Lines[I].substr(8).ltrim("\t :"); 165 } 166 167 if (Implementer == "0x41") { // ARM Ltd. 168 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 169 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 170 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 171 return "cortex-a53"; 172 173 174 // Look for the CPU part line. 175 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 176 if (Lines[I].startswith("CPU part")) 177 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 178 // values correspond to the "Part number" in the CP15/c0 register. The 179 // contents are specified in the various processor manuals. 180 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 181 .Case("0x926", "arm926ej-s") 182 .Case("0xb02", "mpcore") 183 .Case("0xb36", "arm1136j-s") 184 .Case("0xb56", "arm1156t2-s") 185 .Case("0xb76", "arm1176jz-s") 186 .Case("0xc08", "cortex-a8") 187 .Case("0xc09", "cortex-a9") 188 .Case("0xc0f", "cortex-a15") 189 .Case("0xc20", "cortex-m0") 190 .Case("0xc23", "cortex-m3") 191 .Case("0xc24", "cortex-m4") 192 .Case("0xd04", "cortex-a35") 193 .Case("0xd03", "cortex-a53") 194 .Case("0xd07", "cortex-a57") 195 .Case("0xd08", "cortex-a72") 196 .Case("0xd09", "cortex-a73") 197 .Default("generic"); 198 } 199 200 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 201 // Look for the CPU part line. 202 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 203 if (Lines[I].startswith("CPU part")) 204 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 205 // values correspond to the "Part number" in the CP15/c0 register. The 206 // contents are specified in the various processor manuals. 207 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 208 .Case("0x06f", "krait") // APQ8064 209 .Case("0x201", "kryo") 210 .Case("0x205", "kryo") 211 .Default("generic"); 212 213 return "generic"; 214 } 215 216 StringRef sys::detail::getHostCPUNameForS390x( 217 const StringRef &ProcCpuinfoContent) { 218 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 219 220 // The "processor 0:" line comes after a fair amount of other information, 221 // including a cache breakdown, but this should be plenty. 222 SmallVector<StringRef, 32> Lines; 223 ProcCpuinfoContent.split(Lines, "\n"); 224 225 // Look for the CPU features. 226 SmallVector<StringRef, 32> CPUFeatures; 227 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 228 if (Lines[I].startswith("features")) { 229 size_t Pos = Lines[I].find(":"); 230 if (Pos != StringRef::npos) { 231 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 232 break; 233 } 234 } 235 236 // We need to check for the presence of vector support independently of 237 // the machine type, since we may only use the vector register set when 238 // supported by the kernel (and hypervisor). 239 bool HaveVectorSupport = false; 240 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 241 if (CPUFeatures[I] == "vx") 242 HaveVectorSupport = true; 243 } 244 245 // Now check the processor machine type. 246 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 247 if (Lines[I].startswith("processor ")) { 248 size_t Pos = Lines[I].find("machine = "); 249 if (Pos != StringRef::npos) { 250 Pos += sizeof("machine = ") - 1; 251 unsigned int Id; 252 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 253 if (Id >= 2964 && HaveVectorSupport) 254 return "z13"; 255 if (Id >= 2827) 256 return "zEC12"; 257 if (Id >= 2817) 258 return "z196"; 259 } 260 } 261 break; 262 } 263 } 264 265 return "generic"; 266 } 267 268 #if defined(__i386__) || defined(_M_IX86) || \ 269 defined(__x86_64__) || defined(_M_X64) 270 271 enum VendorSignatures { 272 SIG_INTEL = 0x756e6547 /* Genu */, 273 SIG_AMD = 0x68747541 /* Auth */ 274 }; 275 276 enum ProcessorVendors { 277 VENDOR_INTEL = 1, 278 VENDOR_AMD, 279 VENDOR_OTHER, 280 VENDOR_MAX 281 }; 282 283 enum ProcessorTypes { 284 INTEL_ATOM = 1, 285 INTEL_CORE2, 286 INTEL_COREI7, 287 AMDFAM10H, 288 AMDFAM15H, 289 INTEL_i386, 290 INTEL_i486, 291 INTEL_PENTIUM, 292 INTEL_PENTIUM_PRO, 293 INTEL_PENTIUM_II, 294 INTEL_PENTIUM_III, 295 INTEL_PENTIUM_IV, 296 INTEL_PENTIUM_M, 297 INTEL_CORE_DUO, 298 INTEL_XEONPHI, 299 INTEL_X86_64, 300 INTEL_NOCONA, 301 INTEL_PRESCOTT, 302 AMD_i486, 303 AMDPENTIUM, 304 AMDATHLON, 305 AMDFAM14H, 306 AMDFAM16H, 307 AMDFAM17H, 308 CPU_TYPE_MAX 309 }; 310 311 enum ProcessorSubtypes { 312 INTEL_COREI7_NEHALEM = 1, 313 INTEL_COREI7_WESTMERE, 314 INTEL_COREI7_SANDYBRIDGE, 315 AMDFAM10H_BARCELONA, 316 AMDFAM10H_SHANGHAI, 317 AMDFAM10H_ISTANBUL, 318 AMDFAM15H_BDVER1, 319 AMDFAM15H_BDVER2, 320 INTEL_PENTIUM_MMX, 321 INTEL_CORE2_65, 322 INTEL_CORE2_45, 323 INTEL_COREI7_IVYBRIDGE, 324 INTEL_COREI7_HASWELL, 325 INTEL_COREI7_BROADWELL, 326 INTEL_COREI7_SKYLAKE, 327 INTEL_COREI7_SKYLAKE_AVX512, 328 INTEL_ATOM_BONNELL, 329 INTEL_ATOM_SILVERMONT, 330 INTEL_ATOM_GOLDMONT, 331 INTEL_KNIGHTS_LANDING, 332 AMDPENTIUM_K6, 333 AMDPENTIUM_K62, 334 AMDPENTIUM_K63, 335 AMDPENTIUM_GEODE, 336 AMDATHLON_TBIRD, 337 AMDATHLON_MP, 338 AMDATHLON_XP, 339 AMDATHLON_K8SSE3, 340 AMDATHLON_OPTERON, 341 AMDATHLON_FX, 342 AMDATHLON_64, 343 AMD_BTVER1, 344 AMD_BTVER2, 345 AMDFAM15H_BDVER3, 346 AMDFAM15H_BDVER4, 347 AMDFAM17H_ZNVER1, 348 CPU_SUBTYPE_MAX 349 }; 350 351 enum ProcessorFeatures { 352 FEATURE_CMOV = 0, 353 FEATURE_MMX, 354 FEATURE_POPCNT, 355 FEATURE_SSE, 356 FEATURE_SSE2, 357 FEATURE_SSE3, 358 FEATURE_SSSE3, 359 FEATURE_SSE4_1, 360 FEATURE_SSE4_2, 361 FEATURE_AVX, 362 FEATURE_AVX2, 363 FEATURE_AVX512, 364 FEATURE_AVX512SAVE, 365 FEATURE_MOVBE, 366 FEATURE_ADX, 367 FEATURE_EM64T 368 }; 369 370 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 371 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 372 // support. Consequently, for i386, the presence of CPUID is checked first 373 // via the corresponding eflags bit. 374 // Removal of cpuid.h header motivated by PR30384 375 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 376 // or test-suite, but are used in external projects e.g. libstdcxx 377 static bool isCpuIdSupported() { 378 #if defined(__GNUC__) || defined(__clang__) 379 #if defined(__i386__) 380 int __cpuid_supported; 381 __asm__(" pushfl\n" 382 " popl %%eax\n" 383 " movl %%eax,%%ecx\n" 384 " xorl $0x00200000,%%eax\n" 385 " pushl %%eax\n" 386 " popfl\n" 387 " pushfl\n" 388 " popl %%eax\n" 389 " movl $0,%0\n" 390 " cmpl %%eax,%%ecx\n" 391 " je 1f\n" 392 " movl $1,%0\n" 393 "1:" 394 : "=r"(__cpuid_supported) 395 : 396 : "eax", "ecx"); 397 if (!__cpuid_supported) 398 return false; 399 #endif 400 return true; 401 #endif 402 return true; 403 } 404 405 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 406 /// the specified arguments. If we can't run cpuid on the host, return true. 407 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 408 unsigned *rECX, unsigned *rEDX) { 409 #if defined(__GNUC__) || defined(__clang__) || defined(_MSC_VER) 410 #if defined(__GNUC__) || defined(__clang__) 411 #if defined(__x86_64__) 412 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 413 // FIXME: should we save this for Clang? 414 __asm__("movq\t%%rbx, %%rsi\n\t" 415 "cpuid\n\t" 416 "xchgq\t%%rbx, %%rsi\n\t" 417 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 418 : "a"(value)); 419 #elif defined(__i386__) 420 __asm__("movl\t%%ebx, %%esi\n\t" 421 "cpuid\n\t" 422 "xchgl\t%%ebx, %%esi\n\t" 423 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 424 : "a"(value)); 425 #else 426 assert(0 && "This method is defined only for x86."); 427 #endif 428 #elif defined(_MSC_VER) 429 // The MSVC intrinsic is portable across x86 and x64. 430 int registers[4]; 431 __cpuid(registers, value); 432 *rEAX = registers[0]; 433 *rEBX = registers[1]; 434 *rECX = registers[2]; 435 *rEDX = registers[3]; 436 #endif 437 return false; 438 #else 439 return true; 440 #endif 441 } 442 443 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 444 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 445 /// return true. 446 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 447 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 448 unsigned *rEDX) { 449 #if defined(__GNUC__) || defined(__clang__) || defined(_MSC_VER) 450 #if defined(__x86_64__) || defined(_M_X64) 451 #if defined(__GNUC__) || defined(__clang__) 452 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. 453 // FIXME: should we save this for Clang? 454 __asm__("movq\t%%rbx, %%rsi\n\t" 455 "cpuid\n\t" 456 "xchgq\t%%rbx, %%rsi\n\t" 457 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 458 : "a"(value), "c"(subleaf)); 459 #elif defined(_MSC_VER) 460 int registers[4]; 461 __cpuidex(registers, value, subleaf); 462 *rEAX = registers[0]; 463 *rEBX = registers[1]; 464 *rECX = registers[2]; 465 *rEDX = registers[3]; 466 #endif 467 #elif defined(__i386__) || defined(_M_IX86) 468 #if defined(__GNUC__) || defined(__clang__) 469 __asm__("movl\t%%ebx, %%esi\n\t" 470 "cpuid\n\t" 471 "xchgl\t%%ebx, %%esi\n\t" 472 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 473 : "a"(value), "c"(subleaf)); 474 #elif defined(_MSC_VER) 475 __asm { 476 mov eax,value 477 mov ecx,subleaf 478 cpuid 479 mov esi,rEAX 480 mov dword ptr [esi],eax 481 mov esi,rEBX 482 mov dword ptr [esi],ebx 483 mov esi,rECX 484 mov dword ptr [esi],ecx 485 mov esi,rEDX 486 mov dword ptr [esi],edx 487 } 488 #endif 489 #else 490 assert(0 && "This method is defined only for x86."); 491 #endif 492 return false; 493 #else 494 return true; 495 #endif 496 } 497 498 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 499 #if defined(__GNUC__) || defined(__clang__) 500 // Check xgetbv; this uses a .byte sequence instead of the instruction 501 // directly because older assemblers do not include support for xgetbv and 502 // there is no easy way to conditionally compile based on the assembler used. 503 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 504 return false; 505 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 506 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 507 *rEAX = Result; 508 *rEDX = Result >> 32; 509 return false; 510 #else 511 return true; 512 #endif 513 } 514 515 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 516 unsigned *Model) { 517 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 518 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 519 if (*Family == 6 || *Family == 0xf) { 520 if (*Family == 0xf) 521 // Examine extended family ID if family ID is F. 522 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 523 // Examine extended model ID if family ID is 6 or F. 524 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 525 } 526 } 527 528 static void 529 getIntelProcessorTypeAndSubtype(unsigned int Family, unsigned int Model, 530 unsigned int Brand_id, unsigned int Features, 531 unsigned *Type, unsigned *Subtype) { 532 if (Brand_id != 0) 533 return; 534 switch (Family) { 535 case 3: 536 *Type = INTEL_i386; 537 break; 538 case 4: 539 switch (Model) { 540 case 0: // Intel486 DX processors 541 case 1: // Intel486 DX processors 542 case 2: // Intel486 SX processors 543 case 3: // Intel487 processors, IntelDX2 OverDrive processors, 544 // IntelDX2 processors 545 case 4: // Intel486 SL processor 546 case 5: // IntelSX2 processors 547 case 7: // Write-Back Enhanced IntelDX2 processors 548 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors 549 default: 550 *Type = INTEL_i486; 551 break; 552 } 553 break; 554 case 5: 555 switch (Model) { 556 case 1: // Pentium OverDrive processor for Pentium processor (60, 66), 557 // Pentium processors (60, 66) 558 case 2: // Pentium OverDrive processor for Pentium processor (75, 90, 559 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133, 560 // 150, 166, 200) 561 case 3: // Pentium OverDrive processors for Intel486 processor-based 562 // systems 563 *Type = INTEL_PENTIUM; 564 break; 565 case 4: // Pentium OverDrive processor with MMX technology for Pentium 566 // processor (75, 90, 100, 120, 133), Pentium processor with 567 // MMX technology (166, 200) 568 *Type = INTEL_PENTIUM; 569 *Subtype = INTEL_PENTIUM_MMX; 570 break; 571 default: 572 *Type = INTEL_PENTIUM; 573 break; 574 } 575 break; 576 case 6: 577 switch (Model) { 578 case 0x01: // Pentium Pro processor 579 *Type = INTEL_PENTIUM_PRO; 580 break; 581 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 582 // model 03 583 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 584 // model 05, and Intel Celeron processor, model 05 585 case 0x06: // Celeron processor, model 06 586 *Type = INTEL_PENTIUM_II; 587 break; 588 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 589 // processor, model 07 590 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 591 // model 08, and Celeron processor, model 08 592 case 0x0a: // Pentium III Xeon processor, model 0Ah 593 case 0x0b: // Pentium III processor, model 0Bh 594 *Type = INTEL_PENTIUM_III; 595 break; 596 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 597 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 598 // 0Dh. All processors are manufactured using the 90 nm process. 599 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 600 // Integrated Processor with Intel QuickAssist Technology 601 *Type = INTEL_PENTIUM_M; 602 break; 603 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 604 // 0Eh. All processors are manufactured using the 65 nm process. 605 *Type = INTEL_CORE_DUO; 606 break; // yonah 607 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 608 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 609 // mobile processor, Intel Core 2 Extreme processor, Intel 610 // Pentium Dual-Core processor, Intel Xeon processor, model 611 // 0Fh. All processors are manufactured using the 65 nm process. 612 case 0x16: // Intel Celeron processor model 16h. All processors are 613 // manufactured using the 65 nm process 614 *Type = INTEL_CORE2; // "core2" 615 *Subtype = INTEL_CORE2_65; 616 break; 617 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 618 // 17h. All processors are manufactured using the 45 nm process. 619 // 620 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 621 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 622 // the 45 nm process. 623 *Type = INTEL_CORE2; // "penryn" 624 *Subtype = INTEL_CORE2_45; 625 break; 626 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 627 // processors are manufactured using the 45 nm process. 628 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 629 // As found in a Summer 2010 model iMac. 630 case 0x1f: 631 case 0x2e: // Nehalem EX 632 *Type = INTEL_COREI7; // "nehalem" 633 *Subtype = INTEL_COREI7_NEHALEM; 634 break; 635 case 0x25: // Intel Core i7, laptop version. 636 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 637 // processors are manufactured using the 32 nm process. 638 case 0x2f: // Westmere EX 639 *Type = INTEL_COREI7; // "westmere" 640 *Subtype = INTEL_COREI7_WESTMERE; 641 break; 642 case 0x2a: // Intel Core i7 processor. All processors are manufactured 643 // using the 32 nm process. 644 case 0x2d: 645 *Type = INTEL_COREI7; //"sandybridge" 646 *Subtype = INTEL_COREI7_SANDYBRIDGE; 647 break; 648 case 0x3a: 649 case 0x3e: // Ivy Bridge EP 650 *Type = INTEL_COREI7; // "ivybridge" 651 *Subtype = INTEL_COREI7_IVYBRIDGE; 652 break; 653 654 // Haswell: 655 case 0x3c: 656 case 0x3f: 657 case 0x45: 658 case 0x46: 659 *Type = INTEL_COREI7; // "haswell" 660 *Subtype = INTEL_COREI7_HASWELL; 661 break; 662 663 // Broadwell: 664 case 0x3d: 665 case 0x47: 666 case 0x4f: 667 case 0x56: 668 *Type = INTEL_COREI7; // "broadwell" 669 *Subtype = INTEL_COREI7_BROADWELL; 670 break; 671 672 // Skylake: 673 case 0x4e: // Skylake mobile 674 case 0x5e: // Skylake desktop 675 case 0x8e: // Kaby Lake mobile 676 case 0x9e: // Kaby Lake desktop 677 *Type = INTEL_COREI7; // "skylake" 678 *Subtype = INTEL_COREI7_SKYLAKE; 679 break; 680 681 // Skylake Xeon: 682 case 0x55: 683 *Type = INTEL_COREI7; 684 // Check that we really have AVX512 685 if (Features & (1 << FEATURE_AVX512)) { 686 *Subtype = INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 687 } else { 688 *Subtype = INTEL_COREI7_SKYLAKE; // "skylake" 689 } 690 break; 691 692 case 0x1c: // Most 45 nm Intel Atom processors 693 case 0x26: // 45 nm Atom Lincroft 694 case 0x27: // 32 nm Atom Medfield 695 case 0x35: // 32 nm Atom Midview 696 case 0x36: // 32 nm Atom Midview 697 *Type = INTEL_ATOM; 698 *Subtype = INTEL_ATOM_BONNELL; 699 break; // "bonnell" 700 701 // Atom Silvermont codes from the Intel software optimization guide. 702 case 0x37: 703 case 0x4a: 704 case 0x4d: 705 case 0x5a: 706 case 0x5d: 707 case 0x4c: // really airmont 708 *Type = INTEL_ATOM; 709 *Subtype = INTEL_ATOM_SILVERMONT; 710 break; // "silvermont" 711 // Goldmont: 712 case 0x5c: 713 case 0x5f: 714 *Type = INTEL_ATOM; 715 *Subtype = INTEL_ATOM_GOLDMONT; 716 break; // "goldmont" 717 case 0x57: 718 *Type = INTEL_XEONPHI; // knl 719 *Subtype = INTEL_KNIGHTS_LANDING; 720 break; 721 722 default: // Unknown family 6 CPU, try to guess. 723 if (Features & (1 << FEATURE_AVX512)) { 724 *Type = INTEL_XEONPHI; // knl 725 *Subtype = INTEL_KNIGHTS_LANDING; 726 break; 727 } 728 if (Features & (1 << FEATURE_ADX)) { 729 *Type = INTEL_COREI7; 730 *Subtype = INTEL_COREI7_BROADWELL; 731 break; 732 } 733 if (Features & (1 << FEATURE_AVX2)) { 734 *Type = INTEL_COREI7; 735 *Subtype = INTEL_COREI7_HASWELL; 736 break; 737 } 738 if (Features & (1 << FEATURE_AVX)) { 739 *Type = INTEL_COREI7; 740 *Subtype = INTEL_COREI7_SANDYBRIDGE; 741 break; 742 } 743 if (Features & (1 << FEATURE_SSE4_2)) { 744 if (Features & (1 << FEATURE_MOVBE)) { 745 *Type = INTEL_ATOM; 746 *Subtype = INTEL_ATOM_SILVERMONT; 747 } else { 748 *Type = INTEL_COREI7; 749 *Subtype = INTEL_COREI7_NEHALEM; 750 } 751 break; 752 } 753 if (Features & (1 << FEATURE_SSE4_1)) { 754 *Type = INTEL_CORE2; // "penryn" 755 *Subtype = INTEL_CORE2_45; 756 break; 757 } 758 if (Features & (1 << FEATURE_SSSE3)) { 759 if (Features & (1 << FEATURE_MOVBE)) { 760 *Type = INTEL_ATOM; 761 *Subtype = INTEL_ATOM_BONNELL; // "bonnell" 762 } else { 763 *Type = INTEL_CORE2; // "core2" 764 *Subtype = INTEL_CORE2_65; 765 } 766 break; 767 } 768 if (Features & (1 << FEATURE_EM64T)) { 769 *Type = INTEL_X86_64; 770 break; // x86-64 771 } 772 if (Features & (1 << FEATURE_SSE2)) { 773 *Type = INTEL_PENTIUM_M; 774 break; 775 } 776 if (Features & (1 << FEATURE_SSE)) { 777 *Type = INTEL_PENTIUM_III; 778 break; 779 } 780 if (Features & (1 << FEATURE_MMX)) { 781 *Type = INTEL_PENTIUM_II; 782 break; 783 } 784 *Type = INTEL_PENTIUM_PRO; 785 break; 786 } 787 break; 788 case 15: { 789 switch (Model) { 790 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are 791 // model 00h and manufactured using the 0.18 micron process. 792 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon 793 // processor MP, and Intel Celeron processor. All processors are 794 // model 01h and manufactured using the 0.18 micron process. 795 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M, 796 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron 797 // processor, and Mobile Intel Celeron processor. All processors 798 // are model 02h and manufactured using the 0.13 micron process. 799 *Type = 800 ((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV); 801 break; 802 803 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D 804 // processor. All processors are model 03h and manufactured using 805 // the 90 nm process. 806 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition, 807 // Pentium D processor, Intel Xeon processor, Intel Xeon 808 // processor MP, Intel Celeron D processor. All processors are 809 // model 04h and manufactured using the 90 nm process. 810 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor 811 // Extreme Edition, Intel Xeon processor, Intel Xeon processor 812 // MP, Intel Celeron D processor. All processors are model 06h 813 // and manufactured using the 65 nm process. 814 *Type = 815 ((Features & (1 << FEATURE_EM64T)) ? INTEL_NOCONA : INTEL_PRESCOTT); 816 break; 817 818 default: 819 *Type = 820 ((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV); 821 break; 822 } 823 break; 824 } 825 default: 826 break; /*"generic"*/ 827 } 828 } 829 830 static void getAMDProcessorTypeAndSubtype(unsigned int Family, 831 unsigned int Model, 832 unsigned int Features, 833 unsigned *Type, 834 unsigned *Subtype) { 835 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 836 // appears to be no way to generate the wide variety of AMD-specific targets 837 // from the information returned from CPUID. 838 switch (Family) { 839 case 4: 840 *Type = AMD_i486; 841 break; 842 case 5: 843 *Type = AMDPENTIUM; 844 switch (Model) { 845 case 6: 846 case 7: 847 *Subtype = AMDPENTIUM_K6; 848 break; // "k6" 849 case 8: 850 *Subtype = AMDPENTIUM_K62; 851 break; // "k6-2" 852 case 9: 853 case 13: 854 *Subtype = AMDPENTIUM_K63; 855 break; // "k6-3" 856 case 10: 857 *Subtype = AMDPENTIUM_GEODE; 858 break; // "geode" 859 } 860 break; 861 case 6: 862 *Type = AMDATHLON; 863 switch (Model) { 864 case 4: 865 *Subtype = AMDATHLON_TBIRD; 866 break; // "athlon-tbird" 867 case 6: 868 case 7: 869 case 8: 870 *Subtype = AMDATHLON_MP; 871 break; // "athlon-mp" 872 case 10: 873 *Subtype = AMDATHLON_XP; 874 break; // "athlon-xp" 875 } 876 break; 877 case 15: 878 *Type = AMDATHLON; 879 if (Features & (1 << FEATURE_SSE3)) { 880 *Subtype = AMDATHLON_K8SSE3; 881 break; // "k8-sse3" 882 } 883 switch (Model) { 884 case 1: 885 *Subtype = AMDATHLON_OPTERON; 886 break; // "opteron" 887 case 5: 888 *Subtype = AMDATHLON_FX; 889 break; // "athlon-fx"; also opteron 890 default: 891 *Subtype = AMDATHLON_64; 892 break; // "athlon64" 893 } 894 break; 895 case 16: 896 *Type = AMDFAM10H; // "amdfam10" 897 switch (Model) { 898 case 2: 899 *Subtype = AMDFAM10H_BARCELONA; 900 break; 901 case 4: 902 *Subtype = AMDFAM10H_SHANGHAI; 903 break; 904 case 8: 905 *Subtype = AMDFAM10H_ISTANBUL; 906 break; 907 } 908 break; 909 case 20: 910 *Type = AMDFAM14H; 911 *Subtype = AMD_BTVER1; 912 break; // "btver1"; 913 case 21: 914 *Type = AMDFAM15H; 915 if (!(Features & 916 (1 << FEATURE_AVX))) { // If no AVX support, provide a sane fallback. 917 *Subtype = AMD_BTVER1; 918 break; // "btver1" 919 } 920 if (Model >= 0x50 && Model <= 0x6f) { 921 *Subtype = AMDFAM15H_BDVER4; 922 break; // "bdver4"; 50h-6Fh: Excavator 923 } 924 if (Model >= 0x30 && Model <= 0x3f) { 925 *Subtype = AMDFAM15H_BDVER3; 926 break; // "bdver3"; 30h-3Fh: Steamroller 927 } 928 if (Model >= 0x10 && Model <= 0x1f) { 929 *Subtype = AMDFAM15H_BDVER2; 930 break; // "bdver2"; 10h-1Fh: Piledriver 931 } 932 if (Model <= 0x0f) { 933 *Subtype = AMDFAM15H_BDVER1; 934 break; // "bdver1"; 00h-0Fh: Bulldozer 935 } 936 break; 937 case 22: 938 *Type = AMDFAM16H; 939 if (!(Features & 940 (1 << FEATURE_AVX))) { // If no AVX support provide a sane fallback. 941 *Subtype = AMD_BTVER1; 942 break; // "btver1"; 943 } 944 *Subtype = AMD_BTVER2; 945 break; // "btver2" 946 case 23: 947 *Type = AMDFAM17H; 948 if (Features & (1 << FEATURE_ADX)) { 949 *Subtype = AMDFAM17H_ZNVER1; 950 break; // "znver1" 951 } 952 *Subtype = AMD_BTVER1; 953 break; 954 default: 955 break; // "generic" 956 } 957 } 958 959 static unsigned getAvailableFeatures(unsigned int ECX, unsigned int EDX, 960 unsigned MaxLeaf) { 961 unsigned Features = 0; 962 unsigned int EAX, EBX; 963 Features |= (((EDX >> 23) & 1) << FEATURE_MMX); 964 Features |= (((EDX >> 25) & 1) << FEATURE_SSE); 965 Features |= (((EDX >> 26) & 1) << FEATURE_SSE2); 966 Features |= (((ECX >> 0) & 1) << FEATURE_SSE3); 967 Features |= (((ECX >> 9) & 1) << FEATURE_SSSE3); 968 Features |= (((ECX >> 19) & 1) << FEATURE_SSE4_1); 969 Features |= (((ECX >> 20) & 1) << FEATURE_SSE4_2); 970 Features |= (((ECX >> 22) & 1) << FEATURE_MOVBE); 971 972 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 973 // indicates that the AVX registers will be saved and restored on context 974 // switch, then we have full AVX support. 975 const unsigned AVXBits = (1 << 27) | (1 << 28); 976 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 977 ((EAX & 0x6) == 0x6); 978 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 979 bool HasLeaf7 = 980 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 981 bool HasADX = HasLeaf7 && ((EBX >> 19) & 1); 982 bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20); 983 bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1); 984 Features |= (HasAVX << FEATURE_AVX); 985 Features |= (HasAVX2 << FEATURE_AVX2); 986 Features |= (HasAVX512 << FEATURE_AVX512); 987 Features |= (HasAVX512Save << FEATURE_AVX512SAVE); 988 Features |= (HasADX << FEATURE_ADX); 989 990 getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 991 Features |= (((EDX >> 29) & 0x1) << FEATURE_EM64T); 992 return Features; 993 } 994 995 StringRef sys::getHostCPUName() { 996 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 997 unsigned MaxLeaf, Vendor; 998 999 #if defined(__GNUC__) || defined(__clang__) 1000 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here 1001 // and simplify it to not invoke __cpuid (like cpu_model.c in 1002 // compiler-rt/lib/builtins/cpu_model.c? 1003 // Opting for the second option. 1004 if(!isCpuIdSupported()) 1005 return "generic"; 1006 #endif 1007 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX)) 1008 return "generic"; 1009 if (getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX)) 1010 return "generic"; 1011 1012 unsigned Brand_id = EBX & 0xff; 1013 unsigned Family = 0, Model = 0; 1014 unsigned Features = 0; 1015 detectX86FamilyModel(EAX, &Family, &Model); 1016 Features = getAvailableFeatures(ECX, EDX, MaxLeaf); 1017 1018 unsigned Type; 1019 unsigned Subtype; 1020 1021 if (Vendor == SIG_INTEL) { 1022 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, &Type, 1023 &Subtype); 1024 switch (Type) { 1025 case INTEL_i386: 1026 return "i386"; 1027 case INTEL_i486: 1028 return "i486"; 1029 case INTEL_PENTIUM: 1030 if (Subtype == INTEL_PENTIUM_MMX) 1031 return "pentium-mmx"; 1032 return "pentium"; 1033 case INTEL_PENTIUM_PRO: 1034 return "pentiumpro"; 1035 case INTEL_PENTIUM_II: 1036 return "pentium2"; 1037 case INTEL_PENTIUM_III: 1038 return "pentium3"; 1039 case INTEL_PENTIUM_IV: 1040 return "pentium4"; 1041 case INTEL_PENTIUM_M: 1042 return "pentium-m"; 1043 case INTEL_CORE_DUO: 1044 return "yonah"; 1045 case INTEL_CORE2: 1046 switch (Subtype) { 1047 case INTEL_CORE2_65: 1048 return "core2"; 1049 case INTEL_CORE2_45: 1050 return "penryn"; 1051 default: 1052 return "core2"; 1053 } 1054 case INTEL_COREI7: 1055 switch (Subtype) { 1056 case INTEL_COREI7_NEHALEM: 1057 return "nehalem"; 1058 case INTEL_COREI7_WESTMERE: 1059 return "westmere"; 1060 case INTEL_COREI7_SANDYBRIDGE: 1061 return "sandybridge"; 1062 case INTEL_COREI7_IVYBRIDGE: 1063 return "ivybridge"; 1064 case INTEL_COREI7_HASWELL: 1065 return "haswell"; 1066 case INTEL_COREI7_BROADWELL: 1067 return "broadwell"; 1068 case INTEL_COREI7_SKYLAKE: 1069 return "skylake"; 1070 case INTEL_COREI7_SKYLAKE_AVX512: 1071 return "skylake-avx512"; 1072 default: 1073 return "corei7"; 1074 } 1075 case INTEL_ATOM: 1076 switch (Subtype) { 1077 case INTEL_ATOM_BONNELL: 1078 return "bonnell"; 1079 case INTEL_ATOM_GOLDMONT: 1080 return "goldmont"; 1081 case INTEL_ATOM_SILVERMONT: 1082 return "silvermont"; 1083 default: 1084 return "atom"; 1085 } 1086 case INTEL_XEONPHI: 1087 return "knl"; /*update for more variants added*/ 1088 case INTEL_X86_64: 1089 return "x86-64"; 1090 case INTEL_NOCONA: 1091 return "nocona"; 1092 case INTEL_PRESCOTT: 1093 return "prescott"; 1094 default: 1095 return "generic"; 1096 } 1097 } else if (Vendor == SIG_AMD) { 1098 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1099 switch (Type) { 1100 case AMD_i486: 1101 return "i486"; 1102 case AMDPENTIUM: 1103 switch (Subtype) { 1104 case AMDPENTIUM_K6: 1105 return "k6"; 1106 case AMDPENTIUM_K62: 1107 return "k6-2"; 1108 case AMDPENTIUM_K63: 1109 return "k6-3"; 1110 case AMDPENTIUM_GEODE: 1111 return "geode"; 1112 default: 1113 return "pentium"; 1114 } 1115 case AMDATHLON: 1116 switch (Subtype) { 1117 case AMDATHLON_TBIRD: 1118 return "athlon-tbird"; 1119 case AMDATHLON_MP: 1120 return "athlon-mp"; 1121 case AMDATHLON_XP: 1122 return "athlon-xp"; 1123 case AMDATHLON_K8SSE3: 1124 return "k8-sse3"; 1125 case AMDATHLON_OPTERON: 1126 return "opteron"; 1127 case AMDATHLON_FX: 1128 return "athlon-fx"; 1129 case AMDATHLON_64: 1130 return "athlon64"; 1131 default: 1132 return "athlon"; 1133 } 1134 case AMDFAM10H: 1135 if(Subtype == AMDFAM10H_BARCELONA) 1136 return "barcelona"; 1137 return "amdfam10"; 1138 case AMDFAM14H: 1139 return "btver1"; 1140 case AMDFAM15H: 1141 switch (Subtype) { 1142 case AMDFAM15H_BDVER1: 1143 return "bdver1"; 1144 case AMDFAM15H_BDVER2: 1145 return "bdver2"; 1146 case AMDFAM15H_BDVER3: 1147 return "bdver3"; 1148 case AMDFAM15H_BDVER4: 1149 return "bdver4"; 1150 case AMD_BTVER1: 1151 return "btver1"; 1152 default: 1153 return "amdfam15"; 1154 } 1155 case AMDFAM16H: 1156 switch (Subtype) { 1157 case AMD_BTVER1: 1158 return "btver1"; 1159 case AMD_BTVER2: 1160 return "btver2"; 1161 default: 1162 return "amdfam16"; 1163 } 1164 case AMDFAM17H: 1165 switch (Subtype) { 1166 case AMD_BTVER1: 1167 return "btver1"; 1168 case AMDFAM17H_ZNVER1: 1169 return "znver1"; 1170 default: 1171 return "amdfam17"; 1172 } 1173 default: 1174 return "generic"; 1175 } 1176 } 1177 return "generic"; 1178 } 1179 1180 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1181 StringRef sys::getHostCPUName() { 1182 host_basic_info_data_t hostInfo; 1183 mach_msg_type_number_t infoCount; 1184 1185 infoCount = HOST_BASIC_INFO_COUNT; 1186 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo, 1187 &infoCount); 1188 1189 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1190 return "generic"; 1191 1192 switch (hostInfo.cpu_subtype) { 1193 case CPU_SUBTYPE_POWERPC_601: 1194 return "601"; 1195 case CPU_SUBTYPE_POWERPC_602: 1196 return "602"; 1197 case CPU_SUBTYPE_POWERPC_603: 1198 return "603"; 1199 case CPU_SUBTYPE_POWERPC_603e: 1200 return "603e"; 1201 case CPU_SUBTYPE_POWERPC_603ev: 1202 return "603ev"; 1203 case CPU_SUBTYPE_POWERPC_604: 1204 return "604"; 1205 case CPU_SUBTYPE_POWERPC_604e: 1206 return "604e"; 1207 case CPU_SUBTYPE_POWERPC_620: 1208 return "620"; 1209 case CPU_SUBTYPE_POWERPC_750: 1210 return "750"; 1211 case CPU_SUBTYPE_POWERPC_7400: 1212 return "7400"; 1213 case CPU_SUBTYPE_POWERPC_7450: 1214 return "7450"; 1215 case CPU_SUBTYPE_POWERPC_970: 1216 return "970"; 1217 default:; 1218 } 1219 1220 return "generic"; 1221 } 1222 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1223 StringRef sys::getHostCPUName() { 1224 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1225 const StringRef& Content = P ? P->getBuffer() : ""; 1226 return detail::getHostCPUNameForPowerPC(Content); 1227 } 1228 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1229 StringRef sys::getHostCPUName() { 1230 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1231 const StringRef& Content = P ? P->getBuffer() : ""; 1232 return detail::getHostCPUNameForARM(Content); 1233 } 1234 #elif defined(__linux__) && defined(__s390x__) 1235 StringRef sys::getHostCPUName() { 1236 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1237 const StringRef& Content = P ? P->getBuffer() : ""; 1238 return detail::getHostCPUNameForS390x(Content); 1239 } 1240 #else 1241 StringRef sys::getHostCPUName() { return "generic"; } 1242 #endif 1243 1244 #if defined(__linux__) && defined(__x86_64__) 1245 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1246 // using the number of unique physical/core id pairs. The following 1247 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1248 static int computeHostNumPhysicalCores() { 1249 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1250 // mmapped because it appears to have 0 size. 1251 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1252 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1253 if (std::error_code EC = Text.getError()) { 1254 llvm::errs() << "Can't read " 1255 << "/proc/cpuinfo: " << EC.message() << "\n"; 1256 return -1; 1257 } 1258 SmallVector<StringRef, 8> strs; 1259 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1260 /*KeepEmpty=*/false); 1261 int CurPhysicalId = -1; 1262 int CurCoreId = -1; 1263 SmallSet<std::pair<int, int>, 32> UniqueItems; 1264 for (auto &Line : strs) { 1265 Line = Line.trim(); 1266 if (!Line.startswith("physical id") && !Line.startswith("core id")) 1267 continue; 1268 std::pair<StringRef, StringRef> Data = Line.split(':'); 1269 auto Name = Data.first.trim(); 1270 auto Val = Data.second.trim(); 1271 if (Name == "physical id") { 1272 assert(CurPhysicalId == -1 && 1273 "Expected a core id before seeing another physical id"); 1274 Val.getAsInteger(10, CurPhysicalId); 1275 } 1276 if (Name == "core id") { 1277 assert(CurCoreId == -1 && 1278 "Expected a physical id before seeing another core id"); 1279 Val.getAsInteger(10, CurCoreId); 1280 } 1281 if (CurPhysicalId != -1 && CurCoreId != -1) { 1282 UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId)); 1283 CurPhysicalId = -1; 1284 CurCoreId = -1; 1285 } 1286 } 1287 return UniqueItems.size(); 1288 } 1289 #elif defined(__APPLE__) && defined(__x86_64__) 1290 #include <sys/param.h> 1291 #include <sys/sysctl.h> 1292 1293 // Gets the number of *physical cores* on the machine. 1294 static int computeHostNumPhysicalCores() { 1295 uint32_t count; 1296 size_t len = sizeof(count); 1297 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1298 if (count < 1) { 1299 int nm[2]; 1300 nm[0] = CTL_HW; 1301 nm[1] = HW_AVAILCPU; 1302 sysctl(nm, 2, &count, &len, NULL, 0); 1303 if (count < 1) 1304 return -1; 1305 } 1306 return count; 1307 } 1308 #else 1309 // On other systems, return -1 to indicate unknown. 1310 static int computeHostNumPhysicalCores() { return -1; } 1311 #endif 1312 1313 int sys::getHostNumPhysicalCores() { 1314 static int NumCores = computeHostNumPhysicalCores(); 1315 return NumCores; 1316 } 1317 1318 #if defined(__i386__) || defined(_M_IX86) || \ 1319 defined(__x86_64__) || defined(_M_X64) 1320 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1321 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1322 unsigned MaxLevel; 1323 union { 1324 unsigned u[3]; 1325 char c[12]; 1326 } text; 1327 1328 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1329 MaxLevel < 1) 1330 return false; 1331 1332 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1333 1334 Features["cmov"] = (EDX >> 15) & 1; 1335 Features["mmx"] = (EDX >> 23) & 1; 1336 Features["sse"] = (EDX >> 25) & 1; 1337 Features["sse2"] = (EDX >> 26) & 1; 1338 Features["sse3"] = (ECX >> 0) & 1; 1339 Features["ssse3"] = (ECX >> 9) & 1; 1340 Features["sse4.1"] = (ECX >> 19) & 1; 1341 Features["sse4.2"] = (ECX >> 20) & 1; 1342 1343 Features["pclmul"] = (ECX >> 1) & 1; 1344 Features["cx16"] = (ECX >> 13) & 1; 1345 Features["movbe"] = (ECX >> 22) & 1; 1346 Features["popcnt"] = (ECX >> 23) & 1; 1347 Features["aes"] = (ECX >> 25) & 1; 1348 Features["rdrnd"] = (ECX >> 30) & 1; 1349 1350 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1351 // indicates that the AVX registers will be saved and restored on context 1352 // switch, then we have full AVX support. 1353 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1354 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1355 Features["avx"] = HasAVXSave; 1356 Features["fma"] = HasAVXSave && (ECX >> 12) & 1; 1357 Features["f16c"] = HasAVXSave && (ECX >> 29) & 1; 1358 1359 // Only enable XSAVE if OS has enabled support for saving YMM state. 1360 Features["xsave"] = HasAVXSave && (ECX >> 26) & 1; 1361 1362 // AVX512 requires additional context to be saved by the OS. 1363 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1364 1365 unsigned MaxExtLevel; 1366 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1367 1368 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1369 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1370 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1371 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1372 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1373 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1374 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1375 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1376 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1377 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1378 1379 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1380 !getX86CpuIDAndInfoEx(0x80000008,0x0, &EAX, &EBX, &ECX, &EDX); 1381 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1382 1383 bool HasLeaf7 = 1384 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1385 1386 // AVX2 is only supported if we have the OS save support from AVX. 1387 Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1); 1388 1389 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1390 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1391 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1392 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1393 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1394 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1395 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1396 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1397 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1398 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1399 1400 // AVX512 is only supported if the OS supports the context save for it. 1401 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1402 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1403 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1404 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1405 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1406 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1407 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1408 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1409 1410 Features["prefetchwt1"] = HasLeaf7 && (ECX & 1); 1411 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1412 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1413 // Enable protection keys 1414 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1415 1416 bool HasLeafD = MaxLevel >= 0xd && 1417 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1418 1419 // Only enable XSAVE if OS has enabled support for saving YMM state. 1420 Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1); 1421 Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1); 1422 Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1); 1423 1424 return true; 1425 } 1426 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1427 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1428 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1429 if (!P) 1430 return false; 1431 1432 SmallVector<StringRef, 32> Lines; 1433 P->getBuffer().split(Lines, "\n"); 1434 1435 SmallVector<StringRef, 32> CPUFeatures; 1436 1437 // Look for the CPU features. 1438 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1439 if (Lines[I].startswith("Features")) { 1440 Lines[I].split(CPUFeatures, ' '); 1441 break; 1442 } 1443 1444 #if defined(__aarch64__) 1445 // Keep track of which crypto features we have seen 1446 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1447 uint32_t crypto = 0; 1448 #endif 1449 1450 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1451 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1452 #if defined(__aarch64__) 1453 .Case("asimd", "neon") 1454 .Case("fp", "fp-armv8") 1455 .Case("crc32", "crc") 1456 #else 1457 .Case("half", "fp16") 1458 .Case("neon", "neon") 1459 .Case("vfpv3", "vfp3") 1460 .Case("vfpv3d16", "d16") 1461 .Case("vfpv4", "vfp4") 1462 .Case("idiva", "hwdiv-arm") 1463 .Case("idivt", "hwdiv") 1464 #endif 1465 .Default(""); 1466 1467 #if defined(__aarch64__) 1468 // We need to check crypto separately since we need all of the crypto 1469 // extensions to enable the subtarget feature 1470 if (CPUFeatures[I] == "aes") 1471 crypto |= CAP_AES; 1472 else if (CPUFeatures[I] == "pmull") 1473 crypto |= CAP_PMULL; 1474 else if (CPUFeatures[I] == "sha1") 1475 crypto |= CAP_SHA1; 1476 else if (CPUFeatures[I] == "sha2") 1477 crypto |= CAP_SHA2; 1478 #endif 1479 1480 if (LLVMFeatureStr != "") 1481 Features[LLVMFeatureStr] = true; 1482 } 1483 1484 #if defined(__aarch64__) 1485 // If we have all crypto bits we can add the feature 1486 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1487 Features["crypto"] = true; 1488 #endif 1489 1490 return true; 1491 } 1492 #else 1493 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1494 #endif 1495 1496 std::string sys::getProcessTriple() { 1497 Triple PT(Triple::normalize(LLVM_HOST_TRIPLE)); 1498 1499 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1500 PT = PT.get64BitArchVariant(); 1501 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1502 PT = PT.get32BitArchVariant(); 1503 1504 return PT.str(); 1505 } 1506