1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the operating system Host concept. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Support/Host.h" 15 #include "llvm/Support/TargetParser.h" 16 #include "llvm/ADT/SmallSet.h" 17 #include "llvm/ADT/SmallVector.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/ADT/Triple.h" 21 #include "llvm/Config/config.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/FileSystem.h" 24 #include "llvm/Support/MemoryBuffer.h" 25 #include "llvm/Support/raw_ostream.h" 26 #include <assert.h> 27 #include <string.h> 28 29 // Include the platform-specific parts of this class. 30 #ifdef LLVM_ON_UNIX 31 #include "Unix/Host.inc" 32 #endif 33 #ifdef LLVM_ON_WIN32 34 #include "Windows/Host.inc" 35 #endif 36 #ifdef _MSC_VER 37 #include <intrin.h> 38 #endif 39 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 40 #include <mach/host_info.h> 41 #include <mach/mach.h> 42 #include <mach/mach_host.h> 43 #include <mach/machine.h> 44 #endif 45 46 #define DEBUG_TYPE "host-detection" 47 48 //===----------------------------------------------------------------------===// 49 // 50 // Implementations of the CPU detection routines 51 // 52 //===----------------------------------------------------------------------===// 53 54 using namespace llvm; 55 56 static std::unique_ptr<llvm::MemoryBuffer> 57 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 58 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 59 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 60 if (std::error_code EC = Text.getError()) { 61 llvm::errs() << "Can't read " 62 << "/proc/cpuinfo: " << EC.message() << "\n"; 63 return nullptr; 64 } 65 return std::move(*Text); 66 } 67 68 StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) { 69 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 70 // and so we must use an operating-system interface to determine the current 71 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 72 const char *generic = "generic"; 73 74 // The cpu line is second (after the 'processor: 0' line), so if this 75 // buffer is too small then something has changed (or is wrong). 76 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 77 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 78 79 StringRef::const_iterator CIP = CPUInfoStart; 80 81 StringRef::const_iterator CPUStart = 0; 82 size_t CPULen = 0; 83 84 // We need to find the first line which starts with cpu, spaces, and a colon. 85 // After the colon, there may be some additional spaces and then the cpu type. 86 while (CIP < CPUInfoEnd && CPUStart == 0) { 87 if (CIP < CPUInfoEnd && *CIP == '\n') 88 ++CIP; 89 90 if (CIP < CPUInfoEnd && *CIP == 'c') { 91 ++CIP; 92 if (CIP < CPUInfoEnd && *CIP == 'p') { 93 ++CIP; 94 if (CIP < CPUInfoEnd && *CIP == 'u') { 95 ++CIP; 96 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 97 ++CIP; 98 99 if (CIP < CPUInfoEnd && *CIP == ':') { 100 ++CIP; 101 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 102 ++CIP; 103 104 if (CIP < CPUInfoEnd) { 105 CPUStart = CIP; 106 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 107 *CIP != ',' && *CIP != '\n')) 108 ++CIP; 109 CPULen = CIP - CPUStart; 110 } 111 } 112 } 113 } 114 } 115 116 if (CPUStart == 0) 117 while (CIP < CPUInfoEnd && *CIP != '\n') 118 ++CIP; 119 } 120 121 if (CPUStart == 0) 122 return generic; 123 124 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 125 .Case("604e", "604e") 126 .Case("604", "604") 127 .Case("7400", "7400") 128 .Case("7410", "7400") 129 .Case("7447", "7400") 130 .Case("7455", "7450") 131 .Case("G4", "g4") 132 .Case("POWER4", "970") 133 .Case("PPC970FX", "970") 134 .Case("PPC970MP", "970") 135 .Case("G5", "g5") 136 .Case("POWER5", "g5") 137 .Case("A2", "a2") 138 .Case("POWER6", "pwr6") 139 .Case("POWER7", "pwr7") 140 .Case("POWER8", "pwr8") 141 .Case("POWER8E", "pwr8") 142 .Case("POWER8NVL", "pwr8") 143 .Case("POWER9", "pwr9") 144 .Default(generic); 145 } 146 147 StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { 148 // The cpuid register on arm is not accessible from user space. On Linux, 149 // it is exposed through the /proc/cpuinfo file. 150 151 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 152 // in all cases. 153 SmallVector<StringRef, 32> Lines; 154 ProcCpuinfoContent.split(Lines, "\n"); 155 156 // Look for the CPU implementer line. 157 StringRef Implementer; 158 StringRef Hardware; 159 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 160 if (Lines[I].startswith("CPU implementer")) 161 Implementer = Lines[I].substr(15).ltrim("\t :"); 162 if (Lines[I].startswith("Hardware")) 163 Hardware = Lines[I].substr(8).ltrim("\t :"); 164 } 165 166 if (Implementer == "0x41") { // ARM Ltd. 167 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 168 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 169 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 170 return "cortex-a53"; 171 172 173 // Look for the CPU part line. 174 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 175 if (Lines[I].startswith("CPU part")) 176 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 177 // values correspond to the "Part number" in the CP15/c0 register. The 178 // contents are specified in the various processor manuals. 179 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 180 .Case("0x926", "arm926ej-s") 181 .Case("0xb02", "mpcore") 182 .Case("0xb36", "arm1136j-s") 183 .Case("0xb56", "arm1156t2-s") 184 .Case("0xb76", "arm1176jz-s") 185 .Case("0xc08", "cortex-a8") 186 .Case("0xc09", "cortex-a9") 187 .Case("0xc0f", "cortex-a15") 188 .Case("0xc20", "cortex-m0") 189 .Case("0xc23", "cortex-m3") 190 .Case("0xc24", "cortex-m4") 191 .Case("0xd04", "cortex-a35") 192 .Case("0xd03", "cortex-a53") 193 .Case("0xd07", "cortex-a57") 194 .Case("0xd08", "cortex-a72") 195 .Case("0xd09", "cortex-a73") 196 .Default("generic"); 197 } 198 199 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 200 // Look for the CPU part line. 201 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 202 if (Lines[I].startswith("CPU part")) 203 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 204 // values correspond to the "Part number" in the CP15/c0 register. The 205 // contents are specified in the various processor manuals. 206 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 207 .Case("0x06f", "krait") // APQ8064 208 .Case("0x201", "kryo") 209 .Case("0x205", "kryo") 210 .Case("0x211", "kryo") 211 .Case("0x800", "cortex-a73") 212 .Case("0x801", "cortex-a73") 213 .Case("0xc00", "falkor") 214 .Case("0xc01", "saphira") 215 .Default("generic"); 216 217 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. 218 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow 219 // any predictive pattern across variants and parts. 220 unsigned Variant = 0, Part = 0; 221 222 // Look for the CPU variant line, whose value is a 1 digit hexadecimal 223 // number, corresponding to the Variant bits in the CP15/C0 register. 224 for (auto I : Lines) 225 if (I.consume_front("CPU variant")) 226 I.ltrim("\t :").getAsInteger(0, Variant); 227 228 // Look for the CPU part line, whose value is a 3 digit hexadecimal 229 // number, corresponding to the PartNum bits in the CP15/C0 register. 230 for (auto I : Lines) 231 if (I.consume_front("CPU part")) 232 I.ltrim("\t :").getAsInteger(0, Part); 233 234 unsigned Exynos = (Variant << 12) | Part; 235 switch (Exynos) { 236 default: 237 // Default by falling through to Exynos M1. 238 LLVM_FALLTHROUGH; 239 240 case 0x1001: 241 return "exynos-m1"; 242 243 case 0x4001: 244 return "exynos-m2"; 245 } 246 } 247 248 return "generic"; 249 } 250 251 StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { 252 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 253 254 // The "processor 0:" line comes after a fair amount of other information, 255 // including a cache breakdown, but this should be plenty. 256 SmallVector<StringRef, 32> Lines; 257 ProcCpuinfoContent.split(Lines, "\n"); 258 259 // Look for the CPU features. 260 SmallVector<StringRef, 32> CPUFeatures; 261 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 262 if (Lines[I].startswith("features")) { 263 size_t Pos = Lines[I].find(":"); 264 if (Pos != StringRef::npos) { 265 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 266 break; 267 } 268 } 269 270 // We need to check for the presence of vector support independently of 271 // the machine type, since we may only use the vector register set when 272 // supported by the kernel (and hypervisor). 273 bool HaveVectorSupport = false; 274 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 275 if (CPUFeatures[I] == "vx") 276 HaveVectorSupport = true; 277 } 278 279 // Now check the processor machine type. 280 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 281 if (Lines[I].startswith("processor ")) { 282 size_t Pos = Lines[I].find("machine = "); 283 if (Pos != StringRef::npos) { 284 Pos += sizeof("machine = ") - 1; 285 unsigned int Id; 286 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 287 if (Id >= 3906 && HaveVectorSupport) 288 return "z14"; 289 if (Id >= 2964 && HaveVectorSupport) 290 return "z13"; 291 if (Id >= 2827) 292 return "zEC12"; 293 if (Id >= 2817) 294 return "z196"; 295 } 296 } 297 break; 298 } 299 } 300 301 return "generic"; 302 } 303 304 StringRef sys::detail::getHostCPUNameForBPF() { 305 #if !defined(__linux__) || !defined(__x86_64__) 306 return "generic"; 307 #else 308 uint8_t insns[40] __attribute__ ((aligned (8))) = 309 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 310 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 311 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 312 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 313 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 314 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 315 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 316 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 317 /* BPF_EXIT_INSN() */ 318 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 319 320 struct bpf_prog_load_attr { 321 uint32_t prog_type; 322 uint32_t insn_cnt; 323 uint64_t insns; 324 uint64_t license; 325 uint32_t log_level; 326 uint32_t log_size; 327 uint64_t log_buf; 328 uint32_t kern_version; 329 uint32_t prog_flags; 330 } attr = {}; 331 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 332 attr.insn_cnt = 5; 333 attr.insns = (uint64_t)insns; 334 attr.license = (uint64_t)"DUMMY"; 335 336 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 337 if (fd >= 0) { 338 close(fd); 339 return "v2"; 340 } 341 return "v1"; 342 #endif 343 } 344 345 #if defined(__i386__) || defined(_M_IX86) || \ 346 defined(__x86_64__) || defined(_M_X64) 347 348 enum VendorSignatures { 349 SIG_INTEL = 0x756e6547 /* Genu */, 350 SIG_AMD = 0x68747541 /* Auth */ 351 }; 352 353 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 354 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 355 // support. Consequently, for i386, the presence of CPUID is checked first 356 // via the corresponding eflags bit. 357 // Removal of cpuid.h header motivated by PR30384 358 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 359 // or test-suite, but are used in external projects e.g. libstdcxx 360 static bool isCpuIdSupported() { 361 #if defined(__GNUC__) || defined(__clang__) 362 #if defined(__i386__) 363 int __cpuid_supported; 364 __asm__(" pushfl\n" 365 " popl %%eax\n" 366 " movl %%eax,%%ecx\n" 367 " xorl $0x00200000,%%eax\n" 368 " pushl %%eax\n" 369 " popfl\n" 370 " pushfl\n" 371 " popl %%eax\n" 372 " movl $0,%0\n" 373 " cmpl %%eax,%%ecx\n" 374 " je 1f\n" 375 " movl $1,%0\n" 376 "1:" 377 : "=r"(__cpuid_supported) 378 : 379 : "eax", "ecx"); 380 if (!__cpuid_supported) 381 return false; 382 #endif 383 return true; 384 #endif 385 return true; 386 } 387 388 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 389 /// the specified arguments. If we can't run cpuid on the host, return true. 390 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 391 unsigned *rECX, unsigned *rEDX) { 392 #if defined(__GNUC__) || defined(__clang__) 393 #if defined(__x86_64__) 394 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 395 // FIXME: should we save this for Clang? 396 __asm__("movq\t%%rbx, %%rsi\n\t" 397 "cpuid\n\t" 398 "xchgq\t%%rbx, %%rsi\n\t" 399 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 400 : "a"(value)); 401 return false; 402 #elif defined(__i386__) 403 __asm__("movl\t%%ebx, %%esi\n\t" 404 "cpuid\n\t" 405 "xchgl\t%%ebx, %%esi\n\t" 406 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 407 : "a"(value)); 408 return false; 409 #else 410 return true; 411 #endif 412 #elif defined(_MSC_VER) 413 // The MSVC intrinsic is portable across x86 and x64. 414 int registers[4]; 415 __cpuid(registers, value); 416 *rEAX = registers[0]; 417 *rEBX = registers[1]; 418 *rECX = registers[2]; 419 *rEDX = registers[3]; 420 return false; 421 #else 422 return true; 423 #endif 424 } 425 426 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 427 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 428 /// return true. 429 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 430 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 431 unsigned *rEDX) { 432 #if defined(__GNUC__) || defined(__clang__) 433 #if defined(__x86_64__) 434 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 435 // FIXME: should we save this for Clang? 436 __asm__("movq\t%%rbx, %%rsi\n\t" 437 "cpuid\n\t" 438 "xchgq\t%%rbx, %%rsi\n\t" 439 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 440 : "a"(value), "c"(subleaf)); 441 return false; 442 #elif defined(__i386__) 443 __asm__("movl\t%%ebx, %%esi\n\t" 444 "cpuid\n\t" 445 "xchgl\t%%ebx, %%esi\n\t" 446 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 447 : "a"(value), "c"(subleaf)); 448 return false; 449 #else 450 return true; 451 #endif 452 #elif defined(_MSC_VER) 453 int registers[4]; 454 __cpuidex(registers, value, subleaf); 455 *rEAX = registers[0]; 456 *rEBX = registers[1]; 457 *rECX = registers[2]; 458 *rEDX = registers[3]; 459 return false; 460 #else 461 return true; 462 #endif 463 } 464 465 // Read control register 0 (XCR0). Used to detect features such as AVX. 466 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 467 #if defined(__GNUC__) || defined(__clang__) 468 // Check xgetbv; this uses a .byte sequence instead of the instruction 469 // directly because older assemblers do not include support for xgetbv and 470 // there is no easy way to conditionally compile based on the assembler used. 471 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 472 return false; 473 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 474 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 475 *rEAX = Result; 476 *rEDX = Result >> 32; 477 return false; 478 #else 479 return true; 480 #endif 481 } 482 483 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 484 unsigned *Model) { 485 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 486 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 487 if (*Family == 6 || *Family == 0xf) { 488 if (*Family == 0xf) 489 // Examine extended family ID if family ID is F. 490 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 491 // Examine extended model ID if family ID is 6 or F. 492 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 493 } 494 } 495 496 static void 497 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 498 unsigned Brand_id, unsigned Features, 499 unsigned Features2, unsigned *Type, 500 unsigned *Subtype) { 501 if (Brand_id != 0) 502 return; 503 switch (Family) { 504 case 3: 505 *Type = X86::INTEL_i386; 506 break; 507 case 4: 508 *Type = X86::INTEL_i486; 509 break; 510 case 5: 511 if (Features & (1 << X86::FEATURE_MMX)) { 512 *Type = X86::INTEL_PENTIUM_MMX; 513 break; 514 } 515 *Type = X86::INTEL_PENTIUM; 516 break; 517 case 6: 518 switch (Model) { 519 case 0x01: // Pentium Pro processor 520 *Type = X86::INTEL_PENTIUM_PRO; 521 break; 522 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 523 // model 03 524 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 525 // model 05, and Intel Celeron processor, model 05 526 case 0x06: // Celeron processor, model 06 527 *Type = X86::INTEL_PENTIUM_II; 528 break; 529 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 530 // processor, model 07 531 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 532 // model 08, and Celeron processor, model 08 533 case 0x0a: // Pentium III Xeon processor, model 0Ah 534 case 0x0b: // Pentium III processor, model 0Bh 535 *Type = X86::INTEL_PENTIUM_III; 536 break; 537 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 538 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 539 // 0Dh. All processors are manufactured using the 90 nm process. 540 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 541 // Integrated Processor with Intel QuickAssist Technology 542 *Type = X86::INTEL_PENTIUM_M; 543 break; 544 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 545 // 0Eh. All processors are manufactured using the 65 nm process. 546 *Type = X86::INTEL_CORE_DUO; 547 break; // yonah 548 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 549 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 550 // mobile processor, Intel Core 2 Extreme processor, Intel 551 // Pentium Dual-Core processor, Intel Xeon processor, model 552 // 0Fh. All processors are manufactured using the 65 nm process. 553 case 0x16: // Intel Celeron processor model 16h. All processors are 554 // manufactured using the 65 nm process 555 *Type = X86::INTEL_CORE2; // "core2" 556 *Subtype = X86::INTEL_CORE2_65; 557 break; 558 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 559 // 17h. All processors are manufactured using the 45 nm process. 560 // 561 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 562 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 563 // the 45 nm process. 564 *Type = X86::INTEL_CORE2; // "penryn" 565 *Subtype = X86::INTEL_CORE2_45; 566 break; 567 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 568 // processors are manufactured using the 45 nm process. 569 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 570 // As found in a Summer 2010 model iMac. 571 case 0x1f: 572 case 0x2e: // Nehalem EX 573 *Type = X86::INTEL_COREI7; // "nehalem" 574 *Subtype = X86::INTEL_COREI7_NEHALEM; 575 break; 576 case 0x25: // Intel Core i7, laptop version. 577 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 578 // processors are manufactured using the 32 nm process. 579 case 0x2f: // Westmere EX 580 *Type = X86::INTEL_COREI7; // "westmere" 581 *Subtype = X86::INTEL_COREI7_WESTMERE; 582 break; 583 case 0x2a: // Intel Core i7 processor. All processors are manufactured 584 // using the 32 nm process. 585 case 0x2d: 586 *Type = X86::INTEL_COREI7; //"sandybridge" 587 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 588 break; 589 case 0x3a: 590 case 0x3e: // Ivy Bridge EP 591 *Type = X86::INTEL_COREI7; // "ivybridge" 592 *Subtype = X86::INTEL_COREI7_IVYBRIDGE; 593 break; 594 595 // Haswell: 596 case 0x3c: 597 case 0x3f: 598 case 0x45: 599 case 0x46: 600 *Type = X86::INTEL_COREI7; // "haswell" 601 *Subtype = X86::INTEL_COREI7_HASWELL; 602 break; 603 604 // Broadwell: 605 case 0x3d: 606 case 0x47: 607 case 0x4f: 608 case 0x56: 609 *Type = X86::INTEL_COREI7; // "broadwell" 610 *Subtype = X86::INTEL_COREI7_BROADWELL; 611 break; 612 613 // Skylake: 614 case 0x4e: // Skylake mobile 615 case 0x5e: // Skylake desktop 616 case 0x8e: // Kaby Lake mobile 617 case 0x9e: // Kaby Lake desktop 618 *Type = X86::INTEL_COREI7; // "skylake" 619 *Subtype = X86::INTEL_COREI7_SKYLAKE; 620 break; 621 622 // Skylake Xeon: 623 case 0x55: 624 *Type = X86::INTEL_COREI7; 625 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 626 break; 627 628 // Cannonlake: 629 case 0x66: 630 *Type = X86::INTEL_COREI7; 631 *Subtype = X86::INTEL_COREI7_CANNONLAKE; // "cannonlake" 632 break; 633 634 case 0x1c: // Most 45 nm Intel Atom processors 635 case 0x26: // 45 nm Atom Lincroft 636 case 0x27: // 32 nm Atom Medfield 637 case 0x35: // 32 nm Atom Midview 638 case 0x36: // 32 nm Atom Midview 639 *Type = X86::INTEL_BONNELL; 640 break; // "bonnell" 641 642 // Atom Silvermont codes from the Intel software optimization guide. 643 case 0x37: 644 case 0x4a: 645 case 0x4d: 646 case 0x5a: 647 case 0x5d: 648 case 0x4c: // really airmont 649 *Type = X86::INTEL_SILVERMONT; 650 break; // "silvermont" 651 // Goldmont: 652 case 0x5c: // Apollo Lake 653 case 0x5f: // Denverton 654 case 0x7a: // Gemini Lake 655 *Type = X86::INTEL_GOLDMONT; 656 break; // "goldmont" 657 case 0x57: 658 *Type = X86::INTEL_KNL; // knl 659 break; 660 case 0x85: 661 *Type = X86::INTEL_KNM; // knm 662 break; 663 664 default: // Unknown family 6 CPU, try to guess. 665 if (Features & (1 << X86::FEATURE_AVX512VBMI)) { 666 *Type = X86::INTEL_COREI7; 667 *Subtype = X86::INTEL_COREI7_CANNONLAKE; 668 break; 669 } 670 671 if (Features & (1 << X86::FEATURE_AVX512VL)) { 672 *Type = X86::INTEL_COREI7; 673 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; 674 break; 675 } 676 677 if (Features & (1 << X86::FEATURE_AVX512ER)) { 678 *Type = X86::INTEL_KNL; // knl 679 break; 680 } 681 682 if (Features2 & (1 << (X86::FEATURE_CLFLUSHOPT - 32))) { 683 if (Features2 & (1 << (X86::FEATURE_SHA - 32))) { 684 *Type = X86::INTEL_GOLDMONT; 685 } else { 686 *Type = X86::INTEL_COREI7; 687 *Subtype = X86::INTEL_COREI7_SKYLAKE; 688 } 689 break; 690 } 691 if (Features2 & (1 << (X86::FEATURE_ADX - 32))) { 692 *Type = X86::INTEL_COREI7; 693 *Subtype = X86::INTEL_COREI7_BROADWELL; 694 break; 695 } 696 if (Features & (1 << X86::FEATURE_AVX2)) { 697 *Type = X86::INTEL_COREI7; 698 *Subtype = X86::INTEL_COREI7_HASWELL; 699 break; 700 } 701 if (Features & (1 << X86::FEATURE_AVX)) { 702 *Type = X86::INTEL_COREI7; 703 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 704 break; 705 } 706 if (Features & (1 << X86::FEATURE_SSE4_2)) { 707 if (Features2 & (1 << (X86::FEATURE_MOVBE - 32))) { 708 *Type = X86::INTEL_SILVERMONT; 709 } else { 710 *Type = X86::INTEL_COREI7; 711 *Subtype = X86::INTEL_COREI7_NEHALEM; 712 } 713 break; 714 } 715 if (Features & (1 << X86::FEATURE_SSE4_1)) { 716 *Type = X86::INTEL_CORE2; // "penryn" 717 *Subtype = X86::INTEL_CORE2_45; 718 break; 719 } 720 if (Features & (1 << X86::FEATURE_SSSE3)) { 721 if (Features2 & (1 << (X86::FEATURE_MOVBE - 32))) { 722 *Type = X86::INTEL_BONNELL; // "bonnell" 723 } else { 724 *Type = X86::INTEL_CORE2; // "core2" 725 *Subtype = X86::INTEL_CORE2_65; 726 } 727 break; 728 } 729 if (Features2 & (1 << (X86::FEATURE_EM64T - 32))) { 730 *Type = X86::INTEL_CORE2; // "core2" 731 *Subtype = X86::INTEL_CORE2_65; 732 break; 733 } 734 if (Features & (1 << X86::FEATURE_SSE3)) { 735 *Type = X86::INTEL_CORE_DUO; 736 break; 737 } 738 if (Features & (1 << X86::FEATURE_SSE2)) { 739 *Type = X86::INTEL_PENTIUM_M; 740 break; 741 } 742 if (Features & (1 << X86::FEATURE_SSE)) { 743 *Type = X86::INTEL_PENTIUM_III; 744 break; 745 } 746 if (Features & (1 << X86::FEATURE_MMX)) { 747 *Type = X86::INTEL_PENTIUM_II; 748 break; 749 } 750 *Type = X86::INTEL_PENTIUM_PRO; 751 break; 752 } 753 break; 754 case 15: { 755 if (Features2 & (1 << (X86::FEATURE_EM64T - 32))) { 756 *Type = X86::INTEL_NOCONA; 757 break; 758 } 759 if (Features & (1 << X86::FEATURE_SSE3)) { 760 *Type = X86::INTEL_PRESCOTT; 761 break; 762 } 763 *Type = X86::INTEL_PENTIUM_IV; 764 break; 765 } 766 default: 767 break; /*"generic"*/ 768 } 769 } 770 771 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 772 unsigned Features, unsigned *Type, 773 unsigned *Subtype) { 774 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 775 // appears to be no way to generate the wide variety of AMD-specific targets 776 // from the information returned from CPUID. 777 switch (Family) { 778 case 4: 779 *Type = X86::AMD_i486; 780 break; 781 case 5: 782 *Type = X86::AMDPENTIUM; 783 switch (Model) { 784 case 6: 785 case 7: 786 *Subtype = X86::AMDPENTIUM_K6; 787 break; // "k6" 788 case 8: 789 *Subtype = X86::AMDPENTIUM_K62; 790 break; // "k6-2" 791 case 9: 792 case 13: 793 *Subtype = X86::AMDPENTIUM_K63; 794 break; // "k6-3" 795 case 10: 796 *Subtype = X86::AMDPENTIUM_GEODE; 797 break; // "geode" 798 } 799 break; 800 case 6: 801 if (Features & (1 << X86::FEATURE_SSE)) { 802 *Type = X86::AMD_ATHLON_XP; 803 break; // "athlon-xp" 804 } 805 *Type = X86::AMD_ATHLON; 806 break; // "athlon" 807 case 15: 808 if (Features & (1 << X86::FEATURE_SSE3)) { 809 *Type = X86::AMD_K8SSE3; 810 break; // "k8-sse3" 811 } 812 *Type = X86::AMD_K8; 813 break; // "k8" 814 case 16: 815 *Type = X86::AMDFAM10H; // "amdfam10" 816 switch (Model) { 817 case 2: 818 *Subtype = X86::AMDFAM10H_BARCELONA; 819 break; 820 case 4: 821 *Subtype = X86::AMDFAM10H_SHANGHAI; 822 break; 823 case 8: 824 *Subtype = X86::AMDFAM10H_ISTANBUL; 825 break; 826 } 827 break; 828 case 20: 829 *Type = X86::AMD_BTVER1; 830 break; // "btver1"; 831 case 21: 832 *Type = X86::AMDFAM15H; 833 if (Model >= 0x60 && Model <= 0x7f) { 834 *Subtype = X86::AMDFAM15H_BDVER4; 835 break; // "bdver4"; 60h-7Fh: Excavator 836 } 837 if (Model >= 0x30 && Model <= 0x3f) { 838 *Subtype = X86::AMDFAM15H_BDVER3; 839 break; // "bdver3"; 30h-3Fh: Steamroller 840 } 841 if (Model >= 0x10 && Model <= 0x1f) { 842 *Subtype = X86::AMDFAM15H_BDVER2; 843 break; // "bdver2"; 10h-1Fh: Piledriver 844 } 845 if (Model <= 0x0f) { 846 *Subtype = X86::AMDFAM15H_BDVER1; 847 break; // "bdver1"; 00h-0Fh: Bulldozer 848 } 849 break; 850 case 22: 851 *Type = X86::AMD_BTVER2; 852 break; // "btver2" 853 case 23: 854 *Type = X86::AMDFAM17H; 855 *Subtype = X86::AMDFAM17H_ZNVER1; 856 break; 857 default: 858 break; // "generic" 859 } 860 } 861 862 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 863 unsigned *FeaturesOut, 864 unsigned *Features2Out) { 865 unsigned Features = 0; 866 unsigned Features2 = 0; 867 unsigned EAX, EBX; 868 869 if ((EDX >> 15) & 1) 870 Features |= 1 << X86::FEATURE_CMOV; 871 if ((EDX >> 23) & 1) 872 Features |= 1 << X86::FEATURE_MMX; 873 if ((EDX >> 25) & 1) 874 Features |= 1 << X86::FEATURE_SSE; 875 if ((EDX >> 26) & 1) 876 Features |= 1 << X86::FEATURE_SSE2; 877 878 if ((ECX >> 0) & 1) 879 Features |= 1 << X86::FEATURE_SSE3; 880 if ((ECX >> 1) & 1) 881 Features |= 1 << X86::FEATURE_PCLMUL; 882 if ((ECX >> 9) & 1) 883 Features |= 1 << X86::FEATURE_SSSE3; 884 if ((ECX >> 12) & 1) 885 Features |= 1 << X86::FEATURE_FMA; 886 if ((ECX >> 19) & 1) 887 Features |= 1 << X86::FEATURE_SSE4_1; 888 if ((ECX >> 20) & 1) 889 Features |= 1 << X86::FEATURE_SSE4_2; 890 if ((ECX >> 23) & 1) 891 Features |= 1 << X86::FEATURE_POPCNT; 892 if ((ECX >> 25) & 1) 893 Features |= 1 << X86::FEATURE_AES; 894 895 if ((ECX >> 22) & 1) 896 Features2 |= 1 << (X86::FEATURE_MOVBE - 32); 897 898 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 899 // indicates that the AVX registers will be saved and restored on context 900 // switch, then we have full AVX support. 901 const unsigned AVXBits = (1 << 27) | (1 << 28); 902 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 903 ((EAX & 0x6) == 0x6); 904 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 905 906 if (HasAVX) 907 Features |= 1 << X86::FEATURE_AVX; 908 909 bool HasLeaf7 = 910 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 911 912 if (HasLeaf7 && ((EBX >> 3) & 1)) 913 Features |= 1 << X86::FEATURE_BMI; 914 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 915 Features |= 1 << X86::FEATURE_AVX2; 916 if (HasLeaf7 && ((EBX >> 9) & 1)) 917 Features |= 1 << X86::FEATURE_BMI2; 918 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 919 Features |= 1 << X86::FEATURE_AVX512F; 920 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 921 Features |= 1 << X86::FEATURE_AVX512DQ; 922 if (HasLeaf7 && ((EBX >> 19) & 1)) 923 Features2 |= 1 << (X86::FEATURE_ADX - 32); 924 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 925 Features |= 1 << X86::FEATURE_AVX512IFMA; 926 if (HasLeaf7 && ((EBX >> 23) & 1)) 927 Features2 |= 1 << (X86::FEATURE_CLFLUSHOPT - 32); 928 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 929 Features |= 1 << X86::FEATURE_AVX512PF; 930 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 931 Features |= 1 << X86::FEATURE_AVX512ER; 932 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 933 Features |= 1 << X86::FEATURE_AVX512CD; 934 if (HasLeaf7 && ((EBX >> 29) & 1)) 935 Features2 |= 1 << (X86::FEATURE_SHA - 32); 936 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 937 Features |= 1 << X86::FEATURE_AVX512BW; 938 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 939 Features |= 1 << X86::FEATURE_AVX512VL; 940 941 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 942 Features |= 1 << X86::FEATURE_AVX512VBMI; 943 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 944 Features |= 1 << X86::FEATURE_AVX512VPOPCNTDQ; 945 946 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 947 Features |= 1 << X86::FEATURE_AVX5124VNNIW; 948 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 949 Features |= 1 << X86::FEATURE_AVX5124FMAPS; 950 951 unsigned MaxExtLevel; 952 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 953 954 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 955 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 956 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 957 Features |= 1 << X86::FEATURE_SSE4_A; 958 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 959 Features |= 1 << X86::FEATURE_XOP; 960 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 961 Features |= 1 << X86::FEATURE_FMA4; 962 963 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 964 Features2 |= 1 << (X86::FEATURE_EM64T - 32); 965 966 *FeaturesOut = Features; 967 *Features2Out = Features2; 968 } 969 970 StringRef sys::getHostCPUName() { 971 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 972 unsigned MaxLeaf, Vendor; 973 974 #if defined(__GNUC__) || defined(__clang__) 975 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here 976 // and simplify it to not invoke __cpuid (like cpu_model.c in 977 // compiler-rt/lib/builtins/cpu_model.c? 978 // Opting for the second option. 979 if(!isCpuIdSupported()) 980 return "generic"; 981 #endif 982 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) 983 return "generic"; 984 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 985 986 unsigned Brand_id = EBX & 0xff; 987 unsigned Family = 0, Model = 0; 988 unsigned Features = 0, Features2 = 0; 989 detectX86FamilyModel(EAX, &Family, &Model); 990 getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2); 991 992 unsigned Type = 0; 993 unsigned Subtype = 0; 994 995 if (Vendor == SIG_INTEL) { 996 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, 997 Features2, &Type, &Subtype); 998 } else if (Vendor == SIG_AMD) { 999 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1000 } 1001 1002 // Check subtypes first since those are more specific. 1003 #define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \ 1004 if (Subtype == X86::ENUM) \ 1005 return ARCHNAME; 1006 #include "llvm/Support/X86TargetParser.def" 1007 1008 // Now check types. 1009 #define X86_CPU_TYPE(ARCHNAME, ENUM) \ 1010 if (Type == X86::ENUM) \ 1011 return ARCHNAME; 1012 #include "llvm/Support/X86TargetParser.def" 1013 1014 return "generic"; 1015 } 1016 1017 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1018 StringRef sys::getHostCPUName() { 1019 host_basic_info_data_t hostInfo; 1020 mach_msg_type_number_t infoCount; 1021 1022 infoCount = HOST_BASIC_INFO_COUNT; 1023 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo, 1024 &infoCount); 1025 1026 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1027 return "generic"; 1028 1029 switch (hostInfo.cpu_subtype) { 1030 case CPU_SUBTYPE_POWERPC_601: 1031 return "601"; 1032 case CPU_SUBTYPE_POWERPC_602: 1033 return "602"; 1034 case CPU_SUBTYPE_POWERPC_603: 1035 return "603"; 1036 case CPU_SUBTYPE_POWERPC_603e: 1037 return "603e"; 1038 case CPU_SUBTYPE_POWERPC_603ev: 1039 return "603ev"; 1040 case CPU_SUBTYPE_POWERPC_604: 1041 return "604"; 1042 case CPU_SUBTYPE_POWERPC_604e: 1043 return "604e"; 1044 case CPU_SUBTYPE_POWERPC_620: 1045 return "620"; 1046 case CPU_SUBTYPE_POWERPC_750: 1047 return "750"; 1048 case CPU_SUBTYPE_POWERPC_7400: 1049 return "7400"; 1050 case CPU_SUBTYPE_POWERPC_7450: 1051 return "7450"; 1052 case CPU_SUBTYPE_POWERPC_970: 1053 return "970"; 1054 default:; 1055 } 1056 1057 return "generic"; 1058 } 1059 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1060 StringRef sys::getHostCPUName() { 1061 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1062 StringRef Content = P ? P->getBuffer() : ""; 1063 return detail::getHostCPUNameForPowerPC(Content); 1064 } 1065 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1066 StringRef sys::getHostCPUName() { 1067 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1068 StringRef Content = P ? P->getBuffer() : ""; 1069 return detail::getHostCPUNameForARM(Content); 1070 } 1071 #elif defined(__linux__) && defined(__s390x__) 1072 StringRef sys::getHostCPUName() { 1073 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1074 StringRef Content = P ? P->getBuffer() : ""; 1075 return detail::getHostCPUNameForS390x(Content); 1076 } 1077 #else 1078 StringRef sys::getHostCPUName() { return "generic"; } 1079 #endif 1080 1081 #if defined(__linux__) && defined(__x86_64__) 1082 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1083 // using the number of unique physical/core id pairs. The following 1084 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1085 static int computeHostNumPhysicalCores() { 1086 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1087 // mmapped because it appears to have 0 size. 1088 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1089 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1090 if (std::error_code EC = Text.getError()) { 1091 llvm::errs() << "Can't read " 1092 << "/proc/cpuinfo: " << EC.message() << "\n"; 1093 return -1; 1094 } 1095 SmallVector<StringRef, 8> strs; 1096 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1097 /*KeepEmpty=*/false); 1098 int CurPhysicalId = -1; 1099 int CurCoreId = -1; 1100 SmallSet<std::pair<int, int>, 32> UniqueItems; 1101 for (auto &Line : strs) { 1102 Line = Line.trim(); 1103 if (!Line.startswith("physical id") && !Line.startswith("core id")) 1104 continue; 1105 std::pair<StringRef, StringRef> Data = Line.split(':'); 1106 auto Name = Data.first.trim(); 1107 auto Val = Data.second.trim(); 1108 if (Name == "physical id") { 1109 assert(CurPhysicalId == -1 && 1110 "Expected a core id before seeing another physical id"); 1111 Val.getAsInteger(10, CurPhysicalId); 1112 } 1113 if (Name == "core id") { 1114 assert(CurCoreId == -1 && 1115 "Expected a physical id before seeing another core id"); 1116 Val.getAsInteger(10, CurCoreId); 1117 } 1118 if (CurPhysicalId != -1 && CurCoreId != -1) { 1119 UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId)); 1120 CurPhysicalId = -1; 1121 CurCoreId = -1; 1122 } 1123 } 1124 return UniqueItems.size(); 1125 } 1126 #elif defined(__APPLE__) && defined(__x86_64__) 1127 #include <sys/param.h> 1128 #include <sys/sysctl.h> 1129 1130 // Gets the number of *physical cores* on the machine. 1131 static int computeHostNumPhysicalCores() { 1132 uint32_t count; 1133 size_t len = sizeof(count); 1134 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1135 if (count < 1) { 1136 int nm[2]; 1137 nm[0] = CTL_HW; 1138 nm[1] = HW_AVAILCPU; 1139 sysctl(nm, 2, &count, &len, NULL, 0); 1140 if (count < 1) 1141 return -1; 1142 } 1143 return count; 1144 } 1145 #else 1146 // On other systems, return -1 to indicate unknown. 1147 static int computeHostNumPhysicalCores() { return -1; } 1148 #endif 1149 1150 int sys::getHostNumPhysicalCores() { 1151 static int NumCores = computeHostNumPhysicalCores(); 1152 return NumCores; 1153 } 1154 1155 #if defined(__i386__) || defined(_M_IX86) || \ 1156 defined(__x86_64__) || defined(_M_X64) 1157 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1158 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1159 unsigned MaxLevel; 1160 union { 1161 unsigned u[3]; 1162 char c[12]; 1163 } text; 1164 1165 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1166 MaxLevel < 1) 1167 return false; 1168 1169 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1170 1171 Features["cmov"] = (EDX >> 15) & 1; 1172 Features["mmx"] = (EDX >> 23) & 1; 1173 Features["sse"] = (EDX >> 25) & 1; 1174 Features["sse2"] = (EDX >> 26) & 1; 1175 1176 Features["sse3"] = (ECX >> 0) & 1; 1177 Features["pclmul"] = (ECX >> 1) & 1; 1178 Features["ssse3"] = (ECX >> 9) & 1; 1179 Features["cx16"] = (ECX >> 13) & 1; 1180 Features["sse4.1"] = (ECX >> 19) & 1; 1181 Features["sse4.2"] = (ECX >> 20) & 1; 1182 Features["movbe"] = (ECX >> 22) & 1; 1183 Features["popcnt"] = (ECX >> 23) & 1; 1184 Features["aes"] = (ECX >> 25) & 1; 1185 Features["rdrnd"] = (ECX >> 30) & 1; 1186 1187 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1188 // indicates that the AVX registers will be saved and restored on context 1189 // switch, then we have full AVX support. 1190 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1191 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1192 // AVX512 requires additional context to be saved by the OS. 1193 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1194 1195 Features["avx"] = HasAVXSave; 1196 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave; 1197 // Only enable XSAVE if OS has enabled support for saving YMM state. 1198 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave; 1199 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave; 1200 1201 unsigned MaxExtLevel; 1202 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1203 1204 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1205 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1206 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1); 1207 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1208 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1209 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1210 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1211 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1212 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1213 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1214 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1215 1216 // Miscellaneous memory related features, detected by 1217 // using the 0x80000008 leaf of the CPUID instruction 1218 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1219 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX); 1220 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1221 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1); 1222 1223 bool HasLeaf7 = 1224 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1225 1226 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1227 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1228 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1229 // AVX2 is only supported if we have the OS save support from AVX. 1230 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave; 1231 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1232 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1233 // AVX512 is only supported if the OS supports the context save for it. 1234 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1235 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1236 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1237 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1238 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1239 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1240 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1241 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1242 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1243 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1244 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1245 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1246 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1247 1248 Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1); 1249 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1250 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1251 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save; 1252 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1); 1253 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1); 1254 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave; 1255 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave; 1256 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save; 1257 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save; 1258 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1259 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1); 1260 1261 Features["ibt"] = HasLeaf7 && ((EDX >> 20) & 1); 1262 1263 bool HasLeafD = MaxLevel >= 0xd && 1264 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1265 1266 // Only enable XSAVE if OS has enabled support for saving YMM state. 1267 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave; 1268 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave; 1269 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave; 1270 1271 return true; 1272 } 1273 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1274 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1275 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1276 if (!P) 1277 return false; 1278 1279 SmallVector<StringRef, 32> Lines; 1280 P->getBuffer().split(Lines, "\n"); 1281 1282 SmallVector<StringRef, 32> CPUFeatures; 1283 1284 // Look for the CPU features. 1285 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1286 if (Lines[I].startswith("Features")) { 1287 Lines[I].split(CPUFeatures, ' '); 1288 break; 1289 } 1290 1291 #if defined(__aarch64__) 1292 // Keep track of which crypto features we have seen 1293 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1294 uint32_t crypto = 0; 1295 #endif 1296 1297 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1298 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1299 #if defined(__aarch64__) 1300 .Case("asimd", "neon") 1301 .Case("fp", "fp-armv8") 1302 .Case("crc32", "crc") 1303 #else 1304 .Case("half", "fp16") 1305 .Case("neon", "neon") 1306 .Case("vfpv3", "vfp3") 1307 .Case("vfpv3d16", "d16") 1308 .Case("vfpv4", "vfp4") 1309 .Case("idiva", "hwdiv-arm") 1310 .Case("idivt", "hwdiv") 1311 #endif 1312 .Default(""); 1313 1314 #if defined(__aarch64__) 1315 // We need to check crypto separately since we need all of the crypto 1316 // extensions to enable the subtarget feature 1317 if (CPUFeatures[I] == "aes") 1318 crypto |= CAP_AES; 1319 else if (CPUFeatures[I] == "pmull") 1320 crypto |= CAP_PMULL; 1321 else if (CPUFeatures[I] == "sha1") 1322 crypto |= CAP_SHA1; 1323 else if (CPUFeatures[I] == "sha2") 1324 crypto |= CAP_SHA2; 1325 #endif 1326 1327 if (LLVMFeatureStr != "") 1328 Features[LLVMFeatureStr] = true; 1329 } 1330 1331 #if defined(__aarch64__) 1332 // If we have all crypto bits we can add the feature 1333 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1334 Features["crypto"] = true; 1335 #endif 1336 1337 return true; 1338 } 1339 #else 1340 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1341 #endif 1342 1343 std::string sys::getProcessTriple() { 1344 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1345 Triple PT(Triple::normalize(TargetTripleString)); 1346 1347 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1348 PT = PT.get64BitArchVariant(); 1349 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1350 PT = PT.get32BitArchVariant(); 1351 1352 return PT.str(); 1353 } 1354