1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the operating system Host concept. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/Host.h" 14 #include "llvm/ADT/SmallSet.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringMap.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/llvm-config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/X86TargetParser.h" 25 #include "llvm/Support/raw_ostream.h" 26 #include <assert.h> 27 #include <string.h> 28 29 // Include the platform-specific parts of this class. 30 #ifdef LLVM_ON_UNIX 31 #include "Unix/Host.inc" 32 #include <sched.h> 33 #endif 34 #ifdef _WIN32 35 #include "Windows/Host.inc" 36 #endif 37 #ifdef _MSC_VER 38 #include <intrin.h> 39 #endif 40 #if defined(__APPLE__) && (!defined(__x86_64__)) 41 #include <mach/host_info.h> 42 #include <mach/mach.h> 43 #include <mach/mach_host.h> 44 #include <mach/machine.h> 45 #endif 46 47 #define DEBUG_TYPE "host-detection" 48 49 //===----------------------------------------------------------------------===// 50 // 51 // Implementations of the CPU detection routines 52 // 53 //===----------------------------------------------------------------------===// 54 55 using namespace llvm; 56 57 static std::unique_ptr<llvm::MemoryBuffer> 58 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 59 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 60 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 61 if (std::error_code EC = Text.getError()) { 62 llvm::errs() << "Can't read " 63 << "/proc/cpuinfo: " << EC.message() << "\n"; 64 return nullptr; 65 } 66 return std::move(*Text); 67 } 68 69 StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) { 70 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 71 // and so we must use an operating-system interface to determine the current 72 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 73 const char *generic = "generic"; 74 75 // The cpu line is second (after the 'processor: 0' line), so if this 76 // buffer is too small then something has changed (or is wrong). 77 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 78 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 79 80 StringRef::const_iterator CIP = CPUInfoStart; 81 82 StringRef::const_iterator CPUStart = 0; 83 size_t CPULen = 0; 84 85 // We need to find the first line which starts with cpu, spaces, and a colon. 86 // After the colon, there may be some additional spaces and then the cpu type. 87 while (CIP < CPUInfoEnd && CPUStart == 0) { 88 if (CIP < CPUInfoEnd && *CIP == '\n') 89 ++CIP; 90 91 if (CIP < CPUInfoEnd && *CIP == 'c') { 92 ++CIP; 93 if (CIP < CPUInfoEnd && *CIP == 'p') { 94 ++CIP; 95 if (CIP < CPUInfoEnd && *CIP == 'u') { 96 ++CIP; 97 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 98 ++CIP; 99 100 if (CIP < CPUInfoEnd && *CIP == ':') { 101 ++CIP; 102 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 103 ++CIP; 104 105 if (CIP < CPUInfoEnd) { 106 CPUStart = CIP; 107 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 108 *CIP != ',' && *CIP != '\n')) 109 ++CIP; 110 CPULen = CIP - CPUStart; 111 } 112 } 113 } 114 } 115 } 116 117 if (CPUStart == 0) 118 while (CIP < CPUInfoEnd && *CIP != '\n') 119 ++CIP; 120 } 121 122 if (CPUStart == 0) 123 return generic; 124 125 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 126 .Case("604e", "604e") 127 .Case("604", "604") 128 .Case("7400", "7400") 129 .Case("7410", "7400") 130 .Case("7447", "7400") 131 .Case("7455", "7450") 132 .Case("G4", "g4") 133 .Case("POWER4", "970") 134 .Case("PPC970FX", "970") 135 .Case("PPC970MP", "970") 136 .Case("G5", "g5") 137 .Case("POWER5", "g5") 138 .Case("A2", "a2") 139 .Case("POWER6", "pwr6") 140 .Case("POWER7", "pwr7") 141 .Case("POWER8", "pwr8") 142 .Case("POWER8E", "pwr8") 143 .Case("POWER8NVL", "pwr8") 144 .Case("POWER9", "pwr9") 145 .Case("POWER10", "pwr10") 146 // FIXME: If we get a simulator or machine with the capabilities of 147 // mcpu=future, we should revisit this and add the name reported by the 148 // simulator/machine. 149 .Default(generic); 150 } 151 152 StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { 153 // The cpuid register on arm is not accessible from user space. On Linux, 154 // it is exposed through the /proc/cpuinfo file. 155 156 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 157 // in all cases. 158 SmallVector<StringRef, 32> Lines; 159 ProcCpuinfoContent.split(Lines, "\n"); 160 161 // Look for the CPU implementer line. 162 StringRef Implementer; 163 StringRef Hardware; 164 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 165 if (Lines[I].startswith("CPU implementer")) 166 Implementer = Lines[I].substr(15).ltrim("\t :"); 167 if (Lines[I].startswith("Hardware")) 168 Hardware = Lines[I].substr(8).ltrim("\t :"); 169 } 170 171 if (Implementer == "0x41") { // ARM Ltd. 172 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 173 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 174 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 175 return "cortex-a53"; 176 177 178 // Look for the CPU part line. 179 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 180 if (Lines[I].startswith("CPU part")) 181 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 182 // values correspond to the "Part number" in the CP15/c0 register. The 183 // contents are specified in the various processor manuals. 184 // This corresponds to the Main ID Register in Technical Reference Manuals. 185 // and is used in programs like sys-utils 186 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 187 .Case("0x926", "arm926ej-s") 188 .Case("0xb02", "mpcore") 189 .Case("0xb36", "arm1136j-s") 190 .Case("0xb56", "arm1156t2-s") 191 .Case("0xb76", "arm1176jz-s") 192 .Case("0xc08", "cortex-a8") 193 .Case("0xc09", "cortex-a9") 194 .Case("0xc0f", "cortex-a15") 195 .Case("0xc20", "cortex-m0") 196 .Case("0xc23", "cortex-m3") 197 .Case("0xc24", "cortex-m4") 198 .Case("0xd22", "cortex-m55") 199 .Case("0xd02", "cortex-a34") 200 .Case("0xd04", "cortex-a35") 201 .Case("0xd03", "cortex-a53") 202 .Case("0xd07", "cortex-a57") 203 .Case("0xd08", "cortex-a72") 204 .Case("0xd09", "cortex-a73") 205 .Case("0xd0a", "cortex-a75") 206 .Case("0xd0b", "cortex-a76") 207 .Case("0xd0c", "neoverse-n1") 208 .Default("generic"); 209 } 210 211 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium. 212 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 213 if (Lines[I].startswith("CPU part")) { 214 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 215 .Case("0x516", "thunderx2t99") 216 .Case("0x0516", "thunderx2t99") 217 .Case("0xaf", "thunderx2t99") 218 .Case("0x0af", "thunderx2t99") 219 .Case("0xa1", "thunderxt88") 220 .Case("0x0a1", "thunderxt88") 221 .Default("generic"); 222 } 223 } 224 } 225 226 if (Implementer == "0x46") { // Fujitsu Ltd. 227 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 228 if (Lines[I].startswith("CPU part")) { 229 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 230 .Case("0x001", "a64fx") 231 .Default("generic"); 232 } 233 } 234 } 235 236 if (Implementer == "0x4e") { // NVIDIA Corporation 237 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 238 if (Lines[I].startswith("CPU part")) { 239 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 240 .Case("0x004", "carmel") 241 .Default("generic"); 242 } 243 } 244 } 245 246 if (Implementer == "0x48") // HiSilicon Technologies, Inc. 247 // Look for the CPU part line. 248 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 249 if (Lines[I].startswith("CPU part")) 250 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 251 // values correspond to the "Part number" in the CP15/c0 register. The 252 // contents are specified in the various processor manuals. 253 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 254 .Case("0xd01", "tsv110") 255 .Default("generic"); 256 257 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 258 // Look for the CPU part line. 259 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 260 if (Lines[I].startswith("CPU part")) 261 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 262 // values correspond to the "Part number" in the CP15/c0 register. The 263 // contents are specified in the various processor manuals. 264 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 265 .Case("0x06f", "krait") // APQ8064 266 .Case("0x201", "kryo") 267 .Case("0x205", "kryo") 268 .Case("0x211", "kryo") 269 .Case("0x800", "cortex-a73") 270 .Case("0x801", "cortex-a73") 271 .Case("0x802", "cortex-a73") 272 .Case("0x803", "cortex-a73") 273 .Case("0x804", "cortex-a73") 274 .Case("0x805", "cortex-a73") 275 .Case("0xc00", "falkor") 276 .Case("0xc01", "saphira") 277 .Default("generic"); 278 279 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. 280 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow 281 // any predictive pattern across variants and parts. 282 unsigned Variant = 0, Part = 0; 283 284 // Look for the CPU variant line, whose value is a 1 digit hexadecimal 285 // number, corresponding to the Variant bits in the CP15/C0 register. 286 for (auto I : Lines) 287 if (I.consume_front("CPU variant")) 288 I.ltrim("\t :").getAsInteger(0, Variant); 289 290 // Look for the CPU part line, whose value is a 3 digit hexadecimal 291 // number, corresponding to the PartNum bits in the CP15/C0 register. 292 for (auto I : Lines) 293 if (I.consume_front("CPU part")) 294 I.ltrim("\t :").getAsInteger(0, Part); 295 296 unsigned Exynos = (Variant << 12) | Part; 297 switch (Exynos) { 298 default: 299 // Default by falling through to Exynos M3. 300 LLVM_FALLTHROUGH; 301 case 0x1002: 302 return "exynos-m3"; 303 case 0x1003: 304 return "exynos-m4"; 305 } 306 } 307 308 return "generic"; 309 } 310 311 StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { 312 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 313 314 // The "processor 0:" line comes after a fair amount of other information, 315 // including a cache breakdown, but this should be plenty. 316 SmallVector<StringRef, 32> Lines; 317 ProcCpuinfoContent.split(Lines, "\n"); 318 319 // Look for the CPU features. 320 SmallVector<StringRef, 32> CPUFeatures; 321 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 322 if (Lines[I].startswith("features")) { 323 size_t Pos = Lines[I].find(":"); 324 if (Pos != StringRef::npos) { 325 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 326 break; 327 } 328 } 329 330 // We need to check for the presence of vector support independently of 331 // the machine type, since we may only use the vector register set when 332 // supported by the kernel (and hypervisor). 333 bool HaveVectorSupport = false; 334 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 335 if (CPUFeatures[I] == "vx") 336 HaveVectorSupport = true; 337 } 338 339 // Now check the processor machine type. 340 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 341 if (Lines[I].startswith("processor ")) { 342 size_t Pos = Lines[I].find("machine = "); 343 if (Pos != StringRef::npos) { 344 Pos += sizeof("machine = ") - 1; 345 unsigned int Id; 346 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 347 if (Id >= 8561 && HaveVectorSupport) 348 return "z15"; 349 if (Id >= 3906 && HaveVectorSupport) 350 return "z14"; 351 if (Id >= 2964 && HaveVectorSupport) 352 return "z13"; 353 if (Id >= 2827) 354 return "zEC12"; 355 if (Id >= 2817) 356 return "z196"; 357 } 358 } 359 break; 360 } 361 } 362 363 return "generic"; 364 } 365 366 StringRef sys::detail::getHostCPUNameForBPF() { 367 #if !defined(__linux__) || !defined(__x86_64__) 368 return "generic"; 369 #else 370 uint8_t v3_insns[40] __attribute__ ((aligned (8))) = 371 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 372 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 373 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 374 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 375 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 376 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 377 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 378 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 379 /* BPF_EXIT_INSN() */ 380 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 381 382 uint8_t v2_insns[40] __attribute__ ((aligned (8))) = 383 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 384 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 385 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 386 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 387 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 388 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 389 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 390 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 391 /* BPF_EXIT_INSN() */ 392 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 393 394 struct bpf_prog_load_attr { 395 uint32_t prog_type; 396 uint32_t insn_cnt; 397 uint64_t insns; 398 uint64_t license; 399 uint32_t log_level; 400 uint32_t log_size; 401 uint64_t log_buf; 402 uint32_t kern_version; 403 uint32_t prog_flags; 404 } attr = {}; 405 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 406 attr.insn_cnt = 5; 407 attr.insns = (uint64_t)v3_insns; 408 attr.license = (uint64_t)"DUMMY"; 409 410 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, 411 sizeof(attr)); 412 if (fd >= 0) { 413 close(fd); 414 return "v3"; 415 } 416 417 /* Clear the whole attr in case its content changed by syscall. */ 418 memset(&attr, 0, sizeof(attr)); 419 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 420 attr.insn_cnt = 5; 421 attr.insns = (uint64_t)v2_insns; 422 attr.license = (uint64_t)"DUMMY"; 423 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 424 if (fd >= 0) { 425 close(fd); 426 return "v2"; 427 } 428 return "v1"; 429 #endif 430 } 431 432 #if defined(__i386__) || defined(_M_IX86) || \ 433 defined(__x86_64__) || defined(_M_X64) 434 435 enum VendorSignatures { 436 SIG_INTEL = 0x756e6547 /* Genu */, 437 SIG_AMD = 0x68747541 /* Auth */ 438 }; 439 440 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 441 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 442 // support. Consequently, for i386, the presence of CPUID is checked first 443 // via the corresponding eflags bit. 444 // Removal of cpuid.h header motivated by PR30384 445 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 446 // or test-suite, but are used in external projects e.g. libstdcxx 447 static bool isCpuIdSupported() { 448 #if defined(__GNUC__) || defined(__clang__) 449 #if defined(__i386__) 450 int __cpuid_supported; 451 __asm__(" pushfl\n" 452 " popl %%eax\n" 453 " movl %%eax,%%ecx\n" 454 " xorl $0x00200000,%%eax\n" 455 " pushl %%eax\n" 456 " popfl\n" 457 " pushfl\n" 458 " popl %%eax\n" 459 " movl $0,%0\n" 460 " cmpl %%eax,%%ecx\n" 461 " je 1f\n" 462 " movl $1,%0\n" 463 "1:" 464 : "=r"(__cpuid_supported) 465 : 466 : "eax", "ecx"); 467 if (!__cpuid_supported) 468 return false; 469 #endif 470 return true; 471 #endif 472 return true; 473 } 474 475 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 476 /// the specified arguments. If we can't run cpuid on the host, return true. 477 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 478 unsigned *rECX, unsigned *rEDX) { 479 #if defined(__GNUC__) || defined(__clang__) 480 #if defined(__x86_64__) 481 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 482 // FIXME: should we save this for Clang? 483 __asm__("movq\t%%rbx, %%rsi\n\t" 484 "cpuid\n\t" 485 "xchgq\t%%rbx, %%rsi\n\t" 486 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 487 : "a"(value)); 488 return false; 489 #elif defined(__i386__) 490 __asm__("movl\t%%ebx, %%esi\n\t" 491 "cpuid\n\t" 492 "xchgl\t%%ebx, %%esi\n\t" 493 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 494 : "a"(value)); 495 return false; 496 #else 497 return true; 498 #endif 499 #elif defined(_MSC_VER) 500 // The MSVC intrinsic is portable across x86 and x64. 501 int registers[4]; 502 __cpuid(registers, value); 503 *rEAX = registers[0]; 504 *rEBX = registers[1]; 505 *rECX = registers[2]; 506 *rEDX = registers[3]; 507 return false; 508 #else 509 return true; 510 #endif 511 } 512 513 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 514 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 515 /// return true. 516 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 517 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 518 unsigned *rEDX) { 519 #if defined(__GNUC__) || defined(__clang__) 520 #if defined(__x86_64__) 521 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 522 // FIXME: should we save this for Clang? 523 __asm__("movq\t%%rbx, %%rsi\n\t" 524 "cpuid\n\t" 525 "xchgq\t%%rbx, %%rsi\n\t" 526 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 527 : "a"(value), "c"(subleaf)); 528 return false; 529 #elif defined(__i386__) 530 __asm__("movl\t%%ebx, %%esi\n\t" 531 "cpuid\n\t" 532 "xchgl\t%%ebx, %%esi\n\t" 533 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 534 : "a"(value), "c"(subleaf)); 535 return false; 536 #else 537 return true; 538 #endif 539 #elif defined(_MSC_VER) 540 int registers[4]; 541 __cpuidex(registers, value, subleaf); 542 *rEAX = registers[0]; 543 *rEBX = registers[1]; 544 *rECX = registers[2]; 545 *rEDX = registers[3]; 546 return false; 547 #else 548 return true; 549 #endif 550 } 551 552 // Read control register 0 (XCR0). Used to detect features such as AVX. 553 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 554 #if defined(__GNUC__) || defined(__clang__) 555 // Check xgetbv; this uses a .byte sequence instead of the instruction 556 // directly because older assemblers do not include support for xgetbv and 557 // there is no easy way to conditionally compile based on the assembler used. 558 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 559 return false; 560 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 561 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 562 *rEAX = Result; 563 *rEDX = Result >> 32; 564 return false; 565 #else 566 return true; 567 #endif 568 } 569 570 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 571 unsigned *Model) { 572 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 573 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 574 if (*Family == 6 || *Family == 0xf) { 575 if (*Family == 0xf) 576 // Examine extended family ID if family ID is F. 577 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 578 // Examine extended model ID if family ID is 6 or F. 579 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 580 } 581 } 582 583 static void 584 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 585 unsigned Brand_id, unsigned Features, 586 unsigned Features2, unsigned Features3, 587 unsigned *Type, unsigned *Subtype) { 588 if (Brand_id != 0) 589 return; 590 switch (Family) { 591 case 3: 592 *Type = X86::INTEL_i386; 593 break; 594 case 4: 595 *Type = X86::INTEL_i486; 596 break; 597 case 5: 598 if (Features & (1 << X86::FEATURE_MMX)) { 599 *Type = X86::INTEL_PENTIUM_MMX; 600 break; 601 } 602 *Type = X86::INTEL_PENTIUM; 603 break; 604 case 6: 605 switch (Model) { 606 case 0x01: // Pentium Pro processor 607 *Type = X86::INTEL_PENTIUM_PRO; 608 break; 609 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 610 // model 03 611 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 612 // model 05, and Intel Celeron processor, model 05 613 case 0x06: // Celeron processor, model 06 614 *Type = X86::INTEL_PENTIUM_II; 615 break; 616 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 617 // processor, model 07 618 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 619 // model 08, and Celeron processor, model 08 620 case 0x0a: // Pentium III Xeon processor, model 0Ah 621 case 0x0b: // Pentium III processor, model 0Bh 622 *Type = X86::INTEL_PENTIUM_III; 623 break; 624 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 625 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 626 // 0Dh. All processors are manufactured using the 90 nm process. 627 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 628 // Integrated Processor with Intel QuickAssist Technology 629 *Type = X86::INTEL_PENTIUM_M; 630 break; 631 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 632 // 0Eh. All processors are manufactured using the 65 nm process. 633 *Type = X86::INTEL_CORE_DUO; 634 break; // yonah 635 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 636 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 637 // mobile processor, Intel Core 2 Extreme processor, Intel 638 // Pentium Dual-Core processor, Intel Xeon processor, model 639 // 0Fh. All processors are manufactured using the 65 nm process. 640 case 0x16: // Intel Celeron processor model 16h. All processors are 641 // manufactured using the 65 nm process 642 *Type = X86::INTEL_CORE2; // "core2" 643 *Subtype = X86::INTEL_CORE2_65; 644 break; 645 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 646 // 17h. All processors are manufactured using the 45 nm process. 647 // 648 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 649 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 650 // the 45 nm process. 651 *Type = X86::INTEL_CORE2; // "penryn" 652 *Subtype = X86::INTEL_CORE2_45; 653 break; 654 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 655 // processors are manufactured using the 45 nm process. 656 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 657 // As found in a Summer 2010 model iMac. 658 case 0x1f: 659 case 0x2e: // Nehalem EX 660 *Type = X86::INTEL_COREI7; // "nehalem" 661 *Subtype = X86::INTEL_COREI7_NEHALEM; 662 break; 663 case 0x25: // Intel Core i7, laptop version. 664 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 665 // processors are manufactured using the 32 nm process. 666 case 0x2f: // Westmere EX 667 *Type = X86::INTEL_COREI7; // "westmere" 668 *Subtype = X86::INTEL_COREI7_WESTMERE; 669 break; 670 case 0x2a: // Intel Core i7 processor. All processors are manufactured 671 // using the 32 nm process. 672 case 0x2d: 673 *Type = X86::INTEL_COREI7; //"sandybridge" 674 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 675 break; 676 case 0x3a: 677 case 0x3e: // Ivy Bridge EP 678 *Type = X86::INTEL_COREI7; // "ivybridge" 679 *Subtype = X86::INTEL_COREI7_IVYBRIDGE; 680 break; 681 682 // Haswell: 683 case 0x3c: 684 case 0x3f: 685 case 0x45: 686 case 0x46: 687 *Type = X86::INTEL_COREI7; // "haswell" 688 *Subtype = X86::INTEL_COREI7_HASWELL; 689 break; 690 691 // Broadwell: 692 case 0x3d: 693 case 0x47: 694 case 0x4f: 695 case 0x56: 696 *Type = X86::INTEL_COREI7; // "broadwell" 697 *Subtype = X86::INTEL_COREI7_BROADWELL; 698 break; 699 700 // Skylake: 701 case 0x4e: // Skylake mobile 702 case 0x5e: // Skylake desktop 703 case 0x8e: // Kaby Lake mobile 704 case 0x9e: // Kaby Lake desktop 705 case 0xa5: // Comet Lake-H/S 706 case 0xa6: // Comet Lake-U 707 *Type = X86::INTEL_COREI7; // "skylake" 708 *Subtype = X86::INTEL_COREI7_SKYLAKE; 709 break; 710 711 // Skylake Xeon: 712 case 0x55: 713 *Type = X86::INTEL_COREI7; 714 if (Features2 & (1 << (X86::FEATURE_AVX512BF16 - 32))) 715 *Subtype = X86::INTEL_COREI7_COOPERLAKE; // "cooperlake" 716 else if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) 717 *Subtype = X86::INTEL_COREI7_CASCADELAKE; // "cascadelake" 718 else 719 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 720 break; 721 722 // Cannonlake: 723 case 0x66: 724 *Type = X86::INTEL_COREI7; 725 *Subtype = X86::INTEL_COREI7_CANNONLAKE; // "cannonlake" 726 break; 727 728 // Icelake: 729 case 0x7d: 730 case 0x7e: 731 *Type = X86::INTEL_COREI7; 732 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; // "icelake-client" 733 break; 734 735 // Icelake Xeon: 736 case 0x6a: 737 case 0x6c: 738 *Type = X86::INTEL_COREI7; 739 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; // "icelake-server" 740 break; 741 742 case 0x1c: // Most 45 nm Intel Atom processors 743 case 0x26: // 45 nm Atom Lincroft 744 case 0x27: // 32 nm Atom Medfield 745 case 0x35: // 32 nm Atom Midview 746 case 0x36: // 32 nm Atom Midview 747 *Type = X86::INTEL_BONNELL; 748 break; // "bonnell" 749 750 // Atom Silvermont codes from the Intel software optimization guide. 751 case 0x37: 752 case 0x4a: 753 case 0x4d: 754 case 0x5a: 755 case 0x5d: 756 case 0x4c: // really airmont 757 *Type = X86::INTEL_SILVERMONT; 758 break; // "silvermont" 759 // Goldmont: 760 case 0x5c: // Apollo Lake 761 case 0x5f: // Denverton 762 *Type = X86::INTEL_GOLDMONT; 763 break; // "goldmont" 764 case 0x7a: 765 *Type = X86::INTEL_GOLDMONT_PLUS; 766 break; 767 case 0x86: 768 *Type = X86::INTEL_TREMONT; 769 break; 770 771 case 0x57: 772 *Type = X86::INTEL_KNL; // knl 773 break; 774 775 case 0x85: 776 *Type = X86::INTEL_KNM; // knm 777 break; 778 779 default: // Unknown family 6 CPU, try to guess. 780 // TODO detect tigerlake host 781 if (Features2 & (1 << (X86::FEATURE_AVX512VP2INTERSECT - 32))) { 782 *Type = X86::INTEL_COREI7; 783 *Subtype = X86::INTEL_COREI7_TIGERLAKE; 784 break; 785 } 786 787 if (Features & (1 << X86::FEATURE_AVX512VBMI2)) { 788 *Type = X86::INTEL_COREI7; 789 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; 790 break; 791 } 792 793 if (Features & (1 << X86::FEATURE_AVX512VBMI)) { 794 *Type = X86::INTEL_COREI7; 795 *Subtype = X86::INTEL_COREI7_CANNONLAKE; 796 break; 797 } 798 799 if (Features2 & (1 << (X86::FEATURE_AVX512BF16 - 32))) { 800 *Type = X86::INTEL_COREI7; 801 *Subtype = X86::INTEL_COREI7_COOPERLAKE; 802 break; 803 } 804 805 if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) { 806 *Type = X86::INTEL_COREI7; 807 *Subtype = X86::INTEL_COREI7_CASCADELAKE; 808 break; 809 } 810 811 if (Features & (1 << X86::FEATURE_AVX512VL)) { 812 *Type = X86::INTEL_COREI7; 813 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; 814 break; 815 } 816 817 if (Features & (1 << X86::FEATURE_AVX512ER)) { 818 *Type = X86::INTEL_KNL; // knl 819 break; 820 } 821 822 if (Features3 & (1 << (X86::FEATURE_CLFLUSHOPT - 64))) { 823 if (Features3 & (1 << (X86::FEATURE_SHA - 64))) { 824 *Type = X86::INTEL_GOLDMONT; 825 } else { 826 *Type = X86::INTEL_COREI7; 827 *Subtype = X86::INTEL_COREI7_SKYLAKE; 828 } 829 break; 830 } 831 if (Features3 & (1 << (X86::FEATURE_ADX - 64))) { 832 *Type = X86::INTEL_COREI7; 833 *Subtype = X86::INTEL_COREI7_BROADWELL; 834 break; 835 } 836 if (Features & (1 << X86::FEATURE_AVX2)) { 837 *Type = X86::INTEL_COREI7; 838 *Subtype = X86::INTEL_COREI7_HASWELL; 839 break; 840 } 841 if (Features & (1 << X86::FEATURE_AVX)) { 842 *Type = X86::INTEL_COREI7; 843 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 844 break; 845 } 846 if (Features & (1 << X86::FEATURE_SSE4_2)) { 847 if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { 848 *Type = X86::INTEL_SILVERMONT; 849 } else { 850 *Type = X86::INTEL_COREI7; 851 *Subtype = X86::INTEL_COREI7_NEHALEM; 852 } 853 break; 854 } 855 if (Features & (1 << X86::FEATURE_SSE4_1)) { 856 *Type = X86::INTEL_CORE2; // "penryn" 857 *Subtype = X86::INTEL_CORE2_45; 858 break; 859 } 860 if (Features & (1 << X86::FEATURE_SSSE3)) { 861 if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { 862 *Type = X86::INTEL_BONNELL; // "bonnell" 863 } else { 864 *Type = X86::INTEL_CORE2; // "core2" 865 *Subtype = X86::INTEL_CORE2_65; 866 } 867 break; 868 } 869 if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { 870 *Type = X86::INTEL_CORE2; // "core2" 871 *Subtype = X86::INTEL_CORE2_65; 872 break; 873 } 874 if (Features & (1 << X86::FEATURE_SSE3)) { 875 *Type = X86::INTEL_CORE_DUO; 876 break; 877 } 878 if (Features & (1 << X86::FEATURE_SSE2)) { 879 *Type = X86::INTEL_PENTIUM_M; 880 break; 881 } 882 if (Features & (1 << X86::FEATURE_SSE)) { 883 *Type = X86::INTEL_PENTIUM_III; 884 break; 885 } 886 if (Features & (1 << X86::FEATURE_MMX)) { 887 *Type = X86::INTEL_PENTIUM_II; 888 break; 889 } 890 *Type = X86::INTEL_PENTIUM_PRO; 891 break; 892 } 893 break; 894 case 15: { 895 if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { 896 *Type = X86::INTEL_NOCONA; 897 break; 898 } 899 if (Features & (1 << X86::FEATURE_SSE3)) { 900 *Type = X86::INTEL_PRESCOTT; 901 break; 902 } 903 *Type = X86::INTEL_PENTIUM_IV; 904 break; 905 } 906 default: 907 break; /*"generic"*/ 908 } 909 } 910 911 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 912 unsigned Features, unsigned *Type, 913 unsigned *Subtype) { 914 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 915 // appears to be no way to generate the wide variety of AMD-specific targets 916 // from the information returned from CPUID. 917 switch (Family) { 918 case 4: 919 *Type = X86::AMD_i486; 920 break; 921 case 5: 922 *Type = X86::AMDPENTIUM; 923 switch (Model) { 924 case 6: 925 case 7: 926 *Subtype = X86::AMDPENTIUM_K6; 927 break; // "k6" 928 case 8: 929 *Subtype = X86::AMDPENTIUM_K62; 930 break; // "k6-2" 931 case 9: 932 case 13: 933 *Subtype = X86::AMDPENTIUM_K63; 934 break; // "k6-3" 935 case 10: 936 *Subtype = X86::AMDPENTIUM_GEODE; 937 break; // "geode" 938 } 939 break; 940 case 6: 941 if (Features & (1 << X86::FEATURE_SSE)) { 942 *Type = X86::AMD_ATHLON_XP; 943 break; // "athlon-xp" 944 } 945 *Type = X86::AMD_ATHLON; 946 break; // "athlon" 947 case 15: 948 if (Features & (1 << X86::FEATURE_SSE3)) { 949 *Type = X86::AMD_K8SSE3; 950 break; // "k8-sse3" 951 } 952 *Type = X86::AMD_K8; 953 break; // "k8" 954 case 16: 955 *Type = X86::AMDFAM10H; // "amdfam10" 956 switch (Model) { 957 case 2: 958 *Subtype = X86::AMDFAM10H_BARCELONA; 959 break; 960 case 4: 961 *Subtype = X86::AMDFAM10H_SHANGHAI; 962 break; 963 case 8: 964 *Subtype = X86::AMDFAM10H_ISTANBUL; 965 break; 966 } 967 break; 968 case 20: 969 *Type = X86::AMD_BTVER1; 970 break; // "btver1"; 971 case 21: 972 *Type = X86::AMDFAM15H; 973 if (Model >= 0x60 && Model <= 0x7f) { 974 *Subtype = X86::AMDFAM15H_BDVER4; 975 break; // "bdver4"; 60h-7Fh: Excavator 976 } 977 if (Model >= 0x30 && Model <= 0x3f) { 978 *Subtype = X86::AMDFAM15H_BDVER3; 979 break; // "bdver3"; 30h-3Fh: Steamroller 980 } 981 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) { 982 *Subtype = X86::AMDFAM15H_BDVER2; 983 break; // "bdver2"; 02h, 10h-1Fh: Piledriver 984 } 985 if (Model <= 0x0f) { 986 *Subtype = X86::AMDFAM15H_BDVER1; 987 break; // "bdver1"; 00h-0Fh: Bulldozer 988 } 989 break; 990 case 22: 991 *Type = X86::AMD_BTVER2; 992 break; // "btver2" 993 case 23: 994 *Type = X86::AMDFAM17H; 995 if ((Model >= 0x30 && Model <= 0x3f) || Model == 0x71) { 996 *Subtype = X86::AMDFAM17H_ZNVER2; 997 break; // "znver2"; 30h-3fh, 71h: Zen2 998 } 999 if (Model <= 0x0f) { 1000 *Subtype = X86::AMDFAM17H_ZNVER1; 1001 break; // "znver1"; 00h-0Fh: Zen1 1002 } 1003 break; 1004 default: 1005 break; // "generic" 1006 } 1007 } 1008 1009 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 1010 unsigned *FeaturesOut, unsigned *Features2Out, 1011 unsigned *Features3Out) { 1012 unsigned Features = 0; 1013 unsigned Features2 = 0; 1014 unsigned Features3 = 0; 1015 unsigned EAX, EBX; 1016 1017 auto setFeature = [&](unsigned F) { 1018 if (F < 32) 1019 Features |= 1U << (F & 0x1f); 1020 else if (F < 64) 1021 Features2 |= 1U << ((F - 32) & 0x1f); 1022 else if (F < 96) 1023 Features3 |= 1U << ((F - 64) & 0x1f); 1024 else 1025 llvm_unreachable("Unexpected FeatureBit"); 1026 }; 1027 1028 if ((EDX >> 15) & 1) 1029 setFeature(X86::FEATURE_CMOV); 1030 if ((EDX >> 23) & 1) 1031 setFeature(X86::FEATURE_MMX); 1032 if ((EDX >> 25) & 1) 1033 setFeature(X86::FEATURE_SSE); 1034 if ((EDX >> 26) & 1) 1035 setFeature(X86::FEATURE_SSE2); 1036 1037 if ((ECX >> 0) & 1) 1038 setFeature(X86::FEATURE_SSE3); 1039 if ((ECX >> 1) & 1) 1040 setFeature(X86::FEATURE_PCLMUL); 1041 if ((ECX >> 9) & 1) 1042 setFeature(X86::FEATURE_SSSE3); 1043 if ((ECX >> 12) & 1) 1044 setFeature(X86::FEATURE_FMA); 1045 if ((ECX >> 19) & 1) 1046 setFeature(X86::FEATURE_SSE4_1); 1047 if ((ECX >> 20) & 1) 1048 setFeature(X86::FEATURE_SSE4_2); 1049 if ((ECX >> 23) & 1) 1050 setFeature(X86::FEATURE_POPCNT); 1051 if ((ECX >> 25) & 1) 1052 setFeature(X86::FEATURE_AES); 1053 1054 if ((ECX >> 22) & 1) 1055 setFeature(X86::FEATURE_MOVBE); 1056 1057 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1058 // indicates that the AVX registers will be saved and restored on context 1059 // switch, then we have full AVX support. 1060 const unsigned AVXBits = (1 << 27) | (1 << 28); 1061 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 1062 ((EAX & 0x6) == 0x6); 1063 #if defined(__APPLE__) 1064 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1065 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1066 // set right now. 1067 bool HasAVX512Save = true; 1068 #else 1069 // AVX512 requires additional context to be saved by the OS. 1070 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 1071 #endif 1072 1073 if (HasAVX) 1074 setFeature(X86::FEATURE_AVX); 1075 1076 bool HasLeaf7 = 1077 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1078 1079 if (HasLeaf7 && ((EBX >> 3) & 1)) 1080 setFeature(X86::FEATURE_BMI); 1081 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 1082 setFeature(X86::FEATURE_AVX2); 1083 if (HasLeaf7 && ((EBX >> 8) & 1)) 1084 setFeature(X86::FEATURE_BMI2); 1085 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 1086 setFeature(X86::FEATURE_AVX512F); 1087 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 1088 setFeature(X86::FEATURE_AVX512DQ); 1089 if (HasLeaf7 && ((EBX >> 19) & 1)) 1090 setFeature(X86::FEATURE_ADX); 1091 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 1092 setFeature(X86::FEATURE_AVX512IFMA); 1093 if (HasLeaf7 && ((EBX >> 23) & 1)) 1094 setFeature(X86::FEATURE_CLFLUSHOPT); 1095 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 1096 setFeature(X86::FEATURE_AVX512PF); 1097 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 1098 setFeature(X86::FEATURE_AVX512ER); 1099 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 1100 setFeature(X86::FEATURE_AVX512CD); 1101 if (HasLeaf7 && ((EBX >> 29) & 1)) 1102 setFeature(X86::FEATURE_SHA); 1103 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 1104 setFeature(X86::FEATURE_AVX512BW); 1105 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 1106 setFeature(X86::FEATURE_AVX512VL); 1107 1108 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 1109 setFeature(X86::FEATURE_AVX512VBMI); 1110 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save) 1111 setFeature(X86::FEATURE_AVX512VBMI2); 1112 if (HasLeaf7 && ((ECX >> 8) & 1)) 1113 setFeature(X86::FEATURE_GFNI); 1114 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX) 1115 setFeature(X86::FEATURE_VPCLMULQDQ); 1116 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save) 1117 setFeature(X86::FEATURE_AVX512VNNI); 1118 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save) 1119 setFeature(X86::FEATURE_AVX512BITALG); 1120 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1121 setFeature(X86::FEATURE_AVX512VPOPCNTDQ); 1122 1123 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1124 setFeature(X86::FEATURE_AVX5124VNNIW); 1125 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1126 setFeature(X86::FEATURE_AVX5124FMAPS); 1127 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save) 1128 setFeature(X86::FEATURE_AVX512VP2INTERSECT); 1129 1130 bool HasLeaf7Subleaf1 = 1131 MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1132 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save) 1133 setFeature(X86::FEATURE_AVX512BF16); 1134 1135 unsigned MaxExtLevel; 1136 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1137 1138 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1139 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1140 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1141 setFeature(X86::FEATURE_SSE4_A); 1142 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1143 setFeature(X86::FEATURE_XOP); 1144 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1145 setFeature(X86::FEATURE_FMA4); 1146 1147 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1148 setFeature(X86::FEATURE_EM64T); 1149 1150 *FeaturesOut = Features; 1151 *Features2Out = Features2; 1152 *Features3Out = Features3; 1153 } 1154 1155 StringRef sys::getHostCPUName() { 1156 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1157 unsigned MaxLeaf, Vendor; 1158 1159 if (!isCpuIdSupported()) 1160 return "generic"; 1161 1162 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) 1163 return "generic"; 1164 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1165 1166 unsigned Brand_id = EBX & 0xff; 1167 unsigned Family = 0, Model = 0; 1168 unsigned Features = 0, Features2 = 0, Features3 = 0; 1169 detectX86FamilyModel(EAX, &Family, &Model); 1170 getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2, &Features3); 1171 1172 unsigned Type = 0; 1173 unsigned Subtype = 0; 1174 1175 if (Vendor == SIG_INTEL) { 1176 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, 1177 Features2, Features3, &Type, &Subtype); 1178 } else if (Vendor == SIG_AMD) { 1179 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1180 } 1181 1182 // Check subtypes first since those are more specific. 1183 #define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \ 1184 if (Subtype == X86::ENUM) \ 1185 return ARCHNAME; 1186 #include "llvm/Support/X86TargetParser.def" 1187 1188 // Now check types. 1189 #define X86_CPU_TYPE(ARCHNAME, ENUM) \ 1190 if (Type == X86::ENUM) \ 1191 return ARCHNAME; 1192 #include "llvm/Support/X86TargetParser.def" 1193 1194 return "generic"; 1195 } 1196 1197 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1198 StringRef sys::getHostCPUName() { 1199 host_basic_info_data_t hostInfo; 1200 mach_msg_type_number_t infoCount; 1201 1202 infoCount = HOST_BASIC_INFO_COUNT; 1203 mach_port_t hostPort = mach_host_self(); 1204 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1205 &infoCount); 1206 mach_port_deallocate(mach_task_self(), hostPort); 1207 1208 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1209 return "generic"; 1210 1211 switch (hostInfo.cpu_subtype) { 1212 case CPU_SUBTYPE_POWERPC_601: 1213 return "601"; 1214 case CPU_SUBTYPE_POWERPC_602: 1215 return "602"; 1216 case CPU_SUBTYPE_POWERPC_603: 1217 return "603"; 1218 case CPU_SUBTYPE_POWERPC_603e: 1219 return "603e"; 1220 case CPU_SUBTYPE_POWERPC_603ev: 1221 return "603ev"; 1222 case CPU_SUBTYPE_POWERPC_604: 1223 return "604"; 1224 case CPU_SUBTYPE_POWERPC_604e: 1225 return "604e"; 1226 case CPU_SUBTYPE_POWERPC_620: 1227 return "620"; 1228 case CPU_SUBTYPE_POWERPC_750: 1229 return "750"; 1230 case CPU_SUBTYPE_POWERPC_7400: 1231 return "7400"; 1232 case CPU_SUBTYPE_POWERPC_7450: 1233 return "7450"; 1234 case CPU_SUBTYPE_POWERPC_970: 1235 return "970"; 1236 default:; 1237 } 1238 1239 return "generic"; 1240 } 1241 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1242 StringRef sys::getHostCPUName() { 1243 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1244 StringRef Content = P ? P->getBuffer() : ""; 1245 return detail::getHostCPUNameForPowerPC(Content); 1246 } 1247 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1248 StringRef sys::getHostCPUName() { 1249 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1250 StringRef Content = P ? P->getBuffer() : ""; 1251 return detail::getHostCPUNameForARM(Content); 1252 } 1253 #elif defined(__linux__) && defined(__s390x__) 1254 StringRef sys::getHostCPUName() { 1255 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1256 StringRef Content = P ? P->getBuffer() : ""; 1257 return detail::getHostCPUNameForS390x(Content); 1258 } 1259 #elif defined(__APPLE__) && defined(__aarch64__) 1260 StringRef sys::getHostCPUName() { 1261 return "cyclone"; 1262 } 1263 #elif defined(__APPLE__) && defined(__arm__) 1264 StringRef sys::getHostCPUName() { 1265 host_basic_info_data_t hostInfo; 1266 mach_msg_type_number_t infoCount; 1267 1268 infoCount = HOST_BASIC_INFO_COUNT; 1269 mach_port_t hostPort = mach_host_self(); 1270 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1271 &infoCount); 1272 mach_port_deallocate(mach_task_self(), hostPort); 1273 1274 if (hostInfo.cpu_type != CPU_TYPE_ARM) { 1275 assert(false && "CPUType not equal to ARM should not be possible on ARM"); 1276 return "generic"; 1277 } 1278 switch (hostInfo.cpu_subtype) { 1279 case CPU_SUBTYPE_ARM_V7S: 1280 return "swift"; 1281 default:; 1282 } 1283 1284 return "generic"; 1285 } 1286 #else 1287 StringRef sys::getHostCPUName() { return "generic"; } 1288 #endif 1289 1290 #if defined(__linux__) && (defined(__i386__) || defined(__x86_64__)) 1291 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1292 // using the number of unique physical/core id pairs. The following 1293 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1294 int computeHostNumPhysicalCores() { 1295 // Enabled represents the number of physical id/core id pairs with at least 1296 // one processor id enabled by the CPU affinity mask. 1297 cpu_set_t Affinity, Enabled; 1298 if (sched_getaffinity(0, sizeof(Affinity), &Affinity) != 0) 1299 return -1; 1300 CPU_ZERO(&Enabled); 1301 1302 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1303 // mmapped because it appears to have 0 size. 1304 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1305 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1306 if (std::error_code EC = Text.getError()) { 1307 llvm::errs() << "Can't read " 1308 << "/proc/cpuinfo: " << EC.message() << "\n"; 1309 return -1; 1310 } 1311 SmallVector<StringRef, 8> strs; 1312 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1313 /*KeepEmpty=*/false); 1314 int CurProcessor = -1; 1315 int CurPhysicalId = -1; 1316 int CurSiblings = -1; 1317 int CurCoreId = -1; 1318 for (StringRef Line : strs) { 1319 std::pair<StringRef, StringRef> Data = Line.split(':'); 1320 auto Name = Data.first.trim(); 1321 auto Val = Data.second.trim(); 1322 // These fields are available if the kernel is configured with CONFIG_SMP. 1323 if (Name == "processor") 1324 Val.getAsInteger(10, CurProcessor); 1325 else if (Name == "physical id") 1326 Val.getAsInteger(10, CurPhysicalId); 1327 else if (Name == "siblings") 1328 Val.getAsInteger(10, CurSiblings); 1329 else if (Name == "core id") { 1330 Val.getAsInteger(10, CurCoreId); 1331 // The processor id corresponds to an index into cpu_set_t. 1332 if (CPU_ISSET(CurProcessor, &Affinity)) 1333 CPU_SET(CurPhysicalId * CurSiblings + CurCoreId, &Enabled); 1334 } 1335 } 1336 return CPU_COUNT(&Enabled); 1337 } 1338 #elif defined(__APPLE__) && defined(__x86_64__) 1339 #include <sys/param.h> 1340 #include <sys/sysctl.h> 1341 1342 // Gets the number of *physical cores* on the machine. 1343 int computeHostNumPhysicalCores() { 1344 uint32_t count; 1345 size_t len = sizeof(count); 1346 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1347 if (count < 1) { 1348 int nm[2]; 1349 nm[0] = CTL_HW; 1350 nm[1] = HW_AVAILCPU; 1351 sysctl(nm, 2, &count, &len, NULL, 0); 1352 if (count < 1) 1353 return -1; 1354 } 1355 return count; 1356 } 1357 #elif defined(_WIN32) && LLVM_ENABLE_THREADS != 0 1358 // Defined in llvm/lib/Support/Windows/Threading.inc 1359 int computeHostNumPhysicalCores(); 1360 #else 1361 // On other systems, return -1 to indicate unknown. 1362 static int computeHostNumPhysicalCores() { return -1; } 1363 #endif 1364 1365 int sys::getHostNumPhysicalCores() { 1366 static int NumCores = computeHostNumPhysicalCores(); 1367 return NumCores; 1368 } 1369 1370 #if defined(__i386__) || defined(_M_IX86) || \ 1371 defined(__x86_64__) || defined(_M_X64) 1372 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1373 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1374 unsigned MaxLevel; 1375 union { 1376 unsigned u[3]; 1377 char c[12]; 1378 } text; 1379 1380 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1381 MaxLevel < 1) 1382 return false; 1383 1384 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1385 1386 Features["cx8"] = (EDX >> 8) & 1; 1387 Features["cmov"] = (EDX >> 15) & 1; 1388 Features["mmx"] = (EDX >> 23) & 1; 1389 Features["fxsr"] = (EDX >> 24) & 1; 1390 Features["sse"] = (EDX >> 25) & 1; 1391 Features["sse2"] = (EDX >> 26) & 1; 1392 1393 Features["sse3"] = (ECX >> 0) & 1; 1394 Features["pclmul"] = (ECX >> 1) & 1; 1395 Features["ssse3"] = (ECX >> 9) & 1; 1396 Features["cx16"] = (ECX >> 13) & 1; 1397 Features["sse4.1"] = (ECX >> 19) & 1; 1398 Features["sse4.2"] = (ECX >> 20) & 1; 1399 Features["movbe"] = (ECX >> 22) & 1; 1400 Features["popcnt"] = (ECX >> 23) & 1; 1401 Features["aes"] = (ECX >> 25) & 1; 1402 Features["rdrnd"] = (ECX >> 30) & 1; 1403 1404 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1405 // indicates that the AVX registers will be saved and restored on context 1406 // switch, then we have full AVX support. 1407 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1408 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1409 #if defined(__APPLE__) 1410 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1411 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1412 // set right now. 1413 bool HasAVX512Save = true; 1414 #else 1415 // AVX512 requires additional context to be saved by the OS. 1416 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1417 #endif 1418 1419 Features["avx"] = HasAVXSave; 1420 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave; 1421 // Only enable XSAVE if OS has enabled support for saving YMM state. 1422 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave; 1423 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave; 1424 1425 unsigned MaxExtLevel; 1426 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1427 1428 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1429 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1430 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1); 1431 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1432 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1433 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1434 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1435 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1436 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1437 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1438 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1439 1440 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1); 1441 1442 // Miscellaneous memory related features, detected by 1443 // using the 0x80000008 leaf of the CPUID instruction 1444 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1445 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX); 1446 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1447 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1); 1448 1449 bool HasLeaf7 = 1450 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1451 1452 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1453 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1454 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1455 // AVX2 is only supported if we have the OS save support from AVX. 1456 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave; 1457 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1458 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1459 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1460 // AVX512 is only supported if the OS supports the context save for it. 1461 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1462 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1463 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1464 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1465 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1466 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1467 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1468 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1469 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1470 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1471 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1472 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1473 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1474 1475 Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1); 1476 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1477 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1478 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1); 1479 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save; 1480 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1); 1481 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1); 1482 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave; 1483 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave; 1484 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save; 1485 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save; 1486 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1487 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1); 1488 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1); 1489 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1); 1490 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1); 1491 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1); 1492 1493 Features["avx512vp2intersect"] = 1494 HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save; 1495 Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1); 1496 Features["tsxldtrk"] = HasLeaf7 && ((EDX >> 16) & 1); 1497 // There are two CPUID leafs which information associated with the pconfig 1498 // instruction: 1499 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th 1500 // bit of EDX), while the EAX=0x1b leaf returns information on the 1501 // availability of specific pconfig leafs. 1502 // The target feature here only refers to the the first of these two. 1503 // Users might need to check for the availability of specific pconfig 1504 // leaves using cpuid, since that information is ignored while 1505 // detecting features using the "-march=native" flag. 1506 // For more info, see X86 ISA docs. 1507 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1); 1508 bool HasLeaf7Subleaf1 = 1509 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1510 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save; 1511 1512 bool HasLeafD = MaxLevel >= 0xd && 1513 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1514 1515 // Only enable XSAVE if OS has enabled support for saving YMM state. 1516 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave; 1517 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave; 1518 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave; 1519 1520 bool HasLeaf14 = MaxLevel >= 0x14 && 1521 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX); 1522 1523 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1); 1524 1525 return true; 1526 } 1527 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1528 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1529 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1530 if (!P) 1531 return false; 1532 1533 SmallVector<StringRef, 32> Lines; 1534 P->getBuffer().split(Lines, "\n"); 1535 1536 SmallVector<StringRef, 32> CPUFeatures; 1537 1538 // Look for the CPU features. 1539 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1540 if (Lines[I].startswith("Features")) { 1541 Lines[I].split(CPUFeatures, ' '); 1542 break; 1543 } 1544 1545 #if defined(__aarch64__) 1546 // Keep track of which crypto features we have seen 1547 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1548 uint32_t crypto = 0; 1549 #endif 1550 1551 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1552 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1553 #if defined(__aarch64__) 1554 .Case("asimd", "neon") 1555 .Case("fp", "fp-armv8") 1556 .Case("crc32", "crc") 1557 #else 1558 .Case("half", "fp16") 1559 .Case("neon", "neon") 1560 .Case("vfpv3", "vfp3") 1561 .Case("vfpv3d16", "d16") 1562 .Case("vfpv4", "vfp4") 1563 .Case("idiva", "hwdiv-arm") 1564 .Case("idivt", "hwdiv") 1565 #endif 1566 .Default(""); 1567 1568 #if defined(__aarch64__) 1569 // We need to check crypto separately since we need all of the crypto 1570 // extensions to enable the subtarget feature 1571 if (CPUFeatures[I] == "aes") 1572 crypto |= CAP_AES; 1573 else if (CPUFeatures[I] == "pmull") 1574 crypto |= CAP_PMULL; 1575 else if (CPUFeatures[I] == "sha1") 1576 crypto |= CAP_SHA1; 1577 else if (CPUFeatures[I] == "sha2") 1578 crypto |= CAP_SHA2; 1579 #endif 1580 1581 if (LLVMFeatureStr != "") 1582 Features[LLVMFeatureStr] = true; 1583 } 1584 1585 #if defined(__aarch64__) 1586 // If we have all crypto bits we can add the feature 1587 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1588 Features["crypto"] = true; 1589 #endif 1590 1591 return true; 1592 } 1593 #elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64)) 1594 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1595 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE)) 1596 Features["neon"] = true; 1597 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE)) 1598 Features["crc"] = true; 1599 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) 1600 Features["crypto"] = true; 1601 1602 return true; 1603 } 1604 #else 1605 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1606 #endif 1607 1608 std::string sys::getProcessTriple() { 1609 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1610 Triple PT(Triple::normalize(TargetTripleString)); 1611 1612 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1613 PT = PT.get64BitArchVariant(); 1614 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1615 PT = PT.get32BitArchVariant(); 1616 1617 return PT.str(); 1618 } 1619