1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the operating system Host concept. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/Host.h" 14 #include "llvm/ADT/SmallSet.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringMap.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/llvm-config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/X86TargetParser.h" 25 #include "llvm/Support/raw_ostream.h" 26 #include <assert.h> 27 #include <string.h> 28 29 // Include the platform-specific parts of this class. 30 #ifdef LLVM_ON_UNIX 31 #include "Unix/Host.inc" 32 #include <sched.h> 33 #endif 34 #ifdef _WIN32 35 #include "Windows/Host.inc" 36 #endif 37 #ifdef _MSC_VER 38 #include <intrin.h> 39 #endif 40 #if defined(__APPLE__) && (!defined(__x86_64__)) 41 #include <mach/host_info.h> 42 #include <mach/mach.h> 43 #include <mach/mach_host.h> 44 #include <mach/machine.h> 45 #endif 46 47 #define DEBUG_TYPE "host-detection" 48 49 //===----------------------------------------------------------------------===// 50 // 51 // Implementations of the CPU detection routines 52 // 53 //===----------------------------------------------------------------------===// 54 55 using namespace llvm; 56 57 static std::unique_ptr<llvm::MemoryBuffer> 58 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 59 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 60 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 61 if (std::error_code EC = Text.getError()) { 62 llvm::errs() << "Can't read " 63 << "/proc/cpuinfo: " << EC.message() << "\n"; 64 return nullptr; 65 } 66 return std::move(*Text); 67 } 68 69 StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) { 70 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 71 // and so we must use an operating-system interface to determine the current 72 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 73 const char *generic = "generic"; 74 75 // The cpu line is second (after the 'processor: 0' line), so if this 76 // buffer is too small then something has changed (or is wrong). 77 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 78 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 79 80 StringRef::const_iterator CIP = CPUInfoStart; 81 82 StringRef::const_iterator CPUStart = 0; 83 size_t CPULen = 0; 84 85 // We need to find the first line which starts with cpu, spaces, and a colon. 86 // After the colon, there may be some additional spaces and then the cpu type. 87 while (CIP < CPUInfoEnd && CPUStart == 0) { 88 if (CIP < CPUInfoEnd && *CIP == '\n') 89 ++CIP; 90 91 if (CIP < CPUInfoEnd && *CIP == 'c') { 92 ++CIP; 93 if (CIP < CPUInfoEnd && *CIP == 'p') { 94 ++CIP; 95 if (CIP < CPUInfoEnd && *CIP == 'u') { 96 ++CIP; 97 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 98 ++CIP; 99 100 if (CIP < CPUInfoEnd && *CIP == ':') { 101 ++CIP; 102 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 103 ++CIP; 104 105 if (CIP < CPUInfoEnd) { 106 CPUStart = CIP; 107 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 108 *CIP != ',' && *CIP != '\n')) 109 ++CIP; 110 CPULen = CIP - CPUStart; 111 } 112 } 113 } 114 } 115 } 116 117 if (CPUStart == 0) 118 while (CIP < CPUInfoEnd && *CIP != '\n') 119 ++CIP; 120 } 121 122 if (CPUStart == 0) 123 return generic; 124 125 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 126 .Case("604e", "604e") 127 .Case("604", "604") 128 .Case("7400", "7400") 129 .Case("7410", "7400") 130 .Case("7447", "7400") 131 .Case("7455", "7450") 132 .Case("G4", "g4") 133 .Case("POWER4", "970") 134 .Case("PPC970FX", "970") 135 .Case("PPC970MP", "970") 136 .Case("G5", "g5") 137 .Case("POWER5", "g5") 138 .Case("A2", "a2") 139 .Case("POWER6", "pwr6") 140 .Case("POWER7", "pwr7") 141 .Case("POWER8", "pwr8") 142 .Case("POWER8E", "pwr8") 143 .Case("POWER8NVL", "pwr8") 144 .Case("POWER9", "pwr9") 145 .Case("POWER10", "pwr10") 146 // FIXME: If we get a simulator or machine with the capabilities of 147 // mcpu=future, we should revisit this and add the name reported by the 148 // simulator/machine. 149 .Default(generic); 150 } 151 152 StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { 153 // The cpuid register on arm is not accessible from user space. On Linux, 154 // it is exposed through the /proc/cpuinfo file. 155 156 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 157 // in all cases. 158 SmallVector<StringRef, 32> Lines; 159 ProcCpuinfoContent.split(Lines, "\n"); 160 161 // Look for the CPU implementer line. 162 StringRef Implementer; 163 StringRef Hardware; 164 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 165 if (Lines[I].startswith("CPU implementer")) 166 Implementer = Lines[I].substr(15).ltrim("\t :"); 167 if (Lines[I].startswith("Hardware")) 168 Hardware = Lines[I].substr(8).ltrim("\t :"); 169 } 170 171 if (Implementer == "0x41") { // ARM Ltd. 172 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 173 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 174 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 175 return "cortex-a53"; 176 177 178 // Look for the CPU part line. 179 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 180 if (Lines[I].startswith("CPU part")) 181 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 182 // values correspond to the "Part number" in the CP15/c0 register. The 183 // contents are specified in the various processor manuals. 184 // This corresponds to the Main ID Register in Technical Reference Manuals. 185 // and is used in programs like sys-utils 186 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 187 .Case("0x926", "arm926ej-s") 188 .Case("0xb02", "mpcore") 189 .Case("0xb36", "arm1136j-s") 190 .Case("0xb56", "arm1156t2-s") 191 .Case("0xb76", "arm1176jz-s") 192 .Case("0xc08", "cortex-a8") 193 .Case("0xc09", "cortex-a9") 194 .Case("0xc0f", "cortex-a15") 195 .Case("0xc20", "cortex-m0") 196 .Case("0xc23", "cortex-m3") 197 .Case("0xc24", "cortex-m4") 198 .Case("0xd22", "cortex-m55") 199 .Case("0xd02", "cortex-a34") 200 .Case("0xd04", "cortex-a35") 201 .Case("0xd03", "cortex-a53") 202 .Case("0xd07", "cortex-a57") 203 .Case("0xd08", "cortex-a72") 204 .Case("0xd09", "cortex-a73") 205 .Case("0xd0a", "cortex-a75") 206 .Case("0xd0b", "cortex-a76") 207 .Case("0xd0c", "neoverse-n1") 208 .Default("generic"); 209 } 210 211 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium. 212 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 213 if (Lines[I].startswith("CPU part")) { 214 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 215 .Case("0x516", "thunderx2t99") 216 .Case("0x0516", "thunderx2t99") 217 .Case("0xaf", "thunderx2t99") 218 .Case("0x0af", "thunderx2t99") 219 .Case("0xa1", "thunderxt88") 220 .Case("0x0a1", "thunderxt88") 221 .Default("generic"); 222 } 223 } 224 } 225 226 if (Implementer == "0x46") { // Fujitsu Ltd. 227 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 228 if (Lines[I].startswith("CPU part")) { 229 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 230 .Case("0x001", "a64fx") 231 .Default("generic"); 232 } 233 } 234 } 235 236 if (Implementer == "0x4e") { // NVIDIA Corporation 237 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 238 if (Lines[I].startswith("CPU part")) { 239 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 240 .Case("0x004", "carmel") 241 .Default("generic"); 242 } 243 } 244 } 245 246 if (Implementer == "0x48") // HiSilicon Technologies, Inc. 247 // Look for the CPU part line. 248 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 249 if (Lines[I].startswith("CPU part")) 250 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 251 // values correspond to the "Part number" in the CP15/c0 register. The 252 // contents are specified in the various processor manuals. 253 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 254 .Case("0xd01", "tsv110") 255 .Default("generic"); 256 257 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 258 // Look for the CPU part line. 259 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 260 if (Lines[I].startswith("CPU part")) 261 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 262 // values correspond to the "Part number" in the CP15/c0 register. The 263 // contents are specified in the various processor manuals. 264 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 265 .Case("0x06f", "krait") // APQ8064 266 .Case("0x201", "kryo") 267 .Case("0x205", "kryo") 268 .Case("0x211", "kryo") 269 .Case("0x800", "cortex-a73") 270 .Case("0x801", "cortex-a73") 271 .Case("0x802", "cortex-a73") 272 .Case("0x803", "cortex-a73") 273 .Case("0x804", "cortex-a73") 274 .Case("0x805", "cortex-a73") 275 .Case("0xc00", "falkor") 276 .Case("0xc01", "saphira") 277 .Default("generic"); 278 279 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. 280 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow 281 // any predictive pattern across variants and parts. 282 unsigned Variant = 0, Part = 0; 283 284 // Look for the CPU variant line, whose value is a 1 digit hexadecimal 285 // number, corresponding to the Variant bits in the CP15/C0 register. 286 for (auto I : Lines) 287 if (I.consume_front("CPU variant")) 288 I.ltrim("\t :").getAsInteger(0, Variant); 289 290 // Look for the CPU part line, whose value is a 3 digit hexadecimal 291 // number, corresponding to the PartNum bits in the CP15/C0 register. 292 for (auto I : Lines) 293 if (I.consume_front("CPU part")) 294 I.ltrim("\t :").getAsInteger(0, Part); 295 296 unsigned Exynos = (Variant << 12) | Part; 297 switch (Exynos) { 298 default: 299 // Default by falling through to Exynos M3. 300 LLVM_FALLTHROUGH; 301 case 0x1002: 302 return "exynos-m3"; 303 case 0x1003: 304 return "exynos-m4"; 305 } 306 } 307 308 return "generic"; 309 } 310 311 StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { 312 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 313 314 // The "processor 0:" line comes after a fair amount of other information, 315 // including a cache breakdown, but this should be plenty. 316 SmallVector<StringRef, 32> Lines; 317 ProcCpuinfoContent.split(Lines, "\n"); 318 319 // Look for the CPU features. 320 SmallVector<StringRef, 32> CPUFeatures; 321 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 322 if (Lines[I].startswith("features")) { 323 size_t Pos = Lines[I].find(":"); 324 if (Pos != StringRef::npos) { 325 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 326 break; 327 } 328 } 329 330 // We need to check for the presence of vector support independently of 331 // the machine type, since we may only use the vector register set when 332 // supported by the kernel (and hypervisor). 333 bool HaveVectorSupport = false; 334 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 335 if (CPUFeatures[I] == "vx") 336 HaveVectorSupport = true; 337 } 338 339 // Now check the processor machine type. 340 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 341 if (Lines[I].startswith("processor ")) { 342 size_t Pos = Lines[I].find("machine = "); 343 if (Pos != StringRef::npos) { 344 Pos += sizeof("machine = ") - 1; 345 unsigned int Id; 346 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 347 if (Id >= 8561 && HaveVectorSupport) 348 return "z15"; 349 if (Id >= 3906 && HaveVectorSupport) 350 return "z14"; 351 if (Id >= 2964 && HaveVectorSupport) 352 return "z13"; 353 if (Id >= 2827) 354 return "zEC12"; 355 if (Id >= 2817) 356 return "z196"; 357 } 358 } 359 break; 360 } 361 } 362 363 return "generic"; 364 } 365 366 StringRef sys::detail::getHostCPUNameForBPF() { 367 #if !defined(__linux__) || !defined(__x86_64__) 368 return "generic"; 369 #else 370 uint8_t v3_insns[40] __attribute__ ((aligned (8))) = 371 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 372 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 373 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 374 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 375 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 376 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 377 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 378 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 379 /* BPF_EXIT_INSN() */ 380 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 381 382 uint8_t v2_insns[40] __attribute__ ((aligned (8))) = 383 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 384 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 385 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 386 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 387 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 388 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 389 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 390 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 391 /* BPF_EXIT_INSN() */ 392 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 393 394 struct bpf_prog_load_attr { 395 uint32_t prog_type; 396 uint32_t insn_cnt; 397 uint64_t insns; 398 uint64_t license; 399 uint32_t log_level; 400 uint32_t log_size; 401 uint64_t log_buf; 402 uint32_t kern_version; 403 uint32_t prog_flags; 404 } attr = {}; 405 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 406 attr.insn_cnt = 5; 407 attr.insns = (uint64_t)v3_insns; 408 attr.license = (uint64_t)"DUMMY"; 409 410 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, 411 sizeof(attr)); 412 if (fd >= 0) { 413 close(fd); 414 return "v3"; 415 } 416 417 /* Clear the whole attr in case its content changed by syscall. */ 418 memset(&attr, 0, sizeof(attr)); 419 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 420 attr.insn_cnt = 5; 421 attr.insns = (uint64_t)v2_insns; 422 attr.license = (uint64_t)"DUMMY"; 423 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 424 if (fd >= 0) { 425 close(fd); 426 return "v2"; 427 } 428 return "v1"; 429 #endif 430 } 431 432 #if defined(__i386__) || defined(_M_IX86) || \ 433 defined(__x86_64__) || defined(_M_X64) 434 435 enum VendorSignatures { 436 SIG_INTEL = 0x756e6547 /* Genu */, 437 SIG_AMD = 0x68747541 /* Auth */ 438 }; 439 440 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 441 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 442 // support. Consequently, for i386, the presence of CPUID is checked first 443 // via the corresponding eflags bit. 444 // Removal of cpuid.h header motivated by PR30384 445 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 446 // or test-suite, but are used in external projects e.g. libstdcxx 447 static bool isCpuIdSupported() { 448 #if defined(__GNUC__) || defined(__clang__) 449 #if defined(__i386__) 450 int __cpuid_supported; 451 __asm__(" pushfl\n" 452 " popl %%eax\n" 453 " movl %%eax,%%ecx\n" 454 " xorl $0x00200000,%%eax\n" 455 " pushl %%eax\n" 456 " popfl\n" 457 " pushfl\n" 458 " popl %%eax\n" 459 " movl $0,%0\n" 460 " cmpl %%eax,%%ecx\n" 461 " je 1f\n" 462 " movl $1,%0\n" 463 "1:" 464 : "=r"(__cpuid_supported) 465 : 466 : "eax", "ecx"); 467 if (!__cpuid_supported) 468 return false; 469 #endif 470 return true; 471 #endif 472 return true; 473 } 474 475 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 476 /// the specified arguments. If we can't run cpuid on the host, return true. 477 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 478 unsigned *rECX, unsigned *rEDX) { 479 #if defined(__GNUC__) || defined(__clang__) 480 #if defined(__x86_64__) 481 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 482 // FIXME: should we save this for Clang? 483 __asm__("movq\t%%rbx, %%rsi\n\t" 484 "cpuid\n\t" 485 "xchgq\t%%rbx, %%rsi\n\t" 486 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 487 : "a"(value)); 488 return false; 489 #elif defined(__i386__) 490 __asm__("movl\t%%ebx, %%esi\n\t" 491 "cpuid\n\t" 492 "xchgl\t%%ebx, %%esi\n\t" 493 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 494 : "a"(value)); 495 return false; 496 #else 497 return true; 498 #endif 499 #elif defined(_MSC_VER) 500 // The MSVC intrinsic is portable across x86 and x64. 501 int registers[4]; 502 __cpuid(registers, value); 503 *rEAX = registers[0]; 504 *rEBX = registers[1]; 505 *rECX = registers[2]; 506 *rEDX = registers[3]; 507 return false; 508 #else 509 return true; 510 #endif 511 } 512 513 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 514 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 515 /// return true. 516 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 517 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 518 unsigned *rEDX) { 519 #if defined(__GNUC__) || defined(__clang__) 520 #if defined(__x86_64__) 521 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 522 // FIXME: should we save this for Clang? 523 __asm__("movq\t%%rbx, %%rsi\n\t" 524 "cpuid\n\t" 525 "xchgq\t%%rbx, %%rsi\n\t" 526 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 527 : "a"(value), "c"(subleaf)); 528 return false; 529 #elif defined(__i386__) 530 __asm__("movl\t%%ebx, %%esi\n\t" 531 "cpuid\n\t" 532 "xchgl\t%%ebx, %%esi\n\t" 533 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 534 : "a"(value), "c"(subleaf)); 535 return false; 536 #else 537 return true; 538 #endif 539 #elif defined(_MSC_VER) 540 int registers[4]; 541 __cpuidex(registers, value, subleaf); 542 *rEAX = registers[0]; 543 *rEBX = registers[1]; 544 *rECX = registers[2]; 545 *rEDX = registers[3]; 546 return false; 547 #else 548 return true; 549 #endif 550 } 551 552 // Read control register 0 (XCR0). Used to detect features such as AVX. 553 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 554 #if defined(__GNUC__) || defined(__clang__) 555 // Check xgetbv; this uses a .byte sequence instead of the instruction 556 // directly because older assemblers do not include support for xgetbv and 557 // there is no easy way to conditionally compile based on the assembler used. 558 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 559 return false; 560 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 561 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 562 *rEAX = Result; 563 *rEDX = Result >> 32; 564 return false; 565 #else 566 return true; 567 #endif 568 } 569 570 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 571 unsigned *Model) { 572 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 573 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 574 if (*Family == 6 || *Family == 0xf) { 575 if (*Family == 0xf) 576 // Examine extended family ID if family ID is F. 577 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 578 // Examine extended model ID if family ID is 6 or F. 579 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 580 } 581 } 582 583 static void 584 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 585 unsigned Brand_id, unsigned Features, 586 unsigned Features2, unsigned Features3, 587 unsigned *Type, unsigned *Subtype) { 588 auto testFeature = [&](unsigned F) { 589 if (F < 32) 590 return (Features & (1U << (F & 0x1f))) != 0; 591 if (F < 64) 592 return (Features2 & (1U << ((F - 32) & 0x1f))) != 0; 593 if (F < 96) 594 return (Features3 & (1U << ((F - 64) & 0x1f))) != 0; 595 llvm_unreachable("Unexpected FeatureBit"); 596 }; 597 598 if (Brand_id != 0) 599 return; 600 switch (Family) { 601 case 3: 602 *Type = X86::INTEL_i386; 603 break; 604 case 4: 605 *Type = X86::INTEL_i486; 606 break; 607 case 5: 608 if (testFeature(X86::FEATURE_MMX)) { 609 *Type = X86::INTEL_PENTIUM_MMX; 610 break; 611 } 612 *Type = X86::INTEL_PENTIUM; 613 break; 614 case 6: 615 switch (Model) { 616 case 0x01: // Pentium Pro processor 617 *Type = X86::INTEL_PENTIUM_PRO; 618 break; 619 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 620 // model 03 621 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 622 // model 05, and Intel Celeron processor, model 05 623 case 0x06: // Celeron processor, model 06 624 *Type = X86::INTEL_PENTIUM_II; 625 break; 626 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 627 // processor, model 07 628 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 629 // model 08, and Celeron processor, model 08 630 case 0x0a: // Pentium III Xeon processor, model 0Ah 631 case 0x0b: // Pentium III processor, model 0Bh 632 *Type = X86::INTEL_PENTIUM_III; 633 break; 634 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 635 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 636 // 0Dh. All processors are manufactured using the 90 nm process. 637 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 638 // Integrated Processor with Intel QuickAssist Technology 639 *Type = X86::INTEL_PENTIUM_M; 640 break; 641 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 642 // 0Eh. All processors are manufactured using the 65 nm process. 643 *Type = X86::INTEL_CORE_DUO; 644 break; // yonah 645 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 646 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 647 // mobile processor, Intel Core 2 Extreme processor, Intel 648 // Pentium Dual-Core processor, Intel Xeon processor, model 649 // 0Fh. All processors are manufactured using the 65 nm process. 650 case 0x16: // Intel Celeron processor model 16h. All processors are 651 // manufactured using the 65 nm process 652 *Type = X86::INTEL_CORE2; // "core2" 653 *Subtype = X86::INTEL_CORE2_65; 654 break; 655 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 656 // 17h. All processors are manufactured using the 45 nm process. 657 // 658 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 659 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 660 // the 45 nm process. 661 *Type = X86::INTEL_CORE2; // "penryn" 662 *Subtype = X86::INTEL_CORE2_45; 663 break; 664 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 665 // processors are manufactured using the 45 nm process. 666 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 667 // As found in a Summer 2010 model iMac. 668 case 0x1f: 669 case 0x2e: // Nehalem EX 670 *Type = X86::INTEL_COREI7; // "nehalem" 671 *Subtype = X86::INTEL_COREI7_NEHALEM; 672 break; 673 case 0x25: // Intel Core i7, laptop version. 674 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 675 // processors are manufactured using the 32 nm process. 676 case 0x2f: // Westmere EX 677 *Type = X86::INTEL_COREI7; // "westmere" 678 *Subtype = X86::INTEL_COREI7_WESTMERE; 679 break; 680 case 0x2a: // Intel Core i7 processor. All processors are manufactured 681 // using the 32 nm process. 682 case 0x2d: 683 *Type = X86::INTEL_COREI7; //"sandybridge" 684 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 685 break; 686 case 0x3a: 687 case 0x3e: // Ivy Bridge EP 688 *Type = X86::INTEL_COREI7; // "ivybridge" 689 *Subtype = X86::INTEL_COREI7_IVYBRIDGE; 690 break; 691 692 // Haswell: 693 case 0x3c: 694 case 0x3f: 695 case 0x45: 696 case 0x46: 697 *Type = X86::INTEL_COREI7; // "haswell" 698 *Subtype = X86::INTEL_COREI7_HASWELL; 699 break; 700 701 // Broadwell: 702 case 0x3d: 703 case 0x47: 704 case 0x4f: 705 case 0x56: 706 *Type = X86::INTEL_COREI7; // "broadwell" 707 *Subtype = X86::INTEL_COREI7_BROADWELL; 708 break; 709 710 // Skylake: 711 case 0x4e: // Skylake mobile 712 case 0x5e: // Skylake desktop 713 case 0x8e: // Kaby Lake mobile 714 case 0x9e: // Kaby Lake desktop 715 case 0xa5: // Comet Lake-H/S 716 case 0xa6: // Comet Lake-U 717 *Type = X86::INTEL_COREI7; // "skylake" 718 *Subtype = X86::INTEL_COREI7_SKYLAKE; 719 break; 720 721 // Skylake Xeon: 722 case 0x55: 723 *Type = X86::INTEL_COREI7; 724 if (testFeature(X86::FEATURE_AVX512BF16)) 725 *Subtype = X86::INTEL_COREI7_COOPERLAKE; // "cooperlake" 726 else if (testFeature(X86::FEATURE_AVX512VNNI)) 727 *Subtype = X86::INTEL_COREI7_CASCADELAKE; // "cascadelake" 728 else 729 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 730 break; 731 732 // Cannonlake: 733 case 0x66: 734 *Type = X86::INTEL_COREI7; 735 *Subtype = X86::INTEL_COREI7_CANNONLAKE; // "cannonlake" 736 break; 737 738 // Icelake: 739 case 0x7d: 740 case 0x7e: 741 *Type = X86::INTEL_COREI7; 742 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; // "icelake-client" 743 break; 744 745 // Icelake Xeon: 746 case 0x6a: 747 case 0x6c: 748 *Type = X86::INTEL_COREI7; 749 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; // "icelake-server" 750 break; 751 752 case 0x1c: // Most 45 nm Intel Atom processors 753 case 0x26: // 45 nm Atom Lincroft 754 case 0x27: // 32 nm Atom Medfield 755 case 0x35: // 32 nm Atom Midview 756 case 0x36: // 32 nm Atom Midview 757 *Type = X86::INTEL_BONNELL; 758 break; // "bonnell" 759 760 // Atom Silvermont codes from the Intel software optimization guide. 761 case 0x37: 762 case 0x4a: 763 case 0x4d: 764 case 0x5a: 765 case 0x5d: 766 case 0x4c: // really airmont 767 *Type = X86::INTEL_SILVERMONT; 768 break; // "silvermont" 769 // Goldmont: 770 case 0x5c: // Apollo Lake 771 case 0x5f: // Denverton 772 *Type = X86::INTEL_GOLDMONT; 773 break; // "goldmont" 774 case 0x7a: 775 *Type = X86::INTEL_GOLDMONT_PLUS; 776 break; 777 case 0x86: 778 *Type = X86::INTEL_TREMONT; 779 break; 780 781 case 0x57: 782 *Type = X86::INTEL_KNL; // knl 783 break; 784 785 case 0x85: 786 *Type = X86::INTEL_KNM; // knm 787 break; 788 789 default: // Unknown family 6 CPU, try to guess. 790 // TODO detect tigerlake host from model 791 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) { 792 *Type = X86::INTEL_COREI7; 793 *Subtype = X86::INTEL_COREI7_TIGERLAKE; 794 break; 795 } 796 797 if (testFeature(X86::FEATURE_AVX512VBMI2)) { 798 *Type = X86::INTEL_COREI7; 799 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; 800 break; 801 } 802 803 if (testFeature(X86::FEATURE_AVX512VBMI)) { 804 *Type = X86::INTEL_COREI7; 805 *Subtype = X86::INTEL_COREI7_CANNONLAKE; 806 break; 807 } 808 809 if (testFeature(X86::FEATURE_AVX512BF16)) { 810 *Type = X86::INTEL_COREI7; 811 *Subtype = X86::INTEL_COREI7_COOPERLAKE; 812 break; 813 } 814 815 if (testFeature(X86::FEATURE_AVX512VNNI)) { 816 *Type = X86::INTEL_COREI7; 817 *Subtype = X86::INTEL_COREI7_CASCADELAKE; 818 break; 819 } 820 821 if (testFeature(X86::FEATURE_AVX512VL)) { 822 *Type = X86::INTEL_COREI7; 823 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; 824 break; 825 } 826 827 if (testFeature(X86::FEATURE_AVX512ER)) { 828 *Type = X86::INTEL_KNL; // knl 829 break; 830 } 831 832 if (testFeature(X86::FEATURE_CLFLUSHOPT)) { 833 if (testFeature(X86::FEATURE_SHA)) { 834 *Type = X86::INTEL_GOLDMONT; 835 } else { 836 *Type = X86::INTEL_COREI7; 837 *Subtype = X86::INTEL_COREI7_SKYLAKE; 838 } 839 break; 840 } 841 if (testFeature(X86::FEATURE_ADX)) { 842 *Type = X86::INTEL_COREI7; 843 *Subtype = X86::INTEL_COREI7_BROADWELL; 844 break; 845 } 846 if (testFeature(X86::FEATURE_AVX2)) { 847 *Type = X86::INTEL_COREI7; 848 *Subtype = X86::INTEL_COREI7_HASWELL; 849 break; 850 } 851 if (testFeature(X86::FEATURE_AVX)) { 852 *Type = X86::INTEL_COREI7; 853 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 854 break; 855 } 856 if (testFeature(X86::FEATURE_SSE4_2)) { 857 if (testFeature(X86::FEATURE_MOVBE)) { 858 *Type = X86::INTEL_SILVERMONT; 859 } else { 860 *Type = X86::INTEL_COREI7; 861 *Subtype = X86::INTEL_COREI7_NEHALEM; 862 } 863 break; 864 } 865 if (testFeature(X86::FEATURE_SSE4_1)) { 866 *Type = X86::INTEL_CORE2; // "penryn" 867 *Subtype = X86::INTEL_CORE2_45; 868 break; 869 } 870 if (testFeature(X86::FEATURE_SSSE3)) { 871 if (testFeature(X86::FEATURE_MOVBE)) { 872 *Type = X86::INTEL_BONNELL; // "bonnell" 873 } else { 874 *Type = X86::INTEL_CORE2; // "core2" 875 *Subtype = X86::INTEL_CORE2_65; 876 } 877 break; 878 } 879 if (testFeature(X86::FEATURE_EM64T)) { 880 *Type = X86::INTEL_CORE2; // "core2" 881 *Subtype = X86::INTEL_CORE2_65; 882 break; 883 } 884 if (testFeature(X86::FEATURE_SSE3)) { 885 *Type = X86::INTEL_CORE_DUO; 886 break; 887 } 888 if (testFeature(X86::FEATURE_SSE2)) { 889 *Type = X86::INTEL_PENTIUM_M; 890 break; 891 } 892 if (testFeature(X86::FEATURE_SSE)) { 893 *Type = X86::INTEL_PENTIUM_III; 894 break; 895 } 896 if (testFeature(X86::FEATURE_MMX)) { 897 *Type = X86::INTEL_PENTIUM_II; 898 break; 899 } 900 *Type = X86::INTEL_PENTIUM_PRO; 901 break; 902 } 903 break; 904 case 15: { 905 if (testFeature(X86::FEATURE_EM64T)) { 906 *Type = X86::INTEL_NOCONA; 907 break; 908 } 909 if (testFeature(X86::FEATURE_SSE3)) { 910 *Type = X86::INTEL_PRESCOTT; 911 break; 912 } 913 *Type = X86::INTEL_PENTIUM_IV; 914 break; 915 } 916 default: 917 break; /*"generic"*/ 918 } 919 } 920 921 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 922 unsigned Features, unsigned *Type, 923 unsigned *Subtype) { 924 auto testFeature = [&](unsigned F) { 925 if (F < 32) 926 return (Features & (1U << (F & 0x1f))) != 0; 927 llvm_unreachable("Unexpected FeatureBit"); 928 }; 929 930 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 931 // appears to be no way to generate the wide variety of AMD-specific targets 932 // from the information returned from CPUID. 933 switch (Family) { 934 case 4: 935 *Type = X86::AMD_i486; 936 break; 937 case 5: 938 *Type = X86::AMDPENTIUM; 939 switch (Model) { 940 case 6: 941 case 7: 942 *Subtype = X86::AMDPENTIUM_K6; 943 break; // "k6" 944 case 8: 945 *Subtype = X86::AMDPENTIUM_K62; 946 break; // "k6-2" 947 case 9: 948 case 13: 949 *Subtype = X86::AMDPENTIUM_K63; 950 break; // "k6-3" 951 case 10: 952 *Subtype = X86::AMDPENTIUM_GEODE; 953 break; // "geode" 954 } 955 break; 956 case 6: 957 if (testFeature(X86::FEATURE_SSE)) { 958 *Type = X86::AMD_ATHLON_XP; 959 break; // "athlon-xp" 960 } 961 *Type = X86::AMD_ATHLON; 962 break; // "athlon" 963 case 15: 964 if (testFeature(X86::FEATURE_SSE3)) { 965 *Type = X86::AMD_K8SSE3; 966 break; // "k8-sse3" 967 } 968 *Type = X86::AMD_K8; 969 break; // "k8" 970 case 16: 971 *Type = X86::AMDFAM10H; // "amdfam10" 972 switch (Model) { 973 case 2: 974 *Subtype = X86::AMDFAM10H_BARCELONA; 975 break; 976 case 4: 977 *Subtype = X86::AMDFAM10H_SHANGHAI; 978 break; 979 case 8: 980 *Subtype = X86::AMDFAM10H_ISTANBUL; 981 break; 982 } 983 break; 984 case 20: 985 *Type = X86::AMD_BTVER1; 986 break; // "btver1"; 987 case 21: 988 *Type = X86::AMDFAM15H; 989 if (Model >= 0x60 && Model <= 0x7f) { 990 *Subtype = X86::AMDFAM15H_BDVER4; 991 break; // "bdver4"; 60h-7Fh: Excavator 992 } 993 if (Model >= 0x30 && Model <= 0x3f) { 994 *Subtype = X86::AMDFAM15H_BDVER3; 995 break; // "bdver3"; 30h-3Fh: Steamroller 996 } 997 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) { 998 *Subtype = X86::AMDFAM15H_BDVER2; 999 break; // "bdver2"; 02h, 10h-1Fh: Piledriver 1000 } 1001 if (Model <= 0x0f) { 1002 *Subtype = X86::AMDFAM15H_BDVER1; 1003 break; // "bdver1"; 00h-0Fh: Bulldozer 1004 } 1005 break; 1006 case 22: 1007 *Type = X86::AMD_BTVER2; 1008 break; // "btver2" 1009 case 23: 1010 *Type = X86::AMDFAM17H; 1011 if ((Model >= 0x30 && Model <= 0x3f) || Model == 0x71) { 1012 *Subtype = X86::AMDFAM17H_ZNVER2; 1013 break; // "znver2"; 30h-3fh, 71h: Zen2 1014 } 1015 if (Model <= 0x0f) { 1016 *Subtype = X86::AMDFAM17H_ZNVER1; 1017 break; // "znver1"; 00h-0Fh: Zen1 1018 } 1019 break; 1020 default: 1021 break; // "generic" 1022 } 1023 } 1024 1025 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 1026 unsigned *FeaturesOut, unsigned *Features2Out, 1027 unsigned *Features3Out) { 1028 unsigned Features = 0; 1029 unsigned Features2 = 0; 1030 unsigned Features3 = 0; 1031 unsigned EAX, EBX; 1032 1033 auto setFeature = [&](unsigned F) { 1034 if (F < 32) 1035 Features |= 1U << (F & 0x1f); 1036 else if (F < 64) 1037 Features2 |= 1U << ((F - 32) & 0x1f); 1038 else if (F < 96) 1039 Features3 |= 1U << ((F - 64) & 0x1f); 1040 else 1041 llvm_unreachable("Unexpected FeatureBit"); 1042 }; 1043 1044 if ((EDX >> 15) & 1) 1045 setFeature(X86::FEATURE_CMOV); 1046 if ((EDX >> 23) & 1) 1047 setFeature(X86::FEATURE_MMX); 1048 if ((EDX >> 25) & 1) 1049 setFeature(X86::FEATURE_SSE); 1050 if ((EDX >> 26) & 1) 1051 setFeature(X86::FEATURE_SSE2); 1052 1053 if ((ECX >> 0) & 1) 1054 setFeature(X86::FEATURE_SSE3); 1055 if ((ECX >> 1) & 1) 1056 setFeature(X86::FEATURE_PCLMUL); 1057 if ((ECX >> 9) & 1) 1058 setFeature(X86::FEATURE_SSSE3); 1059 if ((ECX >> 12) & 1) 1060 setFeature(X86::FEATURE_FMA); 1061 if ((ECX >> 19) & 1) 1062 setFeature(X86::FEATURE_SSE4_1); 1063 if ((ECX >> 20) & 1) 1064 setFeature(X86::FEATURE_SSE4_2); 1065 if ((ECX >> 23) & 1) 1066 setFeature(X86::FEATURE_POPCNT); 1067 if ((ECX >> 25) & 1) 1068 setFeature(X86::FEATURE_AES); 1069 1070 if ((ECX >> 22) & 1) 1071 setFeature(X86::FEATURE_MOVBE); 1072 1073 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1074 // indicates that the AVX registers will be saved and restored on context 1075 // switch, then we have full AVX support. 1076 const unsigned AVXBits = (1 << 27) | (1 << 28); 1077 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 1078 ((EAX & 0x6) == 0x6); 1079 #if defined(__APPLE__) 1080 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1081 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1082 // set right now. 1083 bool HasAVX512Save = true; 1084 #else 1085 // AVX512 requires additional context to be saved by the OS. 1086 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 1087 #endif 1088 1089 if (HasAVX) 1090 setFeature(X86::FEATURE_AVX); 1091 1092 bool HasLeaf7 = 1093 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1094 1095 if (HasLeaf7 && ((EBX >> 3) & 1)) 1096 setFeature(X86::FEATURE_BMI); 1097 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 1098 setFeature(X86::FEATURE_AVX2); 1099 if (HasLeaf7 && ((EBX >> 8) & 1)) 1100 setFeature(X86::FEATURE_BMI2); 1101 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 1102 setFeature(X86::FEATURE_AVX512F); 1103 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 1104 setFeature(X86::FEATURE_AVX512DQ); 1105 if (HasLeaf7 && ((EBX >> 19) & 1)) 1106 setFeature(X86::FEATURE_ADX); 1107 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 1108 setFeature(X86::FEATURE_AVX512IFMA); 1109 if (HasLeaf7 && ((EBX >> 23) & 1)) 1110 setFeature(X86::FEATURE_CLFLUSHOPT); 1111 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 1112 setFeature(X86::FEATURE_AVX512PF); 1113 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 1114 setFeature(X86::FEATURE_AVX512ER); 1115 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 1116 setFeature(X86::FEATURE_AVX512CD); 1117 if (HasLeaf7 && ((EBX >> 29) & 1)) 1118 setFeature(X86::FEATURE_SHA); 1119 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 1120 setFeature(X86::FEATURE_AVX512BW); 1121 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 1122 setFeature(X86::FEATURE_AVX512VL); 1123 1124 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 1125 setFeature(X86::FEATURE_AVX512VBMI); 1126 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save) 1127 setFeature(X86::FEATURE_AVX512VBMI2); 1128 if (HasLeaf7 && ((ECX >> 8) & 1)) 1129 setFeature(X86::FEATURE_GFNI); 1130 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX) 1131 setFeature(X86::FEATURE_VPCLMULQDQ); 1132 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save) 1133 setFeature(X86::FEATURE_AVX512VNNI); 1134 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save) 1135 setFeature(X86::FEATURE_AVX512BITALG); 1136 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1137 setFeature(X86::FEATURE_AVX512VPOPCNTDQ); 1138 1139 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1140 setFeature(X86::FEATURE_AVX5124VNNIW); 1141 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1142 setFeature(X86::FEATURE_AVX5124FMAPS); 1143 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save) 1144 setFeature(X86::FEATURE_AVX512VP2INTERSECT); 1145 1146 bool HasLeaf7Subleaf1 = 1147 MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1148 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save) 1149 setFeature(X86::FEATURE_AVX512BF16); 1150 1151 unsigned MaxExtLevel; 1152 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1153 1154 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1155 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1156 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1157 setFeature(X86::FEATURE_SSE4_A); 1158 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1159 setFeature(X86::FEATURE_XOP); 1160 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1161 setFeature(X86::FEATURE_FMA4); 1162 1163 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1164 setFeature(X86::FEATURE_EM64T); 1165 1166 *FeaturesOut = Features; 1167 *Features2Out = Features2; 1168 *Features3Out = Features3; 1169 } 1170 1171 StringRef sys::getHostCPUName() { 1172 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1173 unsigned MaxLeaf, Vendor; 1174 1175 if (!isCpuIdSupported()) 1176 return "generic"; 1177 1178 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) 1179 return "generic"; 1180 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1181 1182 unsigned Brand_id = EBX & 0xff; 1183 unsigned Family = 0, Model = 0; 1184 unsigned Features = 0, Features2 = 0, Features3 = 0; 1185 detectX86FamilyModel(EAX, &Family, &Model); 1186 getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2, &Features3); 1187 1188 unsigned Type = 0; 1189 unsigned Subtype = 0; 1190 1191 if (Vendor == SIG_INTEL) { 1192 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, 1193 Features2, Features3, &Type, &Subtype); 1194 } else if (Vendor == SIG_AMD) { 1195 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1196 } 1197 1198 // Check subtypes first since those are more specific. 1199 #define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \ 1200 if (Subtype == X86::ENUM) \ 1201 return ARCHNAME; 1202 #include "llvm/Support/X86TargetParser.def" 1203 1204 // Now check types. 1205 #define X86_CPU_TYPE(ARCHNAME, ENUM) \ 1206 if (Type == X86::ENUM) \ 1207 return ARCHNAME; 1208 #include "llvm/Support/X86TargetParser.def" 1209 1210 return "generic"; 1211 } 1212 1213 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1214 StringRef sys::getHostCPUName() { 1215 host_basic_info_data_t hostInfo; 1216 mach_msg_type_number_t infoCount; 1217 1218 infoCount = HOST_BASIC_INFO_COUNT; 1219 mach_port_t hostPort = mach_host_self(); 1220 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1221 &infoCount); 1222 mach_port_deallocate(mach_task_self(), hostPort); 1223 1224 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1225 return "generic"; 1226 1227 switch (hostInfo.cpu_subtype) { 1228 case CPU_SUBTYPE_POWERPC_601: 1229 return "601"; 1230 case CPU_SUBTYPE_POWERPC_602: 1231 return "602"; 1232 case CPU_SUBTYPE_POWERPC_603: 1233 return "603"; 1234 case CPU_SUBTYPE_POWERPC_603e: 1235 return "603e"; 1236 case CPU_SUBTYPE_POWERPC_603ev: 1237 return "603ev"; 1238 case CPU_SUBTYPE_POWERPC_604: 1239 return "604"; 1240 case CPU_SUBTYPE_POWERPC_604e: 1241 return "604e"; 1242 case CPU_SUBTYPE_POWERPC_620: 1243 return "620"; 1244 case CPU_SUBTYPE_POWERPC_750: 1245 return "750"; 1246 case CPU_SUBTYPE_POWERPC_7400: 1247 return "7400"; 1248 case CPU_SUBTYPE_POWERPC_7450: 1249 return "7450"; 1250 case CPU_SUBTYPE_POWERPC_970: 1251 return "970"; 1252 default:; 1253 } 1254 1255 return "generic"; 1256 } 1257 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1258 StringRef sys::getHostCPUName() { 1259 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1260 StringRef Content = P ? P->getBuffer() : ""; 1261 return detail::getHostCPUNameForPowerPC(Content); 1262 } 1263 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1264 StringRef sys::getHostCPUName() { 1265 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1266 StringRef Content = P ? P->getBuffer() : ""; 1267 return detail::getHostCPUNameForARM(Content); 1268 } 1269 #elif defined(__linux__) && defined(__s390x__) 1270 StringRef sys::getHostCPUName() { 1271 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1272 StringRef Content = P ? P->getBuffer() : ""; 1273 return detail::getHostCPUNameForS390x(Content); 1274 } 1275 #elif defined(__APPLE__) && defined(__aarch64__) 1276 StringRef sys::getHostCPUName() { 1277 return "cyclone"; 1278 } 1279 #elif defined(__APPLE__) && defined(__arm__) 1280 StringRef sys::getHostCPUName() { 1281 host_basic_info_data_t hostInfo; 1282 mach_msg_type_number_t infoCount; 1283 1284 infoCount = HOST_BASIC_INFO_COUNT; 1285 mach_port_t hostPort = mach_host_self(); 1286 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1287 &infoCount); 1288 mach_port_deallocate(mach_task_self(), hostPort); 1289 1290 if (hostInfo.cpu_type != CPU_TYPE_ARM) { 1291 assert(false && "CPUType not equal to ARM should not be possible on ARM"); 1292 return "generic"; 1293 } 1294 switch (hostInfo.cpu_subtype) { 1295 case CPU_SUBTYPE_ARM_V7S: 1296 return "swift"; 1297 default:; 1298 } 1299 1300 return "generic"; 1301 } 1302 #else 1303 StringRef sys::getHostCPUName() { return "generic"; } 1304 #endif 1305 1306 #if defined(__linux__) && (defined(__i386__) || defined(__x86_64__)) 1307 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1308 // using the number of unique physical/core id pairs. The following 1309 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1310 int computeHostNumPhysicalCores() { 1311 // Enabled represents the number of physical id/core id pairs with at least 1312 // one processor id enabled by the CPU affinity mask. 1313 cpu_set_t Affinity, Enabled; 1314 if (sched_getaffinity(0, sizeof(Affinity), &Affinity) != 0) 1315 return -1; 1316 CPU_ZERO(&Enabled); 1317 1318 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1319 // mmapped because it appears to have 0 size. 1320 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1321 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1322 if (std::error_code EC = Text.getError()) { 1323 llvm::errs() << "Can't read " 1324 << "/proc/cpuinfo: " << EC.message() << "\n"; 1325 return -1; 1326 } 1327 SmallVector<StringRef, 8> strs; 1328 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1329 /*KeepEmpty=*/false); 1330 int CurProcessor = -1; 1331 int CurPhysicalId = -1; 1332 int CurSiblings = -1; 1333 int CurCoreId = -1; 1334 for (StringRef Line : strs) { 1335 std::pair<StringRef, StringRef> Data = Line.split(':'); 1336 auto Name = Data.first.trim(); 1337 auto Val = Data.second.trim(); 1338 // These fields are available if the kernel is configured with CONFIG_SMP. 1339 if (Name == "processor") 1340 Val.getAsInteger(10, CurProcessor); 1341 else if (Name == "physical id") 1342 Val.getAsInteger(10, CurPhysicalId); 1343 else if (Name == "siblings") 1344 Val.getAsInteger(10, CurSiblings); 1345 else if (Name == "core id") { 1346 Val.getAsInteger(10, CurCoreId); 1347 // The processor id corresponds to an index into cpu_set_t. 1348 if (CPU_ISSET(CurProcessor, &Affinity)) 1349 CPU_SET(CurPhysicalId * CurSiblings + CurCoreId, &Enabled); 1350 } 1351 } 1352 return CPU_COUNT(&Enabled); 1353 } 1354 #elif defined(__APPLE__) && defined(__x86_64__) 1355 #include <sys/param.h> 1356 #include <sys/sysctl.h> 1357 1358 // Gets the number of *physical cores* on the machine. 1359 int computeHostNumPhysicalCores() { 1360 uint32_t count; 1361 size_t len = sizeof(count); 1362 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1363 if (count < 1) { 1364 int nm[2]; 1365 nm[0] = CTL_HW; 1366 nm[1] = HW_AVAILCPU; 1367 sysctl(nm, 2, &count, &len, NULL, 0); 1368 if (count < 1) 1369 return -1; 1370 } 1371 return count; 1372 } 1373 #elif defined(_WIN32) && LLVM_ENABLE_THREADS != 0 1374 // Defined in llvm/lib/Support/Windows/Threading.inc 1375 int computeHostNumPhysicalCores(); 1376 #else 1377 // On other systems, return -1 to indicate unknown. 1378 static int computeHostNumPhysicalCores() { return -1; } 1379 #endif 1380 1381 int sys::getHostNumPhysicalCores() { 1382 static int NumCores = computeHostNumPhysicalCores(); 1383 return NumCores; 1384 } 1385 1386 #if defined(__i386__) || defined(_M_IX86) || \ 1387 defined(__x86_64__) || defined(_M_X64) 1388 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1389 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1390 unsigned MaxLevel; 1391 union { 1392 unsigned u[3]; 1393 char c[12]; 1394 } text; 1395 1396 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1397 MaxLevel < 1) 1398 return false; 1399 1400 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1401 1402 Features["cx8"] = (EDX >> 8) & 1; 1403 Features["cmov"] = (EDX >> 15) & 1; 1404 Features["mmx"] = (EDX >> 23) & 1; 1405 Features["fxsr"] = (EDX >> 24) & 1; 1406 Features["sse"] = (EDX >> 25) & 1; 1407 Features["sse2"] = (EDX >> 26) & 1; 1408 1409 Features["sse3"] = (ECX >> 0) & 1; 1410 Features["pclmul"] = (ECX >> 1) & 1; 1411 Features["ssse3"] = (ECX >> 9) & 1; 1412 Features["cx16"] = (ECX >> 13) & 1; 1413 Features["sse4.1"] = (ECX >> 19) & 1; 1414 Features["sse4.2"] = (ECX >> 20) & 1; 1415 Features["movbe"] = (ECX >> 22) & 1; 1416 Features["popcnt"] = (ECX >> 23) & 1; 1417 Features["aes"] = (ECX >> 25) & 1; 1418 Features["rdrnd"] = (ECX >> 30) & 1; 1419 1420 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1421 // indicates that the AVX registers will be saved and restored on context 1422 // switch, then we have full AVX support. 1423 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1424 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1425 #if defined(__APPLE__) 1426 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1427 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1428 // set right now. 1429 bool HasAVX512Save = true; 1430 #else 1431 // AVX512 requires additional context to be saved by the OS. 1432 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1433 #endif 1434 1435 Features["avx"] = HasAVXSave; 1436 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave; 1437 // Only enable XSAVE if OS has enabled support for saving YMM state. 1438 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave; 1439 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave; 1440 1441 unsigned MaxExtLevel; 1442 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1443 1444 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1445 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1446 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1); 1447 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1448 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1449 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1450 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1451 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1452 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1453 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1454 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1455 1456 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1); 1457 1458 // Miscellaneous memory related features, detected by 1459 // using the 0x80000008 leaf of the CPUID instruction 1460 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1461 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX); 1462 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1463 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1); 1464 1465 bool HasLeaf7 = 1466 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1467 1468 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1469 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1470 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1471 // AVX2 is only supported if we have the OS save support from AVX. 1472 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave; 1473 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1474 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1475 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1476 // AVX512 is only supported if the OS supports the context save for it. 1477 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1478 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1479 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1480 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1481 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1482 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1483 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1484 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1485 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1486 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1487 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1488 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1489 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1490 1491 Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1); 1492 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1493 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1494 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1); 1495 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save; 1496 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1); 1497 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1); 1498 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave; 1499 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave; 1500 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save; 1501 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save; 1502 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1503 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1); 1504 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1); 1505 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1); 1506 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1); 1507 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1); 1508 1509 Features["avx512vp2intersect"] = 1510 HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save; 1511 Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1); 1512 Features["tsxldtrk"] = HasLeaf7 && ((EDX >> 16) & 1); 1513 // There are two CPUID leafs which information associated with the pconfig 1514 // instruction: 1515 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th 1516 // bit of EDX), while the EAX=0x1b leaf returns information on the 1517 // availability of specific pconfig leafs. 1518 // The target feature here only refers to the the first of these two. 1519 // Users might need to check for the availability of specific pconfig 1520 // leaves using cpuid, since that information is ignored while 1521 // detecting features using the "-march=native" flag. 1522 // For more info, see X86 ISA docs. 1523 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1); 1524 bool HasLeaf7Subleaf1 = 1525 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1526 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save; 1527 1528 bool HasLeafD = MaxLevel >= 0xd && 1529 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1530 1531 // Only enable XSAVE if OS has enabled support for saving YMM state. 1532 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave; 1533 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave; 1534 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave; 1535 1536 bool HasLeaf14 = MaxLevel >= 0x14 && 1537 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX); 1538 1539 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1); 1540 1541 return true; 1542 } 1543 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1544 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1545 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1546 if (!P) 1547 return false; 1548 1549 SmallVector<StringRef, 32> Lines; 1550 P->getBuffer().split(Lines, "\n"); 1551 1552 SmallVector<StringRef, 32> CPUFeatures; 1553 1554 // Look for the CPU features. 1555 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1556 if (Lines[I].startswith("Features")) { 1557 Lines[I].split(CPUFeatures, ' '); 1558 break; 1559 } 1560 1561 #if defined(__aarch64__) 1562 // Keep track of which crypto features we have seen 1563 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1564 uint32_t crypto = 0; 1565 #endif 1566 1567 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1568 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1569 #if defined(__aarch64__) 1570 .Case("asimd", "neon") 1571 .Case("fp", "fp-armv8") 1572 .Case("crc32", "crc") 1573 #else 1574 .Case("half", "fp16") 1575 .Case("neon", "neon") 1576 .Case("vfpv3", "vfp3") 1577 .Case("vfpv3d16", "d16") 1578 .Case("vfpv4", "vfp4") 1579 .Case("idiva", "hwdiv-arm") 1580 .Case("idivt", "hwdiv") 1581 #endif 1582 .Default(""); 1583 1584 #if defined(__aarch64__) 1585 // We need to check crypto separately since we need all of the crypto 1586 // extensions to enable the subtarget feature 1587 if (CPUFeatures[I] == "aes") 1588 crypto |= CAP_AES; 1589 else if (CPUFeatures[I] == "pmull") 1590 crypto |= CAP_PMULL; 1591 else if (CPUFeatures[I] == "sha1") 1592 crypto |= CAP_SHA1; 1593 else if (CPUFeatures[I] == "sha2") 1594 crypto |= CAP_SHA2; 1595 #endif 1596 1597 if (LLVMFeatureStr != "") 1598 Features[LLVMFeatureStr] = true; 1599 } 1600 1601 #if defined(__aarch64__) 1602 // If we have all crypto bits we can add the feature 1603 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1604 Features["crypto"] = true; 1605 #endif 1606 1607 return true; 1608 } 1609 #elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64)) 1610 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1611 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE)) 1612 Features["neon"] = true; 1613 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE)) 1614 Features["crc"] = true; 1615 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) 1616 Features["crypto"] = true; 1617 1618 return true; 1619 } 1620 #else 1621 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1622 #endif 1623 1624 std::string sys::getProcessTriple() { 1625 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1626 Triple PT(Triple::normalize(TargetTripleString)); 1627 1628 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1629 PT = PT.get64BitArchVariant(); 1630 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1631 PT = PT.get32BitArchVariant(); 1632 1633 return PT.str(); 1634 } 1635