1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the operating system Host concept. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Support/Host.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringRef.h" 17 #include "llvm/ADT/StringSwitch.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/Config/config.h" 20 #include "llvm/Support/Debug.h" 21 #include "llvm/Support/FileSystem.h" 22 #include "llvm/Support/raw_ostream.h" 23 #include <string.h> 24 #include <assert.h> 25 26 // Include the platform-specific parts of this class. 27 #ifdef LLVM_ON_UNIX 28 #include "Unix/Host.inc" 29 #endif 30 #ifdef LLVM_ON_WIN32 31 #include "Windows/Host.inc" 32 #endif 33 #ifdef _MSC_VER 34 #include <intrin.h> 35 #endif 36 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 37 #include <mach/host_info.h> 38 #include <mach/mach.h> 39 #include <mach/mach_host.h> 40 #include <mach/machine.h> 41 #endif 42 43 #define DEBUG_TYPE "host-detection" 44 45 //===----------------------------------------------------------------------===// 46 // 47 // Implementations of the CPU detection routines 48 // 49 //===----------------------------------------------------------------------===// 50 51 using namespace llvm; 52 53 #if defined(__linux__) 54 static ssize_t LLVM_ATTRIBUTE_UNUSED readCpuInfo(void *Buf, size_t Size) { 55 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting 56 // memory buffer because the 'file' has 0 size (it can be read from only 57 // as a stream). 58 59 int FD; 60 std::error_code EC = sys::fs::openFileForRead("/proc/cpuinfo", FD); 61 if (EC) { 62 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << EC.message() << "\n"); 63 return -1; 64 } 65 int Ret = read(FD, Buf, Size); 66 int CloseStatus = close(FD); 67 if (CloseStatus) 68 return -1; 69 return Ret; 70 } 71 #endif 72 73 #if defined(__i386__) || defined(_M_IX86) || \ 74 defined(__x86_64__) || defined(_M_X64) 75 76 enum VendorSignatures { 77 SIG_INTEL = 0x756e6547 /* Genu */, 78 SIG_AMD = 0x68747541 /* Auth */ 79 }; 80 81 enum ProcessorVendors { 82 VENDOR_INTEL = 1, 83 VENDOR_AMD, 84 VENDOR_OTHER, 85 VENDOR_MAX 86 }; 87 88 enum ProcessorTypes { 89 INTEL_ATOM = 1, 90 INTEL_CORE2, 91 INTEL_COREI7, 92 AMDFAM10H, 93 AMDFAM15H, 94 INTEL_i386, 95 INTEL_i486, 96 INTEL_PENTIUM, 97 INTEL_PENTIUM_PRO, 98 INTEL_PENTIUM_II, 99 INTEL_PENTIUM_III, 100 INTEL_PENTIUM_IV, 101 INTEL_PENTIUM_M, 102 INTEL_CORE_DUO, 103 INTEL_XEONPHI, 104 INTEL_X86_64, 105 INTEL_NOCONA, 106 INTEL_PRESCOTT, 107 AMD_i486, 108 AMDPENTIUM, 109 AMDATHLON, 110 AMDFAM14H, 111 AMDFAM16H, 112 CPU_TYPE_MAX 113 }; 114 115 enum ProcessorSubtypes { 116 INTEL_COREI7_NEHALEM = 1, 117 INTEL_COREI7_WESTMERE, 118 INTEL_COREI7_SANDYBRIDGE, 119 AMDFAM10H_BARCELONA, 120 AMDFAM10H_SHANGHAI, 121 AMDFAM10H_ISTANBUL, 122 AMDFAM15H_BDVER1, 123 AMDFAM15H_BDVER2, 124 INTEL_PENTIUM_MMX, 125 INTEL_CORE2_65, 126 INTEL_CORE2_45, 127 INTEL_COREI7_IVYBRIDGE, 128 INTEL_COREI7_HASWELL, 129 INTEL_COREI7_BROADWELL, 130 INTEL_COREI7_SKYLAKE, 131 INTEL_COREI7_SKYLAKE_AVX512, 132 INTEL_ATOM_BONNELL, 133 INTEL_ATOM_SILVERMONT, 134 INTEL_KNIGHTS_LANDING, 135 AMDPENTIUM_K6, 136 AMDPENTIUM_K62, 137 AMDPENTIUM_K63, 138 AMDPENTIUM_GEODE, 139 AMDATHLON_TBIRD, 140 AMDATHLON_MP, 141 AMDATHLON_XP, 142 AMDATHLON_K8SSE3, 143 AMDATHLON_OPTERON, 144 AMDATHLON_FX, 145 AMDATHLON_64, 146 AMD_BTVER1, 147 AMD_BTVER2, 148 AMDFAM15H_BDVER3, 149 AMDFAM15H_BDVER4, 150 CPU_SUBTYPE_MAX 151 }; 152 153 enum ProcessorFeatures { 154 FEATURE_CMOV = 0, 155 FEATURE_MMX, 156 FEATURE_POPCNT, 157 FEATURE_SSE, 158 FEATURE_SSE2, 159 FEATURE_SSE3, 160 FEATURE_SSSE3, 161 FEATURE_SSE4_1, 162 FEATURE_SSE4_2, 163 FEATURE_AVX, 164 FEATURE_AVX2, 165 FEATURE_AVX512, 166 FEATURE_AVX512SAVE, 167 FEATURE_MOVBE, 168 FEATURE_ADX, 169 FEATURE_EM64T 170 }; 171 172 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 173 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 174 // support. Consequently, for i386, the presence of CPUID is checked first 175 // via the corresponding eflags bit. 176 // Removal of cpuid.h header motivated by PR30384 177 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 178 // or test-suite, but are used in external projects e.g. libstdcxx 179 static bool isCpuIdSupported() { 180 #if defined(__GNUC__) || defined(__clang__) 181 #if defined(__i386__) 182 int __cpuid_supported; 183 __asm__(" pushfl\n" 184 " popl %%eax\n" 185 " movl %%eax,%%ecx\n" 186 " xorl $0x00200000,%%eax\n" 187 " pushl %%eax\n" 188 " popfl\n" 189 " pushfl\n" 190 " popl %%eax\n" 191 " movl $0,%0\n" 192 " cmpl %%eax,%%ecx\n" 193 " je 1f\n" 194 " movl $1,%0\n" 195 "1:" 196 : "=r"(__cpuid_supported) 197 : 198 : "eax", "ecx"); 199 if (!__cpuid_supported) 200 return false; 201 #endif 202 return true; 203 #endif 204 return true; 205 } 206 207 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 208 /// the specified arguments. If we can't run cpuid on the host, return true. 209 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 210 unsigned *rECX, unsigned *rEDX) { 211 #if defined(__GNUC__) || defined(__clang__) || defined(_MSC_VER) 212 #if defined(__GNUC__) || defined(__clang__) 213 #if defined(__x86_64__) 214 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 215 // FIXME: should we save this for Clang? 216 __asm__("movq\t%%rbx, %%rsi\n\t" 217 "cpuid\n\t" 218 "xchgq\t%%rbx, %%rsi\n\t" 219 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 220 : "a"(value)); 221 #elif defined(__i386__) 222 __asm__("movl\t%%ebx, %%esi\n\t" 223 "cpuid\n\t" 224 "xchgl\t%%ebx, %%esi\n\t" 225 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 226 : "a"(value)); 227 #else 228 assert(0 && "This method is defined only for x86."); 229 #endif 230 #elif defined(_MSC_VER) 231 // The MSVC intrinsic is portable across x86 and x64. 232 int registers[4]; 233 __cpuid(registers, value); 234 *rEAX = registers[0]; 235 *rEBX = registers[1]; 236 *rECX = registers[2]; 237 *rEDX = registers[3]; 238 #endif 239 return false; 240 #else 241 return true; 242 #endif 243 } 244 245 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 246 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 247 /// return true. 248 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 249 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 250 unsigned *rEDX) { 251 #if defined(__GNUC__) || defined(__clang__) || defined(_MSC_VER) 252 #if defined(__x86_64__) || defined(_M_X64) 253 #if defined(__GNUC__) || defined(__clang__) 254 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. 255 // FIXME: should we save this for Clang? 256 __asm__("movq\t%%rbx, %%rsi\n\t" 257 "cpuid\n\t" 258 "xchgq\t%%rbx, %%rsi\n\t" 259 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 260 : "a"(value), "c"(subleaf)); 261 #elif defined(_MSC_VER) 262 int registers[4]; 263 __cpuidex(registers, value, subleaf); 264 *rEAX = registers[0]; 265 *rEBX = registers[1]; 266 *rECX = registers[2]; 267 *rEDX = registers[3]; 268 #endif 269 #elif defined(__i386__) || defined(_M_IX86) 270 #if defined(__GNUC__) || defined(__clang__) 271 __asm__("movl\t%%ebx, %%esi\n\t" 272 "cpuid\n\t" 273 "xchgl\t%%ebx, %%esi\n\t" 274 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 275 : "a"(value), "c"(subleaf)); 276 #elif defined(_MSC_VER) 277 __asm { 278 mov eax,value 279 mov ecx,subleaf 280 cpuid 281 mov esi,rEAX 282 mov dword ptr [esi],eax 283 mov esi,rEBX 284 mov dword ptr [esi],ebx 285 mov esi,rECX 286 mov dword ptr [esi],ecx 287 mov esi,rEDX 288 mov dword ptr [esi],edx 289 } 290 #endif 291 #else 292 assert(0 && "This method is defined only for x86."); 293 #endif 294 return false; 295 #else 296 return true; 297 #endif 298 } 299 300 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 301 #if defined(__GNUC__) || defined(__clang__) 302 // Check xgetbv; this uses a .byte sequence instead of the instruction 303 // directly because older assemblers do not include support for xgetbv and 304 // there is no easy way to conditionally compile based on the assembler used. 305 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 306 return false; 307 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 308 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 309 *rEAX = Result; 310 *rEDX = Result >> 32; 311 return false; 312 #else 313 return true; 314 #endif 315 } 316 317 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 318 unsigned *Model) { 319 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 320 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 321 if (*Family == 6 || *Family == 0xf) { 322 if (*Family == 0xf) 323 // Examine extended family ID if family ID is F. 324 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 325 // Examine extended model ID if family ID is 6 or F. 326 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 327 } 328 } 329 330 static void 331 getIntelProcessorTypeAndSubtype(unsigned int Family, unsigned int Model, 332 unsigned int Brand_id, unsigned int Features, 333 unsigned *Type, unsigned *Subtype) { 334 if (Brand_id != 0) 335 return; 336 switch (Family) { 337 case 3: 338 *Type = INTEL_i386; 339 break; 340 case 4: 341 switch (Model) { 342 case 0: // Intel486 DX processors 343 case 1: // Intel486 DX processors 344 case 2: // Intel486 SX processors 345 case 3: // Intel487 processors, IntelDX2 OverDrive processors, 346 // IntelDX2 processors 347 case 4: // Intel486 SL processor 348 case 5: // IntelSX2 processors 349 case 7: // Write-Back Enhanced IntelDX2 processors 350 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors 351 default: 352 *Type = INTEL_i486; 353 break; 354 } 355 break; 356 case 5: 357 switch (Model) { 358 case 1: // Pentium OverDrive processor for Pentium processor (60, 66), 359 // Pentium processors (60, 66) 360 case 2: // Pentium OverDrive processor for Pentium processor (75, 90, 361 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133, 362 // 150, 166, 200) 363 case 3: // Pentium OverDrive processors for Intel486 processor-based 364 // systems 365 *Type = INTEL_PENTIUM; 366 break; 367 case 4: // Pentium OverDrive processor with MMX technology for Pentium 368 // processor (75, 90, 100, 120, 133), Pentium processor with 369 // MMX technology (166, 200) 370 *Type = INTEL_PENTIUM; 371 *Subtype = INTEL_PENTIUM_MMX; 372 break; 373 default: 374 *Type = INTEL_PENTIUM; 375 break; 376 } 377 break; 378 case 6: 379 switch (Model) { 380 case 0x01: // Pentium Pro processor 381 *Type = INTEL_PENTIUM_PRO; 382 break; 383 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 384 // model 03 385 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 386 // model 05, and Intel Celeron processor, model 05 387 case 0x06: // Celeron processor, model 06 388 *Type = INTEL_PENTIUM_II; 389 break; 390 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 391 // processor, model 07 392 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 393 // model 08, and Celeron processor, model 08 394 case 0x0a: // Pentium III Xeon processor, model 0Ah 395 case 0x0b: // Pentium III processor, model 0Bh 396 *Type = INTEL_PENTIUM_III; 397 break; 398 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 399 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 400 // 0Dh. All processors are manufactured using the 90 nm process. 401 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 402 // Integrated Processor with Intel QuickAssist Technology 403 *Type = INTEL_PENTIUM_M; 404 break; 405 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 406 // 0Eh. All processors are manufactured using the 65 nm process. 407 *Type = INTEL_CORE_DUO; 408 break; // yonah 409 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 410 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 411 // mobile processor, Intel Core 2 Extreme processor, Intel 412 // Pentium Dual-Core processor, Intel Xeon processor, model 413 // 0Fh. All processors are manufactured using the 65 nm process. 414 case 0x16: // Intel Celeron processor model 16h. All processors are 415 // manufactured using the 65 nm process 416 *Type = INTEL_CORE2; // "core2" 417 *Subtype = INTEL_CORE2_65; 418 break; 419 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 420 // 17h. All processors are manufactured using the 45 nm process. 421 // 422 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 423 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 424 // the 45 nm process. 425 *Type = INTEL_CORE2; // "penryn" 426 *Subtype = INTEL_CORE2_45; 427 break; 428 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 429 // processors are manufactured using the 45 nm process. 430 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 431 // As found in a Summer 2010 model iMac. 432 case 0x1f: 433 case 0x2e: // Nehalem EX 434 *Type = INTEL_COREI7; // "nehalem" 435 *Subtype = INTEL_COREI7_NEHALEM; 436 break; 437 case 0x25: // Intel Core i7, laptop version. 438 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 439 // processors are manufactured using the 32 nm process. 440 case 0x2f: // Westmere EX 441 *Type = INTEL_COREI7; // "westmere" 442 *Subtype = INTEL_COREI7_WESTMERE; 443 break; 444 case 0x2a: // Intel Core i7 processor. All processors are manufactured 445 // using the 32 nm process. 446 case 0x2d: 447 *Type = INTEL_COREI7; //"sandybridge" 448 *Subtype = INTEL_COREI7_SANDYBRIDGE; 449 break; 450 case 0x3a: 451 case 0x3e: // Ivy Bridge EP 452 *Type = INTEL_COREI7; // "ivybridge" 453 *Subtype = INTEL_COREI7_IVYBRIDGE; 454 break; 455 456 // Haswell: 457 case 0x3c: 458 case 0x3f: 459 case 0x45: 460 case 0x46: 461 *Type = INTEL_COREI7; // "haswell" 462 *Subtype = INTEL_COREI7_HASWELL; 463 break; 464 465 // Broadwell: 466 case 0x3d: 467 case 0x47: 468 case 0x4f: 469 case 0x56: 470 *Type = INTEL_COREI7; // "broadwell" 471 *Subtype = INTEL_COREI7_BROADWELL; 472 break; 473 474 // Skylake: 475 case 0x4e: 476 *Type = INTEL_COREI7; // "skylake-avx512" 477 *Subtype = INTEL_COREI7_SKYLAKE_AVX512; 478 break; 479 case 0x5e: 480 *Type = INTEL_COREI7; // "skylake" 481 *Subtype = INTEL_COREI7_SKYLAKE; 482 break; 483 484 case 0x1c: // Most 45 nm Intel Atom processors 485 case 0x26: // 45 nm Atom Lincroft 486 case 0x27: // 32 nm Atom Medfield 487 case 0x35: // 32 nm Atom Midview 488 case 0x36: // 32 nm Atom Midview 489 *Type = INTEL_ATOM; 490 *Subtype = INTEL_ATOM_BONNELL; 491 break; // "bonnell" 492 493 // Atom Silvermont codes from the Intel software optimization guide. 494 case 0x37: 495 case 0x4a: 496 case 0x4d: 497 case 0x5a: 498 case 0x5d: 499 case 0x4c: // really airmont 500 *Type = INTEL_ATOM; 501 *Subtype = INTEL_ATOM_SILVERMONT; 502 break; // "silvermont" 503 504 case 0x57: 505 *Type = INTEL_XEONPHI; // knl 506 *Subtype = INTEL_KNIGHTS_LANDING; 507 break; 508 509 default: // Unknown family 6 CPU, try to guess. 510 if (Features & (1 << FEATURE_AVX512)) { 511 *Type = INTEL_XEONPHI; // knl 512 *Subtype = INTEL_KNIGHTS_LANDING; 513 break; 514 } 515 if (Features & (1 << FEATURE_ADX)) { 516 *Type = INTEL_COREI7; 517 *Subtype = INTEL_COREI7_BROADWELL; 518 break; 519 } 520 if (Features & (1 << FEATURE_AVX2)) { 521 *Type = INTEL_COREI7; 522 *Subtype = INTEL_COREI7_HASWELL; 523 break; 524 } 525 if (Features & (1 << FEATURE_AVX)) { 526 *Type = INTEL_COREI7; 527 *Subtype = INTEL_COREI7_SANDYBRIDGE; 528 break; 529 } 530 if (Features & (1 << FEATURE_SSE4_2)) { 531 if (Features & (1 << FEATURE_MOVBE)) { 532 *Type = INTEL_ATOM; 533 *Subtype = INTEL_ATOM_SILVERMONT; 534 } else { 535 *Type = INTEL_COREI7; 536 *Subtype = INTEL_COREI7_NEHALEM; 537 } 538 break; 539 } 540 if (Features & (1 << FEATURE_SSE4_1)) { 541 *Type = INTEL_CORE2; // "penryn" 542 *Subtype = INTEL_CORE2_45; 543 break; 544 } 545 if (Features & (1 << FEATURE_SSSE3)) { 546 if (Features & (1 << FEATURE_MOVBE)) { 547 *Type = INTEL_ATOM; 548 *Subtype = INTEL_ATOM_BONNELL; // "bonnell" 549 } else { 550 *Type = INTEL_CORE2; // "core2" 551 *Subtype = INTEL_CORE2_65; 552 } 553 break; 554 } 555 if (Features & (1 << FEATURE_EM64T)) { 556 *Type = INTEL_X86_64; 557 break; // x86-64 558 } 559 if (Features & (1 << FEATURE_SSE2)) { 560 *Type = INTEL_PENTIUM_M; 561 break; 562 } 563 if (Features & (1 << FEATURE_SSE)) { 564 *Type = INTEL_PENTIUM_III; 565 break; 566 } 567 if (Features & (1 << FEATURE_MMX)) { 568 *Type = INTEL_PENTIUM_II; 569 break; 570 } 571 *Type = INTEL_PENTIUM_PRO; 572 break; 573 } 574 break; 575 case 15: { 576 switch (Model) { 577 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are 578 // model 00h and manufactured using the 0.18 micron process. 579 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon 580 // processor MP, and Intel Celeron processor. All processors are 581 // model 01h and manufactured using the 0.18 micron process. 582 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M, 583 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron 584 // processor, and Mobile Intel Celeron processor. All processors 585 // are model 02h and manufactured using the 0.13 micron process. 586 *Type = 587 ((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV); 588 break; 589 590 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D 591 // processor. All processors are model 03h and manufactured using 592 // the 90 nm process. 593 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition, 594 // Pentium D processor, Intel Xeon processor, Intel Xeon 595 // processor MP, Intel Celeron D processor. All processors are 596 // model 04h and manufactured using the 90 nm process. 597 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor 598 // Extreme Edition, Intel Xeon processor, Intel Xeon processor 599 // MP, Intel Celeron D processor. All processors are model 06h 600 // and manufactured using the 65 nm process. 601 *Type = 602 ((Features & (1 << FEATURE_EM64T)) ? INTEL_NOCONA : INTEL_PRESCOTT); 603 break; 604 605 default: 606 *Type = 607 ((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV); 608 break; 609 } 610 break; 611 } 612 default: 613 break; /*"generic"*/ 614 } 615 } 616 617 static void getAMDProcessorTypeAndSubtype(unsigned int Family, 618 unsigned int Model, 619 unsigned int Features, 620 unsigned *Type, 621 unsigned *Subtype) { 622 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 623 // appears to be no way to generate the wide variety of AMD-specific targets 624 // from the information returned from CPUID. 625 switch (Family) { 626 case 4: 627 *Type = AMD_i486; 628 break; 629 case 5: 630 *Type = AMDPENTIUM; 631 switch (Model) { 632 case 6: 633 case 7: 634 *Subtype = AMDPENTIUM_K6; 635 break; // "k6" 636 case 8: 637 *Subtype = AMDPENTIUM_K62; 638 break; // "k6-2" 639 case 9: 640 case 13: 641 *Subtype = AMDPENTIUM_K63; 642 break; // "k6-3" 643 case 10: 644 *Subtype = AMDPENTIUM_GEODE; 645 break; // "geode" 646 } 647 break; 648 case 6: 649 *Type = AMDATHLON; 650 switch (Model) { 651 case 4: 652 *Subtype = AMDATHLON_TBIRD; 653 break; // "athlon-tbird" 654 case 6: 655 case 7: 656 case 8: 657 *Subtype = AMDATHLON_MP; 658 break; // "athlon-mp" 659 case 10: 660 *Subtype = AMDATHLON_XP; 661 break; // "athlon-xp" 662 } 663 break; 664 case 15: 665 *Type = AMDATHLON; 666 if (Features & (1 << FEATURE_SSE3)) { 667 *Subtype = AMDATHLON_K8SSE3; 668 break; // "k8-sse3" 669 } 670 switch (Model) { 671 case 1: 672 *Subtype = AMDATHLON_OPTERON; 673 break; // "opteron" 674 case 5: 675 *Subtype = AMDATHLON_FX; 676 break; // "athlon-fx"; also opteron 677 default: 678 *Subtype = AMDATHLON_64; 679 break; // "athlon64" 680 } 681 break; 682 case 16: 683 *Type = AMDFAM10H; // "amdfam10" 684 switch (Model) { 685 case 2: 686 *Subtype = AMDFAM10H_BARCELONA; 687 break; 688 case 4: 689 *Subtype = AMDFAM10H_SHANGHAI; 690 break; 691 case 8: 692 *Subtype = AMDFAM10H_ISTANBUL; 693 break; 694 } 695 break; 696 case 20: 697 *Type = AMDFAM14H; 698 *Subtype = AMD_BTVER1; 699 break; // "btver1"; 700 case 21: 701 *Type = AMDFAM15H; 702 if (!(Features & 703 (1 << FEATURE_AVX))) { // If no AVX support, provide a sane fallback. 704 *Subtype = AMD_BTVER1; 705 break; // "btver1" 706 } 707 if (Model >= 0x50 && Model <= 0x6f) { 708 *Subtype = AMDFAM15H_BDVER4; 709 break; // "bdver4"; 50h-6Fh: Excavator 710 } 711 if (Model >= 0x30 && Model <= 0x3f) { 712 *Subtype = AMDFAM15H_BDVER3; 713 break; // "bdver3"; 30h-3Fh: Steamroller 714 } 715 if (Model >= 0x10 && Model <= 0x1f) { 716 *Subtype = AMDFAM15H_BDVER2; 717 break; // "bdver2"; 10h-1Fh: Piledriver 718 } 719 if (Model <= 0x0f) { 720 *Subtype = AMDFAM15H_BDVER1; 721 break; // "bdver1"; 00h-0Fh: Bulldozer 722 } 723 break; 724 case 22: 725 *Type = AMDFAM16H; 726 if (!(Features & 727 (1 << FEATURE_AVX))) { // If no AVX support provide a sane fallback. 728 *Subtype = AMD_BTVER1; 729 break; // "btver1"; 730 } 731 *Subtype = AMD_BTVER2; 732 break; // "btver2" 733 default: 734 break; // "generic" 735 } 736 } 737 738 static unsigned getAvailableFeatures(unsigned int ECX, unsigned int EDX, 739 unsigned MaxLeaf) { 740 unsigned Features = 0; 741 unsigned int EAX, EBX; 742 Features |= (((EDX >> 23) & 1) << FEATURE_MMX); 743 Features |= (((EDX >> 25) & 1) << FEATURE_SSE); 744 Features |= (((EDX >> 26) & 1) << FEATURE_SSE2); 745 Features |= (((ECX >> 0) & 1) << FEATURE_SSE3); 746 Features |= (((ECX >> 9) & 1) << FEATURE_SSSE3); 747 Features |= (((ECX >> 19) & 1) << FEATURE_SSE4_1); 748 Features |= (((ECX >> 20) & 1) << FEATURE_SSE4_2); 749 Features |= (((ECX >> 22) & 1) << FEATURE_MOVBE); 750 751 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 752 // indicates that the AVX registers will be saved and restored on context 753 // switch, then we have full AVX support. 754 const unsigned AVXBits = (1 << 27) | (1 << 28); 755 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 756 ((EAX & 0x6) == 0x6); 757 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 758 bool HasLeaf7 = 759 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 760 bool HasADX = HasLeaf7 && ((EBX >> 19) & 1); 761 bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20); 762 bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1); 763 Features |= (HasAVX << FEATURE_AVX); 764 Features |= (HasAVX2 << FEATURE_AVX2); 765 Features |= (HasAVX512 << FEATURE_AVX512); 766 Features |= (HasAVX512Save << FEATURE_AVX512SAVE); 767 Features |= (HasADX << FEATURE_ADX); 768 769 getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 770 Features |= (((EDX >> 29) & 0x1) << FEATURE_EM64T); 771 return Features; 772 } 773 774 StringRef sys::getHostCPUName() { 775 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 776 unsigned MaxLeaf, Vendor; 777 778 #if defined(__GNUC__) || defined(__clang__) 779 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here 780 // and simplify it to not invoke __cpuid (like cpu_model.c in 781 // compiler-rt/lib/builtins/cpu_model.c? 782 // Opting for the second option. 783 if(!isCpuIdSupported()) 784 return "generic"; 785 #endif 786 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX)) 787 return "generic"; 788 if (getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX)) 789 return "generic"; 790 791 unsigned Brand_id = EBX & 0xff; 792 unsigned Family = 0, Model = 0; 793 unsigned Features = 0; 794 detectX86FamilyModel(EAX, &Family, &Model); 795 Features = getAvailableFeatures(ECX, EDX, MaxLeaf); 796 797 unsigned Type; 798 unsigned Subtype; 799 800 if (Vendor == SIG_INTEL) { 801 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, &Type, 802 &Subtype); 803 switch (Type) { 804 case INTEL_i386: 805 return "i386"; 806 case INTEL_i486: 807 return "i486"; 808 case INTEL_PENTIUM: 809 if (Subtype == INTEL_PENTIUM_MMX) 810 return "pentium-mmx"; 811 return "pentium"; 812 case INTEL_PENTIUM_PRO: 813 return "pentiumpro"; 814 case INTEL_PENTIUM_II: 815 return "pentium2"; 816 case INTEL_PENTIUM_III: 817 return "pentium3"; 818 case INTEL_PENTIUM_IV: 819 return "pentium4"; 820 case INTEL_PENTIUM_M: 821 return "pentium-m"; 822 case INTEL_CORE_DUO: 823 return "yonah"; 824 case INTEL_CORE2: 825 switch (Subtype) { 826 case INTEL_CORE2_65: 827 return "core2"; 828 case INTEL_CORE2_45: 829 return "penryn"; 830 default: 831 return "core2"; 832 } 833 case INTEL_COREI7: 834 switch (Subtype) { 835 case INTEL_COREI7_NEHALEM: 836 return "nehalem"; 837 case INTEL_COREI7_WESTMERE: 838 return "westmere"; 839 case INTEL_COREI7_SANDYBRIDGE: 840 return "sandybridge"; 841 case INTEL_COREI7_IVYBRIDGE: 842 return "ivybridge"; 843 case INTEL_COREI7_HASWELL: 844 return "haswell"; 845 case INTEL_COREI7_BROADWELL: 846 return "broadwell"; 847 case INTEL_COREI7_SKYLAKE: 848 return "skylake"; 849 case INTEL_COREI7_SKYLAKE_AVX512: 850 return "skylake-avx512"; 851 default: 852 return "corei7"; 853 } 854 case INTEL_ATOM: 855 switch (Subtype) { 856 case INTEL_ATOM_BONNELL: 857 return "bonnell"; 858 case INTEL_ATOM_SILVERMONT: 859 return "silvermont"; 860 default: 861 return "atom"; 862 } 863 case INTEL_XEONPHI: 864 return "knl"; /*update for more variants added*/ 865 case INTEL_X86_64: 866 return "x86-64"; 867 case INTEL_NOCONA: 868 return "nocona"; 869 case INTEL_PRESCOTT: 870 return "prescott"; 871 default: 872 return "generic"; 873 } 874 } else if (Vendor == SIG_AMD) { 875 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 876 switch (Type) { 877 case AMD_i486: 878 return "i486"; 879 case AMDPENTIUM: 880 switch (Subtype) { 881 case AMDPENTIUM_K6: 882 return "k6"; 883 case AMDPENTIUM_K62: 884 return "k6-2"; 885 case AMDPENTIUM_K63: 886 return "k6-3"; 887 case AMDPENTIUM_GEODE: 888 return "geode"; 889 default: 890 return "pentium"; 891 } 892 case AMDATHLON: 893 switch (Subtype) { 894 case AMDATHLON_TBIRD: 895 return "athlon-tbird"; 896 case AMDATHLON_MP: 897 return "athlon-mp"; 898 case AMDATHLON_XP: 899 return "athlon-xp"; 900 case AMDATHLON_K8SSE3: 901 return "k8-sse3"; 902 case AMDATHLON_OPTERON: 903 return "opteron"; 904 case AMDATHLON_FX: 905 return "athlon-fx"; 906 case AMDATHLON_64: 907 return "athlon64"; 908 default: 909 return "athlon"; 910 } 911 case AMDFAM10H: 912 if(Subtype == AMDFAM10H_BARCELONA) 913 return "barcelona"; 914 return "amdfam10"; 915 case AMDFAM14H: 916 return "btver1"; 917 case AMDFAM15H: 918 switch (Subtype) { 919 case AMDFAM15H_BDVER1: 920 return "bdver1"; 921 case AMDFAM15H_BDVER2: 922 return "bdver2"; 923 case AMDFAM15H_BDVER3: 924 return "bdver3"; 925 case AMDFAM15H_BDVER4: 926 return "bdver4"; 927 case AMD_BTVER1: 928 return "btver1"; 929 default: 930 return "amdfam15"; 931 } 932 case AMDFAM16H: 933 switch (Subtype) { 934 case AMD_BTVER1: 935 return "btver1"; 936 case AMD_BTVER2: 937 return "btver2"; 938 default: 939 return "amdfam16"; 940 } 941 default: 942 return "generic"; 943 } 944 } 945 return "generic"; 946 } 947 948 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 949 StringRef sys::getHostCPUName() { 950 host_basic_info_data_t hostInfo; 951 mach_msg_type_number_t infoCount; 952 953 infoCount = HOST_BASIC_INFO_COUNT; 954 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo, 955 &infoCount); 956 957 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 958 return "generic"; 959 960 switch (hostInfo.cpu_subtype) { 961 case CPU_SUBTYPE_POWERPC_601: 962 return "601"; 963 case CPU_SUBTYPE_POWERPC_602: 964 return "602"; 965 case CPU_SUBTYPE_POWERPC_603: 966 return "603"; 967 case CPU_SUBTYPE_POWERPC_603e: 968 return "603e"; 969 case CPU_SUBTYPE_POWERPC_603ev: 970 return "603ev"; 971 case CPU_SUBTYPE_POWERPC_604: 972 return "604"; 973 case CPU_SUBTYPE_POWERPC_604e: 974 return "604e"; 975 case CPU_SUBTYPE_POWERPC_620: 976 return "620"; 977 case CPU_SUBTYPE_POWERPC_750: 978 return "750"; 979 case CPU_SUBTYPE_POWERPC_7400: 980 return "7400"; 981 case CPU_SUBTYPE_POWERPC_7450: 982 return "7450"; 983 case CPU_SUBTYPE_POWERPC_970: 984 return "970"; 985 default:; 986 } 987 988 return "generic"; 989 } 990 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 991 StringRef sys::getHostCPUName() { 992 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 993 // and so we must use an operating-system interface to determine the current 994 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 995 const char *generic = "generic"; 996 997 // The cpu line is second (after the 'processor: 0' line), so if this 998 // buffer is too small then something has changed (or is wrong). 999 char buffer[1024]; 1000 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer)); 1001 if (CPUInfoSize == -1) 1002 return generic; 1003 1004 const char *CPUInfoStart = buffer; 1005 const char *CPUInfoEnd = buffer + CPUInfoSize; 1006 1007 const char *CIP = CPUInfoStart; 1008 1009 const char *CPUStart = 0; 1010 size_t CPULen = 0; 1011 1012 // We need to find the first line which starts with cpu, spaces, and a colon. 1013 // After the colon, there may be some additional spaces and then the cpu type. 1014 while (CIP < CPUInfoEnd && CPUStart == 0) { 1015 if (CIP < CPUInfoEnd && *CIP == '\n') 1016 ++CIP; 1017 1018 if (CIP < CPUInfoEnd && *CIP == 'c') { 1019 ++CIP; 1020 if (CIP < CPUInfoEnd && *CIP == 'p') { 1021 ++CIP; 1022 if (CIP < CPUInfoEnd && *CIP == 'u') { 1023 ++CIP; 1024 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 1025 ++CIP; 1026 1027 if (CIP < CPUInfoEnd && *CIP == ':') { 1028 ++CIP; 1029 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 1030 ++CIP; 1031 1032 if (CIP < CPUInfoEnd) { 1033 CPUStart = CIP; 1034 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 1035 *CIP != ',' && *CIP != '\n')) 1036 ++CIP; 1037 CPULen = CIP - CPUStart; 1038 } 1039 } 1040 } 1041 } 1042 } 1043 1044 if (CPUStart == 0) 1045 while (CIP < CPUInfoEnd && *CIP != '\n') 1046 ++CIP; 1047 } 1048 1049 if (CPUStart == 0) 1050 return generic; 1051 1052 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 1053 .Case("604e", "604e") 1054 .Case("604", "604") 1055 .Case("7400", "7400") 1056 .Case("7410", "7400") 1057 .Case("7447", "7400") 1058 .Case("7455", "7450") 1059 .Case("G4", "g4") 1060 .Case("POWER4", "970") 1061 .Case("PPC970FX", "970") 1062 .Case("PPC970MP", "970") 1063 .Case("G5", "g5") 1064 .Case("POWER5", "g5") 1065 .Case("A2", "a2") 1066 .Case("POWER6", "pwr6") 1067 .Case("POWER7", "pwr7") 1068 .Case("POWER8", "pwr8") 1069 .Case("POWER8E", "pwr8") 1070 .Case("POWER9", "pwr9") 1071 .Default(generic); 1072 } 1073 #elif defined(__linux__) && defined(__arm__) 1074 StringRef sys::getHostCPUName() { 1075 // The cpuid register on arm is not accessible from user space. On Linux, 1076 // it is exposed through the /proc/cpuinfo file. 1077 1078 // Read 1024 bytes from /proc/cpuinfo, which should contain the CPU part line 1079 // in all cases. 1080 char buffer[1024]; 1081 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer)); 1082 if (CPUInfoSize == -1) 1083 return "generic"; 1084 1085 StringRef Str(buffer, CPUInfoSize); 1086 1087 SmallVector<StringRef, 32> Lines; 1088 Str.split(Lines, "\n"); 1089 1090 // Look for the CPU implementer line. 1091 StringRef Implementer; 1092 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1093 if (Lines[I].startswith("CPU implementer")) 1094 Implementer = Lines[I].substr(15).ltrim("\t :"); 1095 1096 if (Implementer == "0x41") // ARM Ltd. 1097 // Look for the CPU part line. 1098 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1099 if (Lines[I].startswith("CPU part")) 1100 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 1101 // values correspond to the "Part number" in the CP15/c0 register. The 1102 // contents are specified in the various processor manuals. 1103 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 1104 .Case("0x926", "arm926ej-s") 1105 .Case("0xb02", "mpcore") 1106 .Case("0xb36", "arm1136j-s") 1107 .Case("0xb56", "arm1156t2-s") 1108 .Case("0xb76", "arm1176jz-s") 1109 .Case("0xc08", "cortex-a8") 1110 .Case("0xc09", "cortex-a9") 1111 .Case("0xc0f", "cortex-a15") 1112 .Case("0xc20", "cortex-m0") 1113 .Case("0xc23", "cortex-m3") 1114 .Case("0xc24", "cortex-m4") 1115 .Default("generic"); 1116 1117 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 1118 // Look for the CPU part line. 1119 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1120 if (Lines[I].startswith("CPU part")) 1121 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 1122 // values correspond to the "Part number" in the CP15/c0 register. The 1123 // contents are specified in the various processor manuals. 1124 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 1125 .Case("0x06f", "krait") // APQ8064 1126 .Default("generic"); 1127 1128 return "generic"; 1129 } 1130 #elif defined(__linux__) && defined(__s390x__) 1131 StringRef sys::getHostCPUName() { 1132 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 1133 1134 // The "processor 0:" line comes after a fair amount of other information, 1135 // including a cache breakdown, but this should be plenty. 1136 char buffer[2048]; 1137 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer)); 1138 if (CPUInfoSize == -1) 1139 return "generic"; 1140 1141 StringRef Str(buffer, CPUInfoSize); 1142 SmallVector<StringRef, 32> Lines; 1143 Str.split(Lines, "\n"); 1144 1145 // Look for the CPU features. 1146 SmallVector<StringRef, 32> CPUFeatures; 1147 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1148 if (Lines[I].startswith("features")) { 1149 size_t Pos = Lines[I].find(":"); 1150 if (Pos != StringRef::npos) { 1151 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 1152 break; 1153 } 1154 } 1155 1156 // We need to check for the presence of vector support independently of 1157 // the machine type, since we may only use the vector register set when 1158 // supported by the kernel (and hypervisor). 1159 bool HaveVectorSupport = false; 1160 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1161 if (CPUFeatures[I] == "vx") 1162 HaveVectorSupport = true; 1163 } 1164 1165 // Now check the processor machine type. 1166 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 1167 if (Lines[I].startswith("processor ")) { 1168 size_t Pos = Lines[I].find("machine = "); 1169 if (Pos != StringRef::npos) { 1170 Pos += sizeof("machine = ") - 1; 1171 unsigned int Id; 1172 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 1173 if (Id >= 2964 && HaveVectorSupport) 1174 return "z13"; 1175 if (Id >= 2827) 1176 return "zEC12"; 1177 if (Id >= 2817) 1178 return "z196"; 1179 } 1180 } 1181 break; 1182 } 1183 } 1184 1185 return "generic"; 1186 } 1187 #else 1188 StringRef sys::getHostCPUName() { return "generic"; } 1189 #endif 1190 1191 #if defined(__i386__) || defined(_M_IX86) || \ 1192 defined(__x86_64__) || defined(_M_X64) 1193 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1194 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1195 unsigned MaxLevel; 1196 union { 1197 unsigned u[3]; 1198 char c[12]; 1199 } text; 1200 1201 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1202 MaxLevel < 1) 1203 return false; 1204 1205 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1206 1207 Features["cmov"] = (EDX >> 15) & 1; 1208 Features["mmx"] = (EDX >> 23) & 1; 1209 Features["sse"] = (EDX >> 25) & 1; 1210 Features["sse2"] = (EDX >> 26) & 1; 1211 Features["sse3"] = (ECX >> 0) & 1; 1212 Features["ssse3"] = (ECX >> 9) & 1; 1213 Features["sse4.1"] = (ECX >> 19) & 1; 1214 Features["sse4.2"] = (ECX >> 20) & 1; 1215 1216 Features["pclmul"] = (ECX >> 1) & 1; 1217 Features["cx16"] = (ECX >> 13) & 1; 1218 Features["movbe"] = (ECX >> 22) & 1; 1219 Features["popcnt"] = (ECX >> 23) & 1; 1220 Features["aes"] = (ECX >> 25) & 1; 1221 Features["rdrnd"] = (ECX >> 30) & 1; 1222 1223 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1224 // indicates that the AVX registers will be saved and restored on context 1225 // switch, then we have full AVX support. 1226 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1227 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1228 Features["avx"] = HasAVXSave; 1229 Features["fma"] = HasAVXSave && (ECX >> 12) & 1; 1230 Features["f16c"] = HasAVXSave && (ECX >> 29) & 1; 1231 1232 // Only enable XSAVE if OS has enabled support for saving YMM state. 1233 Features["xsave"] = HasAVXSave && (ECX >> 26) & 1; 1234 1235 // AVX512 requires additional context to be saved by the OS. 1236 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1237 1238 unsigned MaxExtLevel; 1239 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1240 1241 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1242 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1243 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1244 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1245 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1246 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1247 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1248 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1249 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1250 1251 bool HasLeaf7 = 1252 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1253 1254 // AVX2 is only supported if we have the OS save support from AVX. 1255 Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1); 1256 1257 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1258 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1259 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1260 Features["hle"] = HasLeaf7 && ((EBX >> 4) & 1); 1261 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1262 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1263 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1264 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1265 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1266 Features["smap"] = HasLeaf7 && ((EBX >> 20) & 1); 1267 Features["pcommit"] = HasLeaf7 && ((EBX >> 22) & 1); 1268 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1269 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1270 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1271 1272 // AVX512 is only supported if the OS supports the context save for it. 1273 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1274 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1275 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1276 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1277 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1278 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1279 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1280 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1281 1282 Features["prefetchwt1"] = HasLeaf7 && (ECX & 1); 1283 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1284 // Enable protection keys 1285 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1286 1287 bool HasLeafD = MaxLevel >= 0xd && 1288 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1289 1290 // Only enable XSAVE if OS has enabled support for saving YMM state. 1291 Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1); 1292 Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1); 1293 Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1); 1294 1295 return true; 1296 } 1297 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1298 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1299 // Read 1024 bytes from /proc/cpuinfo, which should contain the Features line 1300 // in all cases. 1301 char buffer[1024]; 1302 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer)); 1303 if (CPUInfoSize == -1) 1304 return false; 1305 1306 StringRef Str(buffer, CPUInfoSize); 1307 1308 SmallVector<StringRef, 32> Lines; 1309 Str.split(Lines, "\n"); 1310 1311 SmallVector<StringRef, 32> CPUFeatures; 1312 1313 // Look for the CPU features. 1314 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1315 if (Lines[I].startswith("Features")) { 1316 Lines[I].split(CPUFeatures, ' '); 1317 break; 1318 } 1319 1320 #if defined(__aarch64__) 1321 // Keep track of which crypto features we have seen 1322 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1323 uint32_t crypto = 0; 1324 #endif 1325 1326 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1327 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1328 #if defined(__aarch64__) 1329 .Case("asimd", "neon") 1330 .Case("fp", "fp-armv8") 1331 .Case("crc32", "crc") 1332 #else 1333 .Case("half", "fp16") 1334 .Case("neon", "neon") 1335 .Case("vfpv3", "vfp3") 1336 .Case("vfpv3d16", "d16") 1337 .Case("vfpv4", "vfp4") 1338 .Case("idiva", "hwdiv-arm") 1339 .Case("idivt", "hwdiv") 1340 #endif 1341 .Default(""); 1342 1343 #if defined(__aarch64__) 1344 // We need to check crypto separately since we need all of the crypto 1345 // extensions to enable the subtarget feature 1346 if (CPUFeatures[I] == "aes") 1347 crypto |= CAP_AES; 1348 else if (CPUFeatures[I] == "pmull") 1349 crypto |= CAP_PMULL; 1350 else if (CPUFeatures[I] == "sha1") 1351 crypto |= CAP_SHA1; 1352 else if (CPUFeatures[I] == "sha2") 1353 crypto |= CAP_SHA2; 1354 #endif 1355 1356 if (LLVMFeatureStr != "") 1357 Features[LLVMFeatureStr] = true; 1358 } 1359 1360 #if defined(__aarch64__) 1361 // If we have all crypto bits we can add the feature 1362 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1363 Features["crypto"] = true; 1364 #endif 1365 1366 return true; 1367 } 1368 #else 1369 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1370 #endif 1371 1372 std::string sys::getProcessTriple() { 1373 Triple PT(Triple::normalize(LLVM_HOST_TRIPLE)); 1374 1375 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1376 PT = PT.get64BitArchVariant(); 1377 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1378 PT = PT.get32BitArchVariant(); 1379 1380 return PT.str(); 1381 } 1382