1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the operating system Host concept. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Support/Host.h" 15 #include "llvm/Support/TargetParser.h" 16 #include "llvm/ADT/SmallSet.h" 17 #include "llvm/ADT/SmallVector.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/ADT/Triple.h" 21 #include "llvm/Config/llvm-config.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/FileSystem.h" 24 #include "llvm/Support/MemoryBuffer.h" 25 #include "llvm/Support/raw_ostream.h" 26 #include <assert.h> 27 #include <string.h> 28 29 // Include the platform-specific parts of this class. 30 #ifdef LLVM_ON_UNIX 31 #include "Unix/Host.inc" 32 #endif 33 #ifdef _WIN32 34 #include "Windows/Host.inc" 35 #endif 36 #ifdef _MSC_VER 37 #include <intrin.h> 38 #endif 39 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 40 #include <mach/host_info.h> 41 #include <mach/mach.h> 42 #include <mach/mach_host.h> 43 #include <mach/machine.h> 44 #endif 45 46 #define DEBUG_TYPE "host-detection" 47 48 //===----------------------------------------------------------------------===// 49 // 50 // Implementations of the CPU detection routines 51 // 52 //===----------------------------------------------------------------------===// 53 54 using namespace llvm; 55 56 static std::unique_ptr<llvm::MemoryBuffer> 57 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 58 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 59 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 60 if (std::error_code EC = Text.getError()) { 61 llvm::errs() << "Can't read " 62 << "/proc/cpuinfo: " << EC.message() << "\n"; 63 return nullptr; 64 } 65 return std::move(*Text); 66 } 67 68 StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) { 69 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 70 // and so we must use an operating-system interface to determine the current 71 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 72 const char *generic = "generic"; 73 74 // The cpu line is second (after the 'processor: 0' line), so if this 75 // buffer is too small then something has changed (or is wrong). 76 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 77 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 78 79 StringRef::const_iterator CIP = CPUInfoStart; 80 81 StringRef::const_iterator CPUStart = 0; 82 size_t CPULen = 0; 83 84 // We need to find the first line which starts with cpu, spaces, and a colon. 85 // After the colon, there may be some additional spaces and then the cpu type. 86 while (CIP < CPUInfoEnd && CPUStart == 0) { 87 if (CIP < CPUInfoEnd && *CIP == '\n') 88 ++CIP; 89 90 if (CIP < CPUInfoEnd && *CIP == 'c') { 91 ++CIP; 92 if (CIP < CPUInfoEnd && *CIP == 'p') { 93 ++CIP; 94 if (CIP < CPUInfoEnd && *CIP == 'u') { 95 ++CIP; 96 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 97 ++CIP; 98 99 if (CIP < CPUInfoEnd && *CIP == ':') { 100 ++CIP; 101 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 102 ++CIP; 103 104 if (CIP < CPUInfoEnd) { 105 CPUStart = CIP; 106 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 107 *CIP != ',' && *CIP != '\n')) 108 ++CIP; 109 CPULen = CIP - CPUStart; 110 } 111 } 112 } 113 } 114 } 115 116 if (CPUStart == 0) 117 while (CIP < CPUInfoEnd && *CIP != '\n') 118 ++CIP; 119 } 120 121 if (CPUStart == 0) 122 return generic; 123 124 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 125 .Case("604e", "604e") 126 .Case("604", "604") 127 .Case("7400", "7400") 128 .Case("7410", "7400") 129 .Case("7447", "7400") 130 .Case("7455", "7450") 131 .Case("G4", "g4") 132 .Case("POWER4", "970") 133 .Case("PPC970FX", "970") 134 .Case("PPC970MP", "970") 135 .Case("G5", "g5") 136 .Case("POWER5", "g5") 137 .Case("A2", "a2") 138 .Case("POWER6", "pwr6") 139 .Case("POWER7", "pwr7") 140 .Case("POWER8", "pwr8") 141 .Case("POWER8E", "pwr8") 142 .Case("POWER8NVL", "pwr8") 143 .Case("POWER9", "pwr9") 144 .Default(generic); 145 } 146 147 StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { 148 // The cpuid register on arm is not accessible from user space. On Linux, 149 // it is exposed through the /proc/cpuinfo file. 150 151 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 152 // in all cases. 153 SmallVector<StringRef, 32> Lines; 154 ProcCpuinfoContent.split(Lines, "\n"); 155 156 // Look for the CPU implementer line. 157 StringRef Implementer; 158 StringRef Hardware; 159 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 160 if (Lines[I].startswith("CPU implementer")) 161 Implementer = Lines[I].substr(15).ltrim("\t :"); 162 if (Lines[I].startswith("Hardware")) 163 Hardware = Lines[I].substr(8).ltrim("\t :"); 164 } 165 166 if (Implementer == "0x41") { // ARM Ltd. 167 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 168 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 169 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 170 return "cortex-a53"; 171 172 173 // Look for the CPU part line. 174 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 175 if (Lines[I].startswith("CPU part")) 176 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 177 // values correspond to the "Part number" in the CP15/c0 register. The 178 // contents are specified in the various processor manuals. 179 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 180 .Case("0x926", "arm926ej-s") 181 .Case("0xb02", "mpcore") 182 .Case("0xb36", "arm1136j-s") 183 .Case("0xb56", "arm1156t2-s") 184 .Case("0xb76", "arm1176jz-s") 185 .Case("0xc08", "cortex-a8") 186 .Case("0xc09", "cortex-a9") 187 .Case("0xc0f", "cortex-a15") 188 .Case("0xc20", "cortex-m0") 189 .Case("0xc23", "cortex-m3") 190 .Case("0xc24", "cortex-m4") 191 .Case("0xd04", "cortex-a35") 192 .Case("0xd03", "cortex-a53") 193 .Case("0xd07", "cortex-a57") 194 .Case("0xd08", "cortex-a72") 195 .Case("0xd09", "cortex-a73") 196 .Default("generic"); 197 } 198 199 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium. 200 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 201 if (Lines[I].startswith("CPU part")) { 202 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 203 .Case("0x516", "thunderx2t99") 204 .Case("0x0516", "thunderx2t99") 205 .Case("0xaf", "thunderx2t99") 206 .Case("0x0af", "thunderx2t99") 207 .Case("0xa1", "thunderxt88") 208 .Case("0x0a1", "thunderxt88") 209 .Default("generic"); 210 } 211 } 212 } 213 214 if (Implementer == "0x48") // HiSilicon Technologies, Inc. 215 // Look for the CPU part line. 216 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 217 if (Lines[I].startswith("CPU part")) 218 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 219 // values correspond to the "Part number" in the CP15/c0 register. The 220 // contents are specified in the various processor manuals. 221 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 222 .Case("0xd01", "tsv110") 223 .Default("generic"); 224 225 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 226 // Look for the CPU part line. 227 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 228 if (Lines[I].startswith("CPU part")) 229 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 230 // values correspond to the "Part number" in the CP15/c0 register. The 231 // contents are specified in the various processor manuals. 232 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 233 .Case("0x06f", "krait") // APQ8064 234 .Case("0x201", "kryo") 235 .Case("0x205", "kryo") 236 .Case("0x211", "kryo") 237 .Case("0x800", "cortex-a73") 238 .Case("0x801", "cortex-a73") 239 .Case("0xc00", "falkor") 240 .Case("0xc01", "saphira") 241 .Default("generic"); 242 243 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. 244 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow 245 // any predictive pattern across variants and parts. 246 unsigned Variant = 0, Part = 0; 247 248 // Look for the CPU variant line, whose value is a 1 digit hexadecimal 249 // number, corresponding to the Variant bits in the CP15/C0 register. 250 for (auto I : Lines) 251 if (I.consume_front("CPU variant")) 252 I.ltrim("\t :").getAsInteger(0, Variant); 253 254 // Look for the CPU part line, whose value is a 3 digit hexadecimal 255 // number, corresponding to the PartNum bits in the CP15/C0 register. 256 for (auto I : Lines) 257 if (I.consume_front("CPU part")) 258 I.ltrim("\t :").getAsInteger(0, Part); 259 260 unsigned Exynos = (Variant << 12) | Part; 261 switch (Exynos) { 262 default: 263 // Default by falling through to Exynos M1. 264 LLVM_FALLTHROUGH; 265 266 case 0x1001: 267 return "exynos-m1"; 268 269 case 0x4001: 270 return "exynos-m2"; 271 } 272 } 273 274 return "generic"; 275 } 276 277 StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { 278 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 279 280 // The "processor 0:" line comes after a fair amount of other information, 281 // including a cache breakdown, but this should be plenty. 282 SmallVector<StringRef, 32> Lines; 283 ProcCpuinfoContent.split(Lines, "\n"); 284 285 // Look for the CPU features. 286 SmallVector<StringRef, 32> CPUFeatures; 287 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 288 if (Lines[I].startswith("features")) { 289 size_t Pos = Lines[I].find(":"); 290 if (Pos != StringRef::npos) { 291 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 292 break; 293 } 294 } 295 296 // We need to check for the presence of vector support independently of 297 // the machine type, since we may only use the vector register set when 298 // supported by the kernel (and hypervisor). 299 bool HaveVectorSupport = false; 300 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 301 if (CPUFeatures[I] == "vx") 302 HaveVectorSupport = true; 303 } 304 305 // Now check the processor machine type. 306 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 307 if (Lines[I].startswith("processor ")) { 308 size_t Pos = Lines[I].find("machine = "); 309 if (Pos != StringRef::npos) { 310 Pos += sizeof("machine = ") - 1; 311 unsigned int Id; 312 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 313 if (Id >= 3906 && HaveVectorSupport) 314 return "z14"; 315 if (Id >= 2964 && HaveVectorSupport) 316 return "z13"; 317 if (Id >= 2827) 318 return "zEC12"; 319 if (Id >= 2817) 320 return "z196"; 321 } 322 } 323 break; 324 } 325 } 326 327 return "generic"; 328 } 329 330 StringRef sys::detail::getHostCPUNameForBPF() { 331 #if !defined(__linux__) || !defined(__x86_64__) 332 return "generic"; 333 #else 334 uint8_t insns[40] __attribute__ ((aligned (8))) = 335 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 336 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 337 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 338 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 339 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 340 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 341 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 342 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 343 /* BPF_EXIT_INSN() */ 344 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 345 346 struct bpf_prog_load_attr { 347 uint32_t prog_type; 348 uint32_t insn_cnt; 349 uint64_t insns; 350 uint64_t license; 351 uint32_t log_level; 352 uint32_t log_size; 353 uint64_t log_buf; 354 uint32_t kern_version; 355 uint32_t prog_flags; 356 } attr = {}; 357 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 358 attr.insn_cnt = 5; 359 attr.insns = (uint64_t)insns; 360 attr.license = (uint64_t)"DUMMY"; 361 362 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 363 if (fd >= 0) { 364 close(fd); 365 return "v2"; 366 } 367 return "v1"; 368 #endif 369 } 370 371 #if defined(__i386__) || defined(_M_IX86) || \ 372 defined(__x86_64__) || defined(_M_X64) 373 374 enum VendorSignatures { 375 SIG_INTEL = 0x756e6547 /* Genu */, 376 SIG_AMD = 0x68747541 /* Auth */ 377 }; 378 379 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 380 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 381 // support. Consequently, for i386, the presence of CPUID is checked first 382 // via the corresponding eflags bit. 383 // Removal of cpuid.h header motivated by PR30384 384 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 385 // or test-suite, but are used in external projects e.g. libstdcxx 386 static bool isCpuIdSupported() { 387 #if defined(__GNUC__) || defined(__clang__) 388 #if defined(__i386__) 389 int __cpuid_supported; 390 __asm__(" pushfl\n" 391 " popl %%eax\n" 392 " movl %%eax,%%ecx\n" 393 " xorl $0x00200000,%%eax\n" 394 " pushl %%eax\n" 395 " popfl\n" 396 " pushfl\n" 397 " popl %%eax\n" 398 " movl $0,%0\n" 399 " cmpl %%eax,%%ecx\n" 400 " je 1f\n" 401 " movl $1,%0\n" 402 "1:" 403 : "=r"(__cpuid_supported) 404 : 405 : "eax", "ecx"); 406 if (!__cpuid_supported) 407 return false; 408 #endif 409 return true; 410 #endif 411 return true; 412 } 413 414 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 415 /// the specified arguments. If we can't run cpuid on the host, return true. 416 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 417 unsigned *rECX, unsigned *rEDX) { 418 #if defined(__GNUC__) || defined(__clang__) 419 #if defined(__x86_64__) 420 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 421 // FIXME: should we save this for Clang? 422 __asm__("movq\t%%rbx, %%rsi\n\t" 423 "cpuid\n\t" 424 "xchgq\t%%rbx, %%rsi\n\t" 425 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 426 : "a"(value)); 427 return false; 428 #elif defined(__i386__) 429 __asm__("movl\t%%ebx, %%esi\n\t" 430 "cpuid\n\t" 431 "xchgl\t%%ebx, %%esi\n\t" 432 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 433 : "a"(value)); 434 return false; 435 #else 436 return true; 437 #endif 438 #elif defined(_MSC_VER) 439 // The MSVC intrinsic is portable across x86 and x64. 440 int registers[4]; 441 __cpuid(registers, value); 442 *rEAX = registers[0]; 443 *rEBX = registers[1]; 444 *rECX = registers[2]; 445 *rEDX = registers[3]; 446 return false; 447 #else 448 return true; 449 #endif 450 } 451 452 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 453 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 454 /// return true. 455 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 456 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 457 unsigned *rEDX) { 458 #if defined(__GNUC__) || defined(__clang__) 459 #if defined(__x86_64__) 460 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 461 // FIXME: should we save this for Clang? 462 __asm__("movq\t%%rbx, %%rsi\n\t" 463 "cpuid\n\t" 464 "xchgq\t%%rbx, %%rsi\n\t" 465 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 466 : "a"(value), "c"(subleaf)); 467 return false; 468 #elif defined(__i386__) 469 __asm__("movl\t%%ebx, %%esi\n\t" 470 "cpuid\n\t" 471 "xchgl\t%%ebx, %%esi\n\t" 472 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 473 : "a"(value), "c"(subleaf)); 474 return false; 475 #else 476 return true; 477 #endif 478 #elif defined(_MSC_VER) 479 int registers[4]; 480 __cpuidex(registers, value, subleaf); 481 *rEAX = registers[0]; 482 *rEBX = registers[1]; 483 *rECX = registers[2]; 484 *rEDX = registers[3]; 485 return false; 486 #else 487 return true; 488 #endif 489 } 490 491 // Read control register 0 (XCR0). Used to detect features such as AVX. 492 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 493 #if defined(__GNUC__) || defined(__clang__) 494 // Check xgetbv; this uses a .byte sequence instead of the instruction 495 // directly because older assemblers do not include support for xgetbv and 496 // there is no easy way to conditionally compile based on the assembler used. 497 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 498 return false; 499 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 500 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 501 *rEAX = Result; 502 *rEDX = Result >> 32; 503 return false; 504 #else 505 return true; 506 #endif 507 } 508 509 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 510 unsigned *Model) { 511 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 512 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 513 if (*Family == 6 || *Family == 0xf) { 514 if (*Family == 0xf) 515 // Examine extended family ID if family ID is F. 516 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 517 // Examine extended model ID if family ID is 6 or F. 518 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 519 } 520 } 521 522 static void 523 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 524 unsigned Brand_id, unsigned Features, 525 unsigned Features2, unsigned Features3, 526 unsigned *Type, unsigned *Subtype) { 527 if (Brand_id != 0) 528 return; 529 switch (Family) { 530 case 3: 531 *Type = X86::INTEL_i386; 532 break; 533 case 4: 534 *Type = X86::INTEL_i486; 535 break; 536 case 5: 537 if (Features & (1 << X86::FEATURE_MMX)) { 538 *Type = X86::INTEL_PENTIUM_MMX; 539 break; 540 } 541 *Type = X86::INTEL_PENTIUM; 542 break; 543 case 6: 544 switch (Model) { 545 case 0x01: // Pentium Pro processor 546 *Type = X86::INTEL_PENTIUM_PRO; 547 break; 548 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 549 // model 03 550 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 551 // model 05, and Intel Celeron processor, model 05 552 case 0x06: // Celeron processor, model 06 553 *Type = X86::INTEL_PENTIUM_II; 554 break; 555 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 556 // processor, model 07 557 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 558 // model 08, and Celeron processor, model 08 559 case 0x0a: // Pentium III Xeon processor, model 0Ah 560 case 0x0b: // Pentium III processor, model 0Bh 561 *Type = X86::INTEL_PENTIUM_III; 562 break; 563 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 564 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 565 // 0Dh. All processors are manufactured using the 90 nm process. 566 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 567 // Integrated Processor with Intel QuickAssist Technology 568 *Type = X86::INTEL_PENTIUM_M; 569 break; 570 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 571 // 0Eh. All processors are manufactured using the 65 nm process. 572 *Type = X86::INTEL_CORE_DUO; 573 break; // yonah 574 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 575 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 576 // mobile processor, Intel Core 2 Extreme processor, Intel 577 // Pentium Dual-Core processor, Intel Xeon processor, model 578 // 0Fh. All processors are manufactured using the 65 nm process. 579 case 0x16: // Intel Celeron processor model 16h. All processors are 580 // manufactured using the 65 nm process 581 *Type = X86::INTEL_CORE2; // "core2" 582 *Subtype = X86::INTEL_CORE2_65; 583 break; 584 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 585 // 17h. All processors are manufactured using the 45 nm process. 586 // 587 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 588 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 589 // the 45 nm process. 590 *Type = X86::INTEL_CORE2; // "penryn" 591 *Subtype = X86::INTEL_CORE2_45; 592 break; 593 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 594 // processors are manufactured using the 45 nm process. 595 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 596 // As found in a Summer 2010 model iMac. 597 case 0x1f: 598 case 0x2e: // Nehalem EX 599 *Type = X86::INTEL_COREI7; // "nehalem" 600 *Subtype = X86::INTEL_COREI7_NEHALEM; 601 break; 602 case 0x25: // Intel Core i7, laptop version. 603 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 604 // processors are manufactured using the 32 nm process. 605 case 0x2f: // Westmere EX 606 *Type = X86::INTEL_COREI7; // "westmere" 607 *Subtype = X86::INTEL_COREI7_WESTMERE; 608 break; 609 case 0x2a: // Intel Core i7 processor. All processors are manufactured 610 // using the 32 nm process. 611 case 0x2d: 612 *Type = X86::INTEL_COREI7; //"sandybridge" 613 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 614 break; 615 case 0x3a: 616 case 0x3e: // Ivy Bridge EP 617 *Type = X86::INTEL_COREI7; // "ivybridge" 618 *Subtype = X86::INTEL_COREI7_IVYBRIDGE; 619 break; 620 621 // Haswell: 622 case 0x3c: 623 case 0x3f: 624 case 0x45: 625 case 0x46: 626 *Type = X86::INTEL_COREI7; // "haswell" 627 *Subtype = X86::INTEL_COREI7_HASWELL; 628 break; 629 630 // Broadwell: 631 case 0x3d: 632 case 0x47: 633 case 0x4f: 634 case 0x56: 635 *Type = X86::INTEL_COREI7; // "broadwell" 636 *Subtype = X86::INTEL_COREI7_BROADWELL; 637 break; 638 639 // Skylake: 640 case 0x4e: // Skylake mobile 641 case 0x5e: // Skylake desktop 642 case 0x8e: // Kaby Lake mobile 643 case 0x9e: // Kaby Lake desktop 644 *Type = X86::INTEL_COREI7; // "skylake" 645 *Subtype = X86::INTEL_COREI7_SKYLAKE; 646 break; 647 648 // Skylake Xeon: 649 case 0x55: 650 *Type = X86::INTEL_COREI7; 651 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 652 break; 653 654 // Cannonlake: 655 case 0x66: 656 *Type = X86::INTEL_COREI7; 657 *Subtype = X86::INTEL_COREI7_CANNONLAKE; // "cannonlake" 658 break; 659 660 case 0x1c: // Most 45 nm Intel Atom processors 661 case 0x26: // 45 nm Atom Lincroft 662 case 0x27: // 32 nm Atom Medfield 663 case 0x35: // 32 nm Atom Midview 664 case 0x36: // 32 nm Atom Midview 665 *Type = X86::INTEL_BONNELL; 666 break; // "bonnell" 667 668 // Atom Silvermont codes from the Intel software optimization guide. 669 case 0x37: 670 case 0x4a: 671 case 0x4d: 672 case 0x5a: 673 case 0x5d: 674 case 0x4c: // really airmont 675 *Type = X86::INTEL_SILVERMONT; 676 break; // "silvermont" 677 // Goldmont: 678 case 0x5c: // Apollo Lake 679 case 0x5f: // Denverton 680 *Type = X86::INTEL_GOLDMONT; 681 break; // "goldmont" 682 case 0x7a: 683 *Type = X86::INTEL_GOLDMONT_PLUS; 684 break; 685 case 0x57: 686 *Type = X86::INTEL_KNL; // knl 687 break; 688 case 0x85: 689 *Type = X86::INTEL_KNM; // knm 690 break; 691 692 default: // Unknown family 6 CPU, try to guess. 693 if (Features & (1 << X86::FEATURE_AVX512VBMI)) { 694 *Type = X86::INTEL_COREI7; 695 *Subtype = X86::INTEL_COREI7_CANNONLAKE; 696 break; 697 } 698 699 if (Features & (1 << X86::FEATURE_AVX512VL)) { 700 *Type = X86::INTEL_COREI7; 701 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; 702 break; 703 } 704 705 if (Features & (1 << X86::FEATURE_AVX512ER)) { 706 *Type = X86::INTEL_KNL; // knl 707 break; 708 } 709 710 if (Features3 & (1 << (X86::FEATURE_CLFLUSHOPT - 64))) { 711 if (Features3 & (1 << (X86::FEATURE_SHA - 64))) { 712 *Type = X86::INTEL_GOLDMONT; 713 } else { 714 *Type = X86::INTEL_COREI7; 715 *Subtype = X86::INTEL_COREI7_SKYLAKE; 716 } 717 break; 718 } 719 if (Features3 & (1 << (X86::FEATURE_ADX - 64))) { 720 *Type = X86::INTEL_COREI7; 721 *Subtype = X86::INTEL_COREI7_BROADWELL; 722 break; 723 } 724 if (Features & (1 << X86::FEATURE_AVX2)) { 725 *Type = X86::INTEL_COREI7; 726 *Subtype = X86::INTEL_COREI7_HASWELL; 727 break; 728 } 729 if (Features & (1 << X86::FEATURE_AVX)) { 730 *Type = X86::INTEL_COREI7; 731 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 732 break; 733 } 734 if (Features & (1 << X86::FEATURE_SSE4_2)) { 735 if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { 736 *Type = X86::INTEL_SILVERMONT; 737 } else { 738 *Type = X86::INTEL_COREI7; 739 *Subtype = X86::INTEL_COREI7_NEHALEM; 740 } 741 break; 742 } 743 if (Features & (1 << X86::FEATURE_SSE4_1)) { 744 *Type = X86::INTEL_CORE2; // "penryn" 745 *Subtype = X86::INTEL_CORE2_45; 746 break; 747 } 748 if (Features & (1 << X86::FEATURE_SSSE3)) { 749 if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { 750 *Type = X86::INTEL_BONNELL; // "bonnell" 751 } else { 752 *Type = X86::INTEL_CORE2; // "core2" 753 *Subtype = X86::INTEL_CORE2_65; 754 } 755 break; 756 } 757 if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { 758 *Type = X86::INTEL_CORE2; // "core2" 759 *Subtype = X86::INTEL_CORE2_65; 760 break; 761 } 762 if (Features & (1 << X86::FEATURE_SSE3)) { 763 *Type = X86::INTEL_CORE_DUO; 764 break; 765 } 766 if (Features & (1 << X86::FEATURE_SSE2)) { 767 *Type = X86::INTEL_PENTIUM_M; 768 break; 769 } 770 if (Features & (1 << X86::FEATURE_SSE)) { 771 *Type = X86::INTEL_PENTIUM_III; 772 break; 773 } 774 if (Features & (1 << X86::FEATURE_MMX)) { 775 *Type = X86::INTEL_PENTIUM_II; 776 break; 777 } 778 *Type = X86::INTEL_PENTIUM_PRO; 779 break; 780 } 781 break; 782 case 15: { 783 if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { 784 *Type = X86::INTEL_NOCONA; 785 break; 786 } 787 if (Features & (1 << X86::FEATURE_SSE3)) { 788 *Type = X86::INTEL_PRESCOTT; 789 break; 790 } 791 *Type = X86::INTEL_PENTIUM_IV; 792 break; 793 } 794 default: 795 break; /*"generic"*/ 796 } 797 } 798 799 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 800 unsigned Features, unsigned *Type, 801 unsigned *Subtype) { 802 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 803 // appears to be no way to generate the wide variety of AMD-specific targets 804 // from the information returned from CPUID. 805 switch (Family) { 806 case 4: 807 *Type = X86::AMD_i486; 808 break; 809 case 5: 810 *Type = X86::AMDPENTIUM; 811 switch (Model) { 812 case 6: 813 case 7: 814 *Subtype = X86::AMDPENTIUM_K6; 815 break; // "k6" 816 case 8: 817 *Subtype = X86::AMDPENTIUM_K62; 818 break; // "k6-2" 819 case 9: 820 case 13: 821 *Subtype = X86::AMDPENTIUM_K63; 822 break; // "k6-3" 823 case 10: 824 *Subtype = X86::AMDPENTIUM_GEODE; 825 break; // "geode" 826 } 827 break; 828 case 6: 829 if (Features & (1 << X86::FEATURE_SSE)) { 830 *Type = X86::AMD_ATHLON_XP; 831 break; // "athlon-xp" 832 } 833 *Type = X86::AMD_ATHLON; 834 break; // "athlon" 835 case 15: 836 if (Features & (1 << X86::FEATURE_SSE3)) { 837 *Type = X86::AMD_K8SSE3; 838 break; // "k8-sse3" 839 } 840 *Type = X86::AMD_K8; 841 break; // "k8" 842 case 16: 843 *Type = X86::AMDFAM10H; // "amdfam10" 844 switch (Model) { 845 case 2: 846 *Subtype = X86::AMDFAM10H_BARCELONA; 847 break; 848 case 4: 849 *Subtype = X86::AMDFAM10H_SHANGHAI; 850 break; 851 case 8: 852 *Subtype = X86::AMDFAM10H_ISTANBUL; 853 break; 854 } 855 break; 856 case 20: 857 *Type = X86::AMD_BTVER1; 858 break; // "btver1"; 859 case 21: 860 *Type = X86::AMDFAM15H; 861 if (Model >= 0x60 && Model <= 0x7f) { 862 *Subtype = X86::AMDFAM15H_BDVER4; 863 break; // "bdver4"; 60h-7Fh: Excavator 864 } 865 if (Model >= 0x30 && Model <= 0x3f) { 866 *Subtype = X86::AMDFAM15H_BDVER3; 867 break; // "bdver3"; 30h-3Fh: Steamroller 868 } 869 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) { 870 *Subtype = X86::AMDFAM15H_BDVER2; 871 break; // "bdver2"; 02h, 10h-1Fh: Piledriver 872 } 873 if (Model <= 0x0f) { 874 *Subtype = X86::AMDFAM15H_BDVER1; 875 break; // "bdver1"; 00h-0Fh: Bulldozer 876 } 877 break; 878 case 22: 879 *Type = X86::AMD_BTVER2; 880 break; // "btver2" 881 case 23: 882 *Type = X86::AMDFAM17H; 883 *Subtype = X86::AMDFAM17H_ZNVER1; 884 break; 885 default: 886 break; // "generic" 887 } 888 } 889 890 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 891 unsigned *FeaturesOut, unsigned *Features2Out, 892 unsigned *Features3Out) { 893 unsigned Features = 0; 894 unsigned Features2 = 0; 895 unsigned Features3 = 0; 896 unsigned EAX, EBX; 897 898 auto setFeature = [&](unsigned F) { 899 if (F < 32) 900 Features |= 1 << F; 901 else if (F < 64) 902 Features2 |= 1 << (F - 32); 903 else if (F < 96) 904 Features3 |= 1 << (F - 64); 905 else 906 llvm_unreachable("Unexpected FeatureBit"); 907 }; 908 909 if ((EDX >> 15) & 1) 910 setFeature(X86::FEATURE_CMOV); 911 if ((EDX >> 23) & 1) 912 setFeature(X86::FEATURE_MMX); 913 if ((EDX >> 25) & 1) 914 setFeature(X86::FEATURE_SSE); 915 if ((EDX >> 26) & 1) 916 setFeature(X86::FEATURE_SSE2); 917 918 if ((ECX >> 0) & 1) 919 setFeature(X86::FEATURE_SSE3); 920 if ((ECX >> 1) & 1) 921 setFeature(X86::FEATURE_PCLMUL); 922 if ((ECX >> 9) & 1) 923 setFeature(X86::FEATURE_SSSE3); 924 if ((ECX >> 12) & 1) 925 setFeature(X86::FEATURE_FMA); 926 if ((ECX >> 19) & 1) 927 setFeature(X86::FEATURE_SSE4_1); 928 if ((ECX >> 20) & 1) 929 setFeature(X86::FEATURE_SSE4_2); 930 if ((ECX >> 23) & 1) 931 setFeature(X86::FEATURE_POPCNT); 932 if ((ECX >> 25) & 1) 933 setFeature(X86::FEATURE_AES); 934 935 if ((ECX >> 22) & 1) 936 setFeature(X86::FEATURE_MOVBE); 937 938 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 939 // indicates that the AVX registers will be saved and restored on context 940 // switch, then we have full AVX support. 941 const unsigned AVXBits = (1 << 27) | (1 << 28); 942 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 943 ((EAX & 0x6) == 0x6); 944 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 945 946 if (HasAVX) 947 setFeature(X86::FEATURE_AVX); 948 949 bool HasLeaf7 = 950 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 951 952 if (HasLeaf7 && ((EBX >> 3) & 1)) 953 setFeature(X86::FEATURE_BMI); 954 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 955 setFeature(X86::FEATURE_AVX2); 956 if (HasLeaf7 && ((EBX >> 9) & 1)) 957 setFeature(X86::FEATURE_BMI2); 958 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 959 setFeature(X86::FEATURE_AVX512F); 960 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 961 setFeature(X86::FEATURE_AVX512DQ); 962 if (HasLeaf7 && ((EBX >> 19) & 1)) 963 setFeature(X86::FEATURE_ADX); 964 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 965 setFeature(X86::FEATURE_AVX512IFMA); 966 if (HasLeaf7 && ((EBX >> 23) & 1)) 967 setFeature(X86::FEATURE_CLFLUSHOPT); 968 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 969 setFeature(X86::FEATURE_AVX512PF); 970 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 971 setFeature(X86::FEATURE_AVX512ER); 972 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 973 setFeature(X86::FEATURE_AVX512CD); 974 if (HasLeaf7 && ((EBX >> 29) & 1)) 975 setFeature(X86::FEATURE_SHA); 976 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 977 setFeature(X86::FEATURE_AVX512BW); 978 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 979 setFeature(X86::FEATURE_AVX512VL); 980 981 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 982 setFeature(X86::FEATURE_AVX512VBMI); 983 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save) 984 setFeature(X86::FEATURE_AVX512VBMI2); 985 if (HasLeaf7 && ((ECX >> 8) & 1)) 986 setFeature(X86::FEATURE_GFNI); 987 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX) 988 setFeature(X86::FEATURE_VPCLMULQDQ); 989 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save) 990 setFeature(X86::FEATURE_AVX512VNNI); 991 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save) 992 setFeature(X86::FEATURE_AVX512BITALG); 993 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 994 setFeature(X86::FEATURE_AVX512VPOPCNTDQ); 995 996 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 997 setFeature(X86::FEATURE_AVX5124VNNIW); 998 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 999 setFeature(X86::FEATURE_AVX5124FMAPS); 1000 1001 unsigned MaxExtLevel; 1002 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1003 1004 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1005 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1006 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1007 setFeature(X86::FEATURE_SSE4_A); 1008 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1009 setFeature(X86::FEATURE_XOP); 1010 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1011 setFeature(X86::FEATURE_FMA4); 1012 1013 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1014 setFeature(X86::FEATURE_EM64T); 1015 1016 *FeaturesOut = Features; 1017 *Features2Out = Features2; 1018 *Features3Out = Features3; 1019 } 1020 1021 StringRef sys::getHostCPUName() { 1022 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1023 unsigned MaxLeaf, Vendor; 1024 1025 #if defined(__GNUC__) || defined(__clang__) 1026 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here 1027 // and simplify it to not invoke __cpuid (like cpu_model.c in 1028 // compiler-rt/lib/builtins/cpu_model.c? 1029 // Opting for the second option. 1030 if(!isCpuIdSupported()) 1031 return "generic"; 1032 #endif 1033 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) 1034 return "generic"; 1035 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1036 1037 unsigned Brand_id = EBX & 0xff; 1038 unsigned Family = 0, Model = 0; 1039 unsigned Features = 0, Features2 = 0, Features3 = 0; 1040 detectX86FamilyModel(EAX, &Family, &Model); 1041 getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2, &Features3); 1042 1043 unsigned Type = 0; 1044 unsigned Subtype = 0; 1045 1046 if (Vendor == SIG_INTEL) { 1047 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, 1048 Features2, Features3, &Type, &Subtype); 1049 } else if (Vendor == SIG_AMD) { 1050 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1051 } 1052 1053 // Check subtypes first since those are more specific. 1054 #define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \ 1055 if (Subtype == X86::ENUM) \ 1056 return ARCHNAME; 1057 #include "llvm/Support/X86TargetParser.def" 1058 1059 // Now check types. 1060 #define X86_CPU_TYPE(ARCHNAME, ENUM) \ 1061 if (Type == X86::ENUM) \ 1062 return ARCHNAME; 1063 #include "llvm/Support/X86TargetParser.def" 1064 1065 return "generic"; 1066 } 1067 1068 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1069 StringRef sys::getHostCPUName() { 1070 host_basic_info_data_t hostInfo; 1071 mach_msg_type_number_t infoCount; 1072 1073 infoCount = HOST_BASIC_INFO_COUNT; 1074 mach_port_t hostPort = mach_host_self(); 1075 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1076 &infoCount); 1077 mach_port_deallocate(mach_task_self(), hostPort); 1078 1079 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1080 return "generic"; 1081 1082 switch (hostInfo.cpu_subtype) { 1083 case CPU_SUBTYPE_POWERPC_601: 1084 return "601"; 1085 case CPU_SUBTYPE_POWERPC_602: 1086 return "602"; 1087 case CPU_SUBTYPE_POWERPC_603: 1088 return "603"; 1089 case CPU_SUBTYPE_POWERPC_603e: 1090 return "603e"; 1091 case CPU_SUBTYPE_POWERPC_603ev: 1092 return "603ev"; 1093 case CPU_SUBTYPE_POWERPC_604: 1094 return "604"; 1095 case CPU_SUBTYPE_POWERPC_604e: 1096 return "604e"; 1097 case CPU_SUBTYPE_POWERPC_620: 1098 return "620"; 1099 case CPU_SUBTYPE_POWERPC_750: 1100 return "750"; 1101 case CPU_SUBTYPE_POWERPC_7400: 1102 return "7400"; 1103 case CPU_SUBTYPE_POWERPC_7450: 1104 return "7450"; 1105 case CPU_SUBTYPE_POWERPC_970: 1106 return "970"; 1107 default:; 1108 } 1109 1110 return "generic"; 1111 } 1112 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1113 StringRef sys::getHostCPUName() { 1114 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1115 StringRef Content = P ? P->getBuffer() : ""; 1116 return detail::getHostCPUNameForPowerPC(Content); 1117 } 1118 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1119 StringRef sys::getHostCPUName() { 1120 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1121 StringRef Content = P ? P->getBuffer() : ""; 1122 return detail::getHostCPUNameForARM(Content); 1123 } 1124 #elif defined(__linux__) && defined(__s390x__) 1125 StringRef sys::getHostCPUName() { 1126 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1127 StringRef Content = P ? P->getBuffer() : ""; 1128 return detail::getHostCPUNameForS390x(Content); 1129 } 1130 #else 1131 StringRef sys::getHostCPUName() { return "generic"; } 1132 #endif 1133 1134 #if defined(__linux__) && defined(__x86_64__) 1135 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1136 // using the number of unique physical/core id pairs. The following 1137 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1138 static int computeHostNumPhysicalCores() { 1139 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1140 // mmapped because it appears to have 0 size. 1141 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1142 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1143 if (std::error_code EC = Text.getError()) { 1144 llvm::errs() << "Can't read " 1145 << "/proc/cpuinfo: " << EC.message() << "\n"; 1146 return -1; 1147 } 1148 SmallVector<StringRef, 8> strs; 1149 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1150 /*KeepEmpty=*/false); 1151 int CurPhysicalId = -1; 1152 int CurCoreId = -1; 1153 SmallSet<std::pair<int, int>, 32> UniqueItems; 1154 for (auto &Line : strs) { 1155 Line = Line.trim(); 1156 if (!Line.startswith("physical id") && !Line.startswith("core id")) 1157 continue; 1158 std::pair<StringRef, StringRef> Data = Line.split(':'); 1159 auto Name = Data.first.trim(); 1160 auto Val = Data.second.trim(); 1161 if (Name == "physical id") { 1162 assert(CurPhysicalId == -1 && 1163 "Expected a core id before seeing another physical id"); 1164 Val.getAsInteger(10, CurPhysicalId); 1165 } 1166 if (Name == "core id") { 1167 assert(CurCoreId == -1 && 1168 "Expected a physical id before seeing another core id"); 1169 Val.getAsInteger(10, CurCoreId); 1170 } 1171 if (CurPhysicalId != -1 && CurCoreId != -1) { 1172 UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId)); 1173 CurPhysicalId = -1; 1174 CurCoreId = -1; 1175 } 1176 } 1177 return UniqueItems.size(); 1178 } 1179 #elif defined(__APPLE__) && defined(__x86_64__) 1180 #include <sys/param.h> 1181 #include <sys/sysctl.h> 1182 1183 // Gets the number of *physical cores* on the machine. 1184 static int computeHostNumPhysicalCores() { 1185 uint32_t count; 1186 size_t len = sizeof(count); 1187 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1188 if (count < 1) { 1189 int nm[2]; 1190 nm[0] = CTL_HW; 1191 nm[1] = HW_AVAILCPU; 1192 sysctl(nm, 2, &count, &len, NULL, 0); 1193 if (count < 1) 1194 return -1; 1195 } 1196 return count; 1197 } 1198 #else 1199 // On other systems, return -1 to indicate unknown. 1200 static int computeHostNumPhysicalCores() { return -1; } 1201 #endif 1202 1203 int sys::getHostNumPhysicalCores() { 1204 static int NumCores = computeHostNumPhysicalCores(); 1205 return NumCores; 1206 } 1207 1208 #if defined(__i386__) || defined(_M_IX86) || \ 1209 defined(__x86_64__) || defined(_M_X64) 1210 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1211 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1212 unsigned MaxLevel; 1213 union { 1214 unsigned u[3]; 1215 char c[12]; 1216 } text; 1217 1218 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1219 MaxLevel < 1) 1220 return false; 1221 1222 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1223 1224 Features["cmov"] = (EDX >> 15) & 1; 1225 Features["mmx"] = (EDX >> 23) & 1; 1226 Features["sse"] = (EDX >> 25) & 1; 1227 Features["sse2"] = (EDX >> 26) & 1; 1228 1229 Features["sse3"] = (ECX >> 0) & 1; 1230 Features["pclmul"] = (ECX >> 1) & 1; 1231 Features["ssse3"] = (ECX >> 9) & 1; 1232 Features["cx16"] = (ECX >> 13) & 1; 1233 Features["sse4.1"] = (ECX >> 19) & 1; 1234 Features["sse4.2"] = (ECX >> 20) & 1; 1235 Features["movbe"] = (ECX >> 22) & 1; 1236 Features["popcnt"] = (ECX >> 23) & 1; 1237 Features["aes"] = (ECX >> 25) & 1; 1238 Features["rdrnd"] = (ECX >> 30) & 1; 1239 1240 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1241 // indicates that the AVX registers will be saved and restored on context 1242 // switch, then we have full AVX support. 1243 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1244 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1245 // AVX512 requires additional context to be saved by the OS. 1246 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1247 1248 Features["avx"] = HasAVXSave; 1249 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave; 1250 // Only enable XSAVE if OS has enabled support for saving YMM state. 1251 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave; 1252 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave; 1253 1254 unsigned MaxExtLevel; 1255 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1256 1257 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1258 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1259 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1); 1260 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1261 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1262 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1263 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1264 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1265 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1266 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1267 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1268 1269 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1); 1270 1271 // Miscellaneous memory related features, detected by 1272 // using the 0x80000008 leaf of the CPUID instruction 1273 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1274 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX); 1275 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1276 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1); 1277 1278 bool HasLeaf7 = 1279 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1280 1281 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1282 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1283 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1284 // AVX2 is only supported if we have the OS save support from AVX. 1285 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave; 1286 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1287 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1288 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1289 // AVX512 is only supported if the OS supports the context save for it. 1290 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1291 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1292 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1293 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1294 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1295 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1296 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1297 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1298 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1299 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1300 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1301 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1302 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1303 1304 Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1); 1305 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1306 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1307 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1); 1308 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save; 1309 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1); 1310 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1); 1311 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave; 1312 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave; 1313 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save; 1314 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save; 1315 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1316 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1); 1317 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1); 1318 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1); 1319 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1); 1320 1321 // There are two CPUID leafs which information associated with the pconfig 1322 // instruction: 1323 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th 1324 // bit of EDX), while the EAX=0x1b leaf returns information on the 1325 // availability of specific pconfig leafs. 1326 // The target feature here only refers to the the first of these two. 1327 // Users might need to check for the availability of specific pconfig 1328 // leaves using cpuid, since that information is ignored while 1329 // detecting features using the "-march=native" flag. 1330 // For more info, see X86 ISA docs. 1331 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1); 1332 1333 bool HasLeafD = MaxLevel >= 0xd && 1334 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1335 1336 // Only enable XSAVE if OS has enabled support for saving YMM state. 1337 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave; 1338 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave; 1339 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave; 1340 1341 bool HasLeaf14 = MaxLevel >= 0x14 && 1342 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX); 1343 1344 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1); 1345 1346 return true; 1347 } 1348 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1349 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1350 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1351 if (!P) 1352 return false; 1353 1354 SmallVector<StringRef, 32> Lines; 1355 P->getBuffer().split(Lines, "\n"); 1356 1357 SmallVector<StringRef, 32> CPUFeatures; 1358 1359 // Look for the CPU features. 1360 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1361 if (Lines[I].startswith("Features")) { 1362 Lines[I].split(CPUFeatures, ' '); 1363 break; 1364 } 1365 1366 #if defined(__aarch64__) 1367 // Keep track of which crypto features we have seen 1368 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1369 uint32_t crypto = 0; 1370 #endif 1371 1372 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1373 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1374 #if defined(__aarch64__) 1375 .Case("asimd", "neon") 1376 .Case("fp", "fp-armv8") 1377 .Case("crc32", "crc") 1378 #else 1379 .Case("half", "fp16") 1380 .Case("neon", "neon") 1381 .Case("vfpv3", "vfp3") 1382 .Case("vfpv3d16", "d16") 1383 .Case("vfpv4", "vfp4") 1384 .Case("idiva", "hwdiv-arm") 1385 .Case("idivt", "hwdiv") 1386 #endif 1387 .Default(""); 1388 1389 #if defined(__aarch64__) 1390 // We need to check crypto separately since we need all of the crypto 1391 // extensions to enable the subtarget feature 1392 if (CPUFeatures[I] == "aes") 1393 crypto |= CAP_AES; 1394 else if (CPUFeatures[I] == "pmull") 1395 crypto |= CAP_PMULL; 1396 else if (CPUFeatures[I] == "sha1") 1397 crypto |= CAP_SHA1; 1398 else if (CPUFeatures[I] == "sha2") 1399 crypto |= CAP_SHA2; 1400 #endif 1401 1402 if (LLVMFeatureStr != "") 1403 Features[LLVMFeatureStr] = true; 1404 } 1405 1406 #if defined(__aarch64__) 1407 // If we have all crypto bits we can add the feature 1408 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1409 Features["crypto"] = true; 1410 #endif 1411 1412 return true; 1413 } 1414 #else 1415 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1416 #endif 1417 1418 std::string sys::getProcessTriple() { 1419 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1420 Triple PT(Triple::normalize(TargetTripleString)); 1421 1422 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1423 PT = PT.get64BitArchVariant(); 1424 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1425 PT = PT.get32BitArchVariant(); 1426 1427 return PT.str(); 1428 } 1429