1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the operating system Host concept. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/Host.h" 14 #include "llvm/ADT/SmallSet.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringMap.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/llvm-config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/X86TargetParser.h" 25 #include "llvm/Support/raw_ostream.h" 26 #include <assert.h> 27 #include <string.h> 28 29 // Include the platform-specific parts of this class. 30 #ifdef LLVM_ON_UNIX 31 #include "Unix/Host.inc" 32 #include <sched.h> 33 #endif 34 #ifdef _WIN32 35 #include "Windows/Host.inc" 36 #endif 37 #ifdef _MSC_VER 38 #include <intrin.h> 39 #endif 40 #if defined(__APPLE__) && (!defined(__x86_64__)) 41 #include <mach/host_info.h> 42 #include <mach/mach.h> 43 #include <mach/mach_host.h> 44 #include <mach/machine.h> 45 #endif 46 47 #define DEBUG_TYPE "host-detection" 48 49 //===----------------------------------------------------------------------===// 50 // 51 // Implementations of the CPU detection routines 52 // 53 //===----------------------------------------------------------------------===// 54 55 using namespace llvm; 56 57 static std::unique_ptr<llvm::MemoryBuffer> 58 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 59 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 60 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 61 if (std::error_code EC = Text.getError()) { 62 llvm::errs() << "Can't read " 63 << "/proc/cpuinfo: " << EC.message() << "\n"; 64 return nullptr; 65 } 66 return std::move(*Text); 67 } 68 69 StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) { 70 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 71 // and so we must use an operating-system interface to determine the current 72 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 73 const char *generic = "generic"; 74 75 // The cpu line is second (after the 'processor: 0' line), so if this 76 // buffer is too small then something has changed (or is wrong). 77 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 78 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 79 80 StringRef::const_iterator CIP = CPUInfoStart; 81 82 StringRef::const_iterator CPUStart = 0; 83 size_t CPULen = 0; 84 85 // We need to find the first line which starts with cpu, spaces, and a colon. 86 // After the colon, there may be some additional spaces and then the cpu type. 87 while (CIP < CPUInfoEnd && CPUStart == 0) { 88 if (CIP < CPUInfoEnd && *CIP == '\n') 89 ++CIP; 90 91 if (CIP < CPUInfoEnd && *CIP == 'c') { 92 ++CIP; 93 if (CIP < CPUInfoEnd && *CIP == 'p') { 94 ++CIP; 95 if (CIP < CPUInfoEnd && *CIP == 'u') { 96 ++CIP; 97 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 98 ++CIP; 99 100 if (CIP < CPUInfoEnd && *CIP == ':') { 101 ++CIP; 102 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 103 ++CIP; 104 105 if (CIP < CPUInfoEnd) { 106 CPUStart = CIP; 107 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 108 *CIP != ',' && *CIP != '\n')) 109 ++CIP; 110 CPULen = CIP - CPUStart; 111 } 112 } 113 } 114 } 115 } 116 117 if (CPUStart == 0) 118 while (CIP < CPUInfoEnd && *CIP != '\n') 119 ++CIP; 120 } 121 122 if (CPUStart == 0) 123 return generic; 124 125 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 126 .Case("604e", "604e") 127 .Case("604", "604") 128 .Case("7400", "7400") 129 .Case("7410", "7400") 130 .Case("7447", "7400") 131 .Case("7455", "7450") 132 .Case("G4", "g4") 133 .Case("POWER4", "970") 134 .Case("PPC970FX", "970") 135 .Case("PPC970MP", "970") 136 .Case("G5", "g5") 137 .Case("POWER5", "g5") 138 .Case("A2", "a2") 139 .Case("POWER6", "pwr6") 140 .Case("POWER7", "pwr7") 141 .Case("POWER8", "pwr8") 142 .Case("POWER8E", "pwr8") 143 .Case("POWER8NVL", "pwr8") 144 .Case("POWER9", "pwr9") 145 .Case("POWER10", "pwr10") 146 // FIXME: If we get a simulator or machine with the capabilities of 147 // mcpu=future, we should revisit this and add the name reported by the 148 // simulator/machine. 149 .Default(generic); 150 } 151 152 StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { 153 // The cpuid register on arm is not accessible from user space. On Linux, 154 // it is exposed through the /proc/cpuinfo file. 155 156 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 157 // in all cases. 158 SmallVector<StringRef, 32> Lines; 159 ProcCpuinfoContent.split(Lines, "\n"); 160 161 // Look for the CPU implementer line. 162 StringRef Implementer; 163 StringRef Hardware; 164 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 165 if (Lines[I].startswith("CPU implementer")) 166 Implementer = Lines[I].substr(15).ltrim("\t :"); 167 if (Lines[I].startswith("Hardware")) 168 Hardware = Lines[I].substr(8).ltrim("\t :"); 169 } 170 171 if (Implementer == "0x41") { // ARM Ltd. 172 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 173 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 174 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 175 return "cortex-a53"; 176 177 178 // Look for the CPU part line. 179 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 180 if (Lines[I].startswith("CPU part")) 181 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 182 // values correspond to the "Part number" in the CP15/c0 register. The 183 // contents are specified in the various processor manuals. 184 // This corresponds to the Main ID Register in Technical Reference Manuals. 185 // and is used in programs like sys-utils 186 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 187 .Case("0x926", "arm926ej-s") 188 .Case("0xb02", "mpcore") 189 .Case("0xb36", "arm1136j-s") 190 .Case("0xb56", "arm1156t2-s") 191 .Case("0xb76", "arm1176jz-s") 192 .Case("0xc08", "cortex-a8") 193 .Case("0xc09", "cortex-a9") 194 .Case("0xc0f", "cortex-a15") 195 .Case("0xc20", "cortex-m0") 196 .Case("0xc23", "cortex-m3") 197 .Case("0xc24", "cortex-m4") 198 .Case("0xd22", "cortex-m55") 199 .Case("0xd02", "cortex-a34") 200 .Case("0xd04", "cortex-a35") 201 .Case("0xd03", "cortex-a53") 202 .Case("0xd07", "cortex-a57") 203 .Case("0xd08", "cortex-a72") 204 .Case("0xd09", "cortex-a73") 205 .Case("0xd0a", "cortex-a75") 206 .Case("0xd0b", "cortex-a76") 207 .Case("0xd0c", "neoverse-n1") 208 .Default("generic"); 209 } 210 211 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium. 212 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 213 if (Lines[I].startswith("CPU part")) { 214 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 215 .Case("0x516", "thunderx2t99") 216 .Case("0x0516", "thunderx2t99") 217 .Case("0xaf", "thunderx2t99") 218 .Case("0x0af", "thunderx2t99") 219 .Case("0xa1", "thunderxt88") 220 .Case("0x0a1", "thunderxt88") 221 .Default("generic"); 222 } 223 } 224 } 225 226 if (Implementer == "0x46") { // Fujitsu Ltd. 227 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 228 if (Lines[I].startswith("CPU part")) { 229 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 230 .Case("0x001", "a64fx") 231 .Default("generic"); 232 } 233 } 234 } 235 236 if (Implementer == "0x4e") { // NVIDIA Corporation 237 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 238 if (Lines[I].startswith("CPU part")) { 239 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 240 .Case("0x004", "carmel") 241 .Default("generic"); 242 } 243 } 244 } 245 246 if (Implementer == "0x48") // HiSilicon Technologies, Inc. 247 // Look for the CPU part line. 248 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 249 if (Lines[I].startswith("CPU part")) 250 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 251 // values correspond to the "Part number" in the CP15/c0 register. The 252 // contents are specified in the various processor manuals. 253 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 254 .Case("0xd01", "tsv110") 255 .Default("generic"); 256 257 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 258 // Look for the CPU part line. 259 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 260 if (Lines[I].startswith("CPU part")) 261 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 262 // values correspond to the "Part number" in the CP15/c0 register. The 263 // contents are specified in the various processor manuals. 264 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 265 .Case("0x06f", "krait") // APQ8064 266 .Case("0x201", "kryo") 267 .Case("0x205", "kryo") 268 .Case("0x211", "kryo") 269 .Case("0x800", "cortex-a73") 270 .Case("0x801", "cortex-a73") 271 .Case("0x802", "cortex-a73") 272 .Case("0x803", "cortex-a73") 273 .Case("0x804", "cortex-a73") 274 .Case("0x805", "cortex-a73") 275 .Case("0xc00", "falkor") 276 .Case("0xc01", "saphira") 277 .Default("generic"); 278 279 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. 280 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow 281 // any predictive pattern across variants and parts. 282 unsigned Variant = 0, Part = 0; 283 284 // Look for the CPU variant line, whose value is a 1 digit hexadecimal 285 // number, corresponding to the Variant bits in the CP15/C0 register. 286 for (auto I : Lines) 287 if (I.consume_front("CPU variant")) 288 I.ltrim("\t :").getAsInteger(0, Variant); 289 290 // Look for the CPU part line, whose value is a 3 digit hexadecimal 291 // number, corresponding to the PartNum bits in the CP15/C0 register. 292 for (auto I : Lines) 293 if (I.consume_front("CPU part")) 294 I.ltrim("\t :").getAsInteger(0, Part); 295 296 unsigned Exynos = (Variant << 12) | Part; 297 switch (Exynos) { 298 default: 299 // Default by falling through to Exynos M3. 300 LLVM_FALLTHROUGH; 301 case 0x1002: 302 return "exynos-m3"; 303 case 0x1003: 304 return "exynos-m4"; 305 } 306 } 307 308 return "generic"; 309 } 310 311 StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { 312 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 313 314 // The "processor 0:" line comes after a fair amount of other information, 315 // including a cache breakdown, but this should be plenty. 316 SmallVector<StringRef, 32> Lines; 317 ProcCpuinfoContent.split(Lines, "\n"); 318 319 // Look for the CPU features. 320 SmallVector<StringRef, 32> CPUFeatures; 321 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 322 if (Lines[I].startswith("features")) { 323 size_t Pos = Lines[I].find(":"); 324 if (Pos != StringRef::npos) { 325 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 326 break; 327 } 328 } 329 330 // We need to check for the presence of vector support independently of 331 // the machine type, since we may only use the vector register set when 332 // supported by the kernel (and hypervisor). 333 bool HaveVectorSupport = false; 334 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 335 if (CPUFeatures[I] == "vx") 336 HaveVectorSupport = true; 337 } 338 339 // Now check the processor machine type. 340 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 341 if (Lines[I].startswith("processor ")) { 342 size_t Pos = Lines[I].find("machine = "); 343 if (Pos != StringRef::npos) { 344 Pos += sizeof("machine = ") - 1; 345 unsigned int Id; 346 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 347 if (Id >= 8561 && HaveVectorSupport) 348 return "z15"; 349 if (Id >= 3906 && HaveVectorSupport) 350 return "z14"; 351 if (Id >= 2964 && HaveVectorSupport) 352 return "z13"; 353 if (Id >= 2827) 354 return "zEC12"; 355 if (Id >= 2817) 356 return "z196"; 357 } 358 } 359 break; 360 } 361 } 362 363 return "generic"; 364 } 365 366 StringRef sys::detail::getHostCPUNameForBPF() { 367 #if !defined(__linux__) || !defined(__x86_64__) 368 return "generic"; 369 #else 370 uint8_t v3_insns[40] __attribute__ ((aligned (8))) = 371 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 372 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 373 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 374 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 375 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 376 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 377 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 378 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 379 /* BPF_EXIT_INSN() */ 380 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 381 382 uint8_t v2_insns[40] __attribute__ ((aligned (8))) = 383 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 384 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 385 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 386 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 387 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 388 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 389 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 390 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 391 /* BPF_EXIT_INSN() */ 392 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 393 394 struct bpf_prog_load_attr { 395 uint32_t prog_type; 396 uint32_t insn_cnt; 397 uint64_t insns; 398 uint64_t license; 399 uint32_t log_level; 400 uint32_t log_size; 401 uint64_t log_buf; 402 uint32_t kern_version; 403 uint32_t prog_flags; 404 } attr = {}; 405 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 406 attr.insn_cnt = 5; 407 attr.insns = (uint64_t)v3_insns; 408 attr.license = (uint64_t)"DUMMY"; 409 410 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, 411 sizeof(attr)); 412 if (fd >= 0) { 413 close(fd); 414 return "v3"; 415 } 416 417 /* Clear the whole attr in case its content changed by syscall. */ 418 memset(&attr, 0, sizeof(attr)); 419 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 420 attr.insn_cnt = 5; 421 attr.insns = (uint64_t)v2_insns; 422 attr.license = (uint64_t)"DUMMY"; 423 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 424 if (fd >= 0) { 425 close(fd); 426 return "v2"; 427 } 428 return "v1"; 429 #endif 430 } 431 432 #if defined(__i386__) || defined(_M_IX86) || \ 433 defined(__x86_64__) || defined(_M_X64) 434 435 enum VendorSignatures { 436 SIG_INTEL = 0x756e6547 /* Genu */, 437 SIG_AMD = 0x68747541 /* Auth */ 438 }; 439 440 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 441 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 442 // support. Consequently, for i386, the presence of CPUID is checked first 443 // via the corresponding eflags bit. 444 // Removal of cpuid.h header motivated by PR30384 445 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 446 // or test-suite, but are used in external projects e.g. libstdcxx 447 static bool isCpuIdSupported() { 448 #if defined(__GNUC__) || defined(__clang__) 449 #if defined(__i386__) 450 int __cpuid_supported; 451 __asm__(" pushfl\n" 452 " popl %%eax\n" 453 " movl %%eax,%%ecx\n" 454 " xorl $0x00200000,%%eax\n" 455 " pushl %%eax\n" 456 " popfl\n" 457 " pushfl\n" 458 " popl %%eax\n" 459 " movl $0,%0\n" 460 " cmpl %%eax,%%ecx\n" 461 " je 1f\n" 462 " movl $1,%0\n" 463 "1:" 464 : "=r"(__cpuid_supported) 465 : 466 : "eax", "ecx"); 467 if (!__cpuid_supported) 468 return false; 469 #endif 470 return true; 471 #endif 472 return true; 473 } 474 475 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 476 /// the specified arguments. If we can't run cpuid on the host, return true. 477 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 478 unsigned *rECX, unsigned *rEDX) { 479 #if defined(__GNUC__) || defined(__clang__) 480 #if defined(__x86_64__) 481 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 482 // FIXME: should we save this for Clang? 483 __asm__("movq\t%%rbx, %%rsi\n\t" 484 "cpuid\n\t" 485 "xchgq\t%%rbx, %%rsi\n\t" 486 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 487 : "a"(value)); 488 return false; 489 #elif defined(__i386__) 490 __asm__("movl\t%%ebx, %%esi\n\t" 491 "cpuid\n\t" 492 "xchgl\t%%ebx, %%esi\n\t" 493 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 494 : "a"(value)); 495 return false; 496 #else 497 return true; 498 #endif 499 #elif defined(_MSC_VER) 500 // The MSVC intrinsic is portable across x86 and x64. 501 int registers[4]; 502 __cpuid(registers, value); 503 *rEAX = registers[0]; 504 *rEBX = registers[1]; 505 *rECX = registers[2]; 506 *rEDX = registers[3]; 507 return false; 508 #else 509 return true; 510 #endif 511 } 512 513 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 514 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 515 /// return true. 516 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 517 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 518 unsigned *rEDX) { 519 #if defined(__GNUC__) || defined(__clang__) 520 #if defined(__x86_64__) 521 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 522 // FIXME: should we save this for Clang? 523 __asm__("movq\t%%rbx, %%rsi\n\t" 524 "cpuid\n\t" 525 "xchgq\t%%rbx, %%rsi\n\t" 526 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 527 : "a"(value), "c"(subleaf)); 528 return false; 529 #elif defined(__i386__) 530 __asm__("movl\t%%ebx, %%esi\n\t" 531 "cpuid\n\t" 532 "xchgl\t%%ebx, %%esi\n\t" 533 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 534 : "a"(value), "c"(subleaf)); 535 return false; 536 #else 537 return true; 538 #endif 539 #elif defined(_MSC_VER) 540 int registers[4]; 541 __cpuidex(registers, value, subleaf); 542 *rEAX = registers[0]; 543 *rEBX = registers[1]; 544 *rECX = registers[2]; 545 *rEDX = registers[3]; 546 return false; 547 #else 548 return true; 549 #endif 550 } 551 552 // Read control register 0 (XCR0). Used to detect features such as AVX. 553 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 554 #if defined(__GNUC__) || defined(__clang__) 555 // Check xgetbv; this uses a .byte sequence instead of the instruction 556 // directly because older assemblers do not include support for xgetbv and 557 // there is no easy way to conditionally compile based on the assembler used. 558 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 559 return false; 560 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 561 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 562 *rEAX = Result; 563 *rEDX = Result >> 32; 564 return false; 565 #else 566 return true; 567 #endif 568 } 569 570 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 571 unsigned *Model) { 572 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 573 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 574 if (*Family == 6 || *Family == 0xf) { 575 if (*Family == 0xf) 576 // Examine extended family ID if family ID is F. 577 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 578 // Examine extended model ID if family ID is 6 or F. 579 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 580 } 581 } 582 583 static void 584 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 585 const unsigned *Features, 586 unsigned *Type, unsigned *Subtype) { 587 auto testFeature = [&](unsigned F) { 588 return (Features[F / 32] & (1U << (F % 32))) != 0; 589 }; 590 591 switch (Family) { 592 case 3: 593 *Type = X86::INTEL_i386; 594 break; 595 case 4: 596 *Type = X86::INTEL_i486; 597 break; 598 case 5: 599 if (testFeature(X86::FEATURE_MMX)) { 600 *Type = X86::INTEL_PENTIUM_MMX; 601 break; 602 } 603 *Type = X86::INTEL_PENTIUM; 604 break; 605 case 6: 606 switch (Model) { 607 case 0x01: // Pentium Pro processor 608 *Type = X86::INTEL_PENTIUM_PRO; 609 break; 610 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 611 // model 03 612 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 613 // model 05, and Intel Celeron processor, model 05 614 case 0x06: // Celeron processor, model 06 615 *Type = X86::INTEL_PENTIUM_II; 616 break; 617 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 618 // processor, model 07 619 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 620 // model 08, and Celeron processor, model 08 621 case 0x0a: // Pentium III Xeon processor, model 0Ah 622 case 0x0b: // Pentium III processor, model 0Bh 623 *Type = X86::INTEL_PENTIUM_III; 624 break; 625 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 626 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 627 // 0Dh. All processors are manufactured using the 90 nm process. 628 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 629 // Integrated Processor with Intel QuickAssist Technology 630 *Type = X86::INTEL_PENTIUM_M; 631 break; 632 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 633 // 0Eh. All processors are manufactured using the 65 nm process. 634 *Type = X86::INTEL_CORE_DUO; 635 break; // yonah 636 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 637 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 638 // mobile processor, Intel Core 2 Extreme processor, Intel 639 // Pentium Dual-Core processor, Intel Xeon processor, model 640 // 0Fh. All processors are manufactured using the 65 nm process. 641 case 0x16: // Intel Celeron processor model 16h. All processors are 642 // manufactured using the 65 nm process 643 *Type = X86::INTEL_CORE2; // "core2" 644 *Subtype = X86::INTEL_CORE2_65; 645 break; 646 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 647 // 17h. All processors are manufactured using the 45 nm process. 648 // 649 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 650 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 651 // the 45 nm process. 652 *Type = X86::INTEL_CORE2; // "penryn" 653 *Subtype = X86::INTEL_CORE2_45; 654 break; 655 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 656 // processors are manufactured using the 45 nm process. 657 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 658 // As found in a Summer 2010 model iMac. 659 case 0x1f: 660 case 0x2e: // Nehalem EX 661 *Type = X86::INTEL_COREI7; // "nehalem" 662 *Subtype = X86::INTEL_COREI7_NEHALEM; 663 break; 664 case 0x25: // Intel Core i7, laptop version. 665 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 666 // processors are manufactured using the 32 nm process. 667 case 0x2f: // Westmere EX 668 *Type = X86::INTEL_COREI7; // "westmere" 669 *Subtype = X86::INTEL_COREI7_WESTMERE; 670 break; 671 case 0x2a: // Intel Core i7 processor. All processors are manufactured 672 // using the 32 nm process. 673 case 0x2d: 674 *Type = X86::INTEL_COREI7; //"sandybridge" 675 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 676 break; 677 case 0x3a: 678 case 0x3e: // Ivy Bridge EP 679 *Type = X86::INTEL_COREI7; // "ivybridge" 680 *Subtype = X86::INTEL_COREI7_IVYBRIDGE; 681 break; 682 683 // Haswell: 684 case 0x3c: 685 case 0x3f: 686 case 0x45: 687 case 0x46: 688 *Type = X86::INTEL_COREI7; // "haswell" 689 *Subtype = X86::INTEL_COREI7_HASWELL; 690 break; 691 692 // Broadwell: 693 case 0x3d: 694 case 0x47: 695 case 0x4f: 696 case 0x56: 697 *Type = X86::INTEL_COREI7; // "broadwell" 698 *Subtype = X86::INTEL_COREI7_BROADWELL; 699 break; 700 701 // Skylake: 702 case 0x4e: // Skylake mobile 703 case 0x5e: // Skylake desktop 704 case 0x8e: // Kaby Lake mobile 705 case 0x9e: // Kaby Lake desktop 706 case 0xa5: // Comet Lake-H/S 707 case 0xa6: // Comet Lake-U 708 *Type = X86::INTEL_COREI7; // "skylake" 709 *Subtype = X86::INTEL_COREI7_SKYLAKE; 710 break; 711 712 // Skylake Xeon: 713 case 0x55: 714 *Type = X86::INTEL_COREI7; 715 if (testFeature(X86::FEATURE_AVX512BF16)) 716 *Subtype = X86::INTEL_COREI7_COOPERLAKE; // "cooperlake" 717 else if (testFeature(X86::FEATURE_AVX512VNNI)) 718 *Subtype = X86::INTEL_COREI7_CASCADELAKE; // "cascadelake" 719 else 720 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 721 break; 722 723 // Cannonlake: 724 case 0x66: 725 *Type = X86::INTEL_COREI7; 726 *Subtype = X86::INTEL_COREI7_CANNONLAKE; // "cannonlake" 727 break; 728 729 // Icelake: 730 case 0x7d: 731 case 0x7e: 732 *Type = X86::INTEL_COREI7; 733 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; // "icelake-client" 734 break; 735 736 // Icelake Xeon: 737 case 0x6a: 738 case 0x6c: 739 *Type = X86::INTEL_COREI7; 740 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; // "icelake-server" 741 break; 742 743 case 0x1c: // Most 45 nm Intel Atom processors 744 case 0x26: // 45 nm Atom Lincroft 745 case 0x27: // 32 nm Atom Medfield 746 case 0x35: // 32 nm Atom Midview 747 case 0x36: // 32 nm Atom Midview 748 *Type = X86::INTEL_BONNELL; 749 break; // "bonnell" 750 751 // Atom Silvermont codes from the Intel software optimization guide. 752 case 0x37: 753 case 0x4a: 754 case 0x4d: 755 case 0x5a: 756 case 0x5d: 757 case 0x4c: // really airmont 758 *Type = X86::INTEL_SILVERMONT; 759 break; // "silvermont" 760 // Goldmont: 761 case 0x5c: // Apollo Lake 762 case 0x5f: // Denverton 763 *Type = X86::INTEL_GOLDMONT; 764 break; // "goldmont" 765 case 0x7a: 766 *Type = X86::INTEL_GOLDMONT_PLUS; 767 break; 768 case 0x86: 769 *Type = X86::INTEL_TREMONT; 770 break; 771 772 case 0x57: 773 *Type = X86::INTEL_KNL; // knl 774 break; 775 776 case 0x85: 777 *Type = X86::INTEL_KNM; // knm 778 break; 779 780 default: // Unknown family 6 CPU, try to guess. 781 // TODO detect tigerlake host from model 782 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) { 783 *Type = X86::INTEL_COREI7; 784 *Subtype = X86::INTEL_COREI7_TIGERLAKE; 785 break; 786 } 787 788 if (testFeature(X86::FEATURE_AVX512VBMI2)) { 789 *Type = X86::INTEL_COREI7; 790 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; 791 break; 792 } 793 794 if (testFeature(X86::FEATURE_AVX512VBMI)) { 795 *Type = X86::INTEL_COREI7; 796 *Subtype = X86::INTEL_COREI7_CANNONLAKE; 797 break; 798 } 799 800 if (testFeature(X86::FEATURE_AVX512BF16)) { 801 *Type = X86::INTEL_COREI7; 802 *Subtype = X86::INTEL_COREI7_COOPERLAKE; 803 break; 804 } 805 806 if (testFeature(X86::FEATURE_AVX512VNNI)) { 807 *Type = X86::INTEL_COREI7; 808 *Subtype = X86::INTEL_COREI7_CASCADELAKE; 809 break; 810 } 811 812 if (testFeature(X86::FEATURE_AVX512VL)) { 813 *Type = X86::INTEL_COREI7; 814 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; 815 break; 816 } 817 818 if (testFeature(X86::FEATURE_AVX512ER)) { 819 *Type = X86::INTEL_KNL; // knl 820 break; 821 } 822 823 if (testFeature(X86::FEATURE_CLFLUSHOPT)) { 824 if (testFeature(X86::FEATURE_SHA)) { 825 *Type = X86::INTEL_GOLDMONT; 826 } else { 827 *Type = X86::INTEL_COREI7; 828 *Subtype = X86::INTEL_COREI7_SKYLAKE; 829 } 830 break; 831 } 832 if (testFeature(X86::FEATURE_ADX)) { 833 *Type = X86::INTEL_COREI7; 834 *Subtype = X86::INTEL_COREI7_BROADWELL; 835 break; 836 } 837 if (testFeature(X86::FEATURE_AVX2)) { 838 *Type = X86::INTEL_COREI7; 839 *Subtype = X86::INTEL_COREI7_HASWELL; 840 break; 841 } 842 if (testFeature(X86::FEATURE_AVX)) { 843 *Type = X86::INTEL_COREI7; 844 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 845 break; 846 } 847 if (testFeature(X86::FEATURE_SSE4_2)) { 848 if (testFeature(X86::FEATURE_MOVBE)) { 849 *Type = X86::INTEL_SILVERMONT; 850 } else { 851 *Type = X86::INTEL_COREI7; 852 *Subtype = X86::INTEL_COREI7_NEHALEM; 853 } 854 break; 855 } 856 if (testFeature(X86::FEATURE_SSE4_1)) { 857 *Type = X86::INTEL_CORE2; // "penryn" 858 *Subtype = X86::INTEL_CORE2_45; 859 break; 860 } 861 if (testFeature(X86::FEATURE_SSSE3)) { 862 if (testFeature(X86::FEATURE_MOVBE)) { 863 *Type = X86::INTEL_BONNELL; // "bonnell" 864 } else { 865 *Type = X86::INTEL_CORE2; // "core2" 866 *Subtype = X86::INTEL_CORE2_65; 867 } 868 break; 869 } 870 if (testFeature(X86::FEATURE_EM64T)) { 871 *Type = X86::INTEL_CORE2; // "core2" 872 *Subtype = X86::INTEL_CORE2_65; 873 break; 874 } 875 if (testFeature(X86::FEATURE_SSE3)) { 876 *Type = X86::INTEL_CORE_DUO; 877 break; 878 } 879 if (testFeature(X86::FEATURE_SSE2)) { 880 *Type = X86::INTEL_PENTIUM_M; 881 break; 882 } 883 if (testFeature(X86::FEATURE_SSE)) { 884 *Type = X86::INTEL_PENTIUM_III; 885 break; 886 } 887 if (testFeature(X86::FEATURE_MMX)) { 888 *Type = X86::INTEL_PENTIUM_II; 889 break; 890 } 891 *Type = X86::INTEL_PENTIUM_PRO; 892 break; 893 } 894 break; 895 case 15: { 896 if (testFeature(X86::FEATURE_EM64T)) { 897 *Type = X86::INTEL_NOCONA; 898 break; 899 } 900 if (testFeature(X86::FEATURE_SSE3)) { 901 *Type = X86::INTEL_PRESCOTT; 902 break; 903 } 904 *Type = X86::INTEL_PENTIUM_IV; 905 break; 906 } 907 default: 908 break; /*"generic"*/ 909 } 910 } 911 912 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 913 const unsigned *Features, 914 unsigned *Type, unsigned *Subtype) { 915 auto testFeature = [&](unsigned F) { 916 return (Features[F / 32] & (1U << (F % 32))) != 0; 917 }; 918 919 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 920 // appears to be no way to generate the wide variety of AMD-specific targets 921 // from the information returned from CPUID. 922 switch (Family) { 923 case 4: 924 *Type = X86::AMD_i486; 925 break; 926 case 5: 927 *Type = X86::AMDPENTIUM; 928 switch (Model) { 929 case 6: 930 case 7: 931 *Subtype = X86::AMDPENTIUM_K6; 932 break; // "k6" 933 case 8: 934 *Subtype = X86::AMDPENTIUM_K62; 935 break; // "k6-2" 936 case 9: 937 case 13: 938 *Subtype = X86::AMDPENTIUM_K63; 939 break; // "k6-3" 940 case 10: 941 *Subtype = X86::AMDPENTIUM_GEODE; 942 break; // "geode" 943 } 944 break; 945 case 6: 946 if (testFeature(X86::FEATURE_SSE)) { 947 *Type = X86::AMD_ATHLON_XP; 948 break; // "athlon-xp" 949 } 950 *Type = X86::AMD_ATHLON; 951 break; // "athlon" 952 case 15: 953 if (testFeature(X86::FEATURE_SSE3)) { 954 *Type = X86::AMD_K8SSE3; 955 break; // "k8-sse3" 956 } 957 *Type = X86::AMD_K8; 958 break; // "k8" 959 case 16: 960 *Type = X86::AMDFAM10H; // "amdfam10" 961 switch (Model) { 962 case 2: 963 *Subtype = X86::AMDFAM10H_BARCELONA; 964 break; 965 case 4: 966 *Subtype = X86::AMDFAM10H_SHANGHAI; 967 break; 968 case 8: 969 *Subtype = X86::AMDFAM10H_ISTANBUL; 970 break; 971 } 972 break; 973 case 20: 974 *Type = X86::AMD_BTVER1; 975 break; // "btver1"; 976 case 21: 977 *Type = X86::AMDFAM15H; 978 if (Model >= 0x60 && Model <= 0x7f) { 979 *Subtype = X86::AMDFAM15H_BDVER4; 980 break; // "bdver4"; 60h-7Fh: Excavator 981 } 982 if (Model >= 0x30 && Model <= 0x3f) { 983 *Subtype = X86::AMDFAM15H_BDVER3; 984 break; // "bdver3"; 30h-3Fh: Steamroller 985 } 986 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) { 987 *Subtype = X86::AMDFAM15H_BDVER2; 988 break; // "bdver2"; 02h, 10h-1Fh: Piledriver 989 } 990 if (Model <= 0x0f) { 991 *Subtype = X86::AMDFAM15H_BDVER1; 992 break; // "bdver1"; 00h-0Fh: Bulldozer 993 } 994 break; 995 case 22: 996 *Type = X86::AMD_BTVER2; 997 break; // "btver2" 998 case 23: 999 *Type = X86::AMDFAM17H; 1000 if ((Model >= 0x30 && Model <= 0x3f) || Model == 0x71) { 1001 *Subtype = X86::AMDFAM17H_ZNVER2; 1002 break; // "znver2"; 30h-3fh, 71h: Zen2 1003 } 1004 if (Model <= 0x0f) { 1005 *Subtype = X86::AMDFAM17H_ZNVER1; 1006 break; // "znver1"; 00h-0Fh: Zen1 1007 } 1008 break; 1009 default: 1010 break; // "generic" 1011 } 1012 } 1013 1014 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 1015 unsigned *Features) { 1016 unsigned EAX, EBX; 1017 1018 auto setFeature = [&](unsigned F) { 1019 Features[F / 32] |= 1U << (F % 32); 1020 }; 1021 1022 if ((EDX >> 15) & 1) 1023 setFeature(X86::FEATURE_CMOV); 1024 if ((EDX >> 23) & 1) 1025 setFeature(X86::FEATURE_MMX); 1026 if ((EDX >> 25) & 1) 1027 setFeature(X86::FEATURE_SSE); 1028 if ((EDX >> 26) & 1) 1029 setFeature(X86::FEATURE_SSE2); 1030 1031 if ((ECX >> 0) & 1) 1032 setFeature(X86::FEATURE_SSE3); 1033 if ((ECX >> 1) & 1) 1034 setFeature(X86::FEATURE_PCLMUL); 1035 if ((ECX >> 9) & 1) 1036 setFeature(X86::FEATURE_SSSE3); 1037 if ((ECX >> 12) & 1) 1038 setFeature(X86::FEATURE_FMA); 1039 if ((ECX >> 19) & 1) 1040 setFeature(X86::FEATURE_SSE4_1); 1041 if ((ECX >> 20) & 1) 1042 setFeature(X86::FEATURE_SSE4_2); 1043 if ((ECX >> 23) & 1) 1044 setFeature(X86::FEATURE_POPCNT); 1045 if ((ECX >> 25) & 1) 1046 setFeature(X86::FEATURE_AES); 1047 1048 if ((ECX >> 22) & 1) 1049 setFeature(X86::FEATURE_MOVBE); 1050 1051 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1052 // indicates that the AVX registers will be saved and restored on context 1053 // switch, then we have full AVX support. 1054 const unsigned AVXBits = (1 << 27) | (1 << 28); 1055 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 1056 ((EAX & 0x6) == 0x6); 1057 #if defined(__APPLE__) 1058 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1059 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1060 // set right now. 1061 bool HasAVX512Save = true; 1062 #else 1063 // AVX512 requires additional context to be saved by the OS. 1064 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 1065 #endif 1066 1067 if (HasAVX) 1068 setFeature(X86::FEATURE_AVX); 1069 1070 bool HasLeaf7 = 1071 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1072 1073 if (HasLeaf7 && ((EBX >> 3) & 1)) 1074 setFeature(X86::FEATURE_BMI); 1075 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 1076 setFeature(X86::FEATURE_AVX2); 1077 if (HasLeaf7 && ((EBX >> 8) & 1)) 1078 setFeature(X86::FEATURE_BMI2); 1079 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 1080 setFeature(X86::FEATURE_AVX512F); 1081 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 1082 setFeature(X86::FEATURE_AVX512DQ); 1083 if (HasLeaf7 && ((EBX >> 19) & 1)) 1084 setFeature(X86::FEATURE_ADX); 1085 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 1086 setFeature(X86::FEATURE_AVX512IFMA); 1087 if (HasLeaf7 && ((EBX >> 23) & 1)) 1088 setFeature(X86::FEATURE_CLFLUSHOPT); 1089 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 1090 setFeature(X86::FEATURE_AVX512PF); 1091 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 1092 setFeature(X86::FEATURE_AVX512ER); 1093 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 1094 setFeature(X86::FEATURE_AVX512CD); 1095 if (HasLeaf7 && ((EBX >> 29) & 1)) 1096 setFeature(X86::FEATURE_SHA); 1097 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 1098 setFeature(X86::FEATURE_AVX512BW); 1099 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 1100 setFeature(X86::FEATURE_AVX512VL); 1101 1102 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 1103 setFeature(X86::FEATURE_AVX512VBMI); 1104 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save) 1105 setFeature(X86::FEATURE_AVX512VBMI2); 1106 if (HasLeaf7 && ((ECX >> 8) & 1)) 1107 setFeature(X86::FEATURE_GFNI); 1108 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX) 1109 setFeature(X86::FEATURE_VPCLMULQDQ); 1110 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save) 1111 setFeature(X86::FEATURE_AVX512VNNI); 1112 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save) 1113 setFeature(X86::FEATURE_AVX512BITALG); 1114 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1115 setFeature(X86::FEATURE_AVX512VPOPCNTDQ); 1116 1117 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1118 setFeature(X86::FEATURE_AVX5124VNNIW); 1119 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1120 setFeature(X86::FEATURE_AVX5124FMAPS); 1121 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save) 1122 setFeature(X86::FEATURE_AVX512VP2INTERSECT); 1123 1124 bool HasLeaf7Subleaf1 = 1125 MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1126 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save) 1127 setFeature(X86::FEATURE_AVX512BF16); 1128 1129 unsigned MaxExtLevel; 1130 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1131 1132 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1133 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1134 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1135 setFeature(X86::FEATURE_SSE4_A); 1136 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1137 setFeature(X86::FEATURE_XOP); 1138 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1139 setFeature(X86::FEATURE_FMA4); 1140 1141 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1142 setFeature(X86::FEATURE_EM64T); 1143 } 1144 1145 StringRef sys::getHostCPUName() { 1146 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1147 unsigned MaxLeaf, Vendor; 1148 1149 if (!isCpuIdSupported()) 1150 return "generic"; 1151 1152 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) 1153 return "generic"; 1154 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1155 1156 unsigned Family = 0, Model = 0; 1157 unsigned Features[(X86::CPU_FEATURE_MAX + 31) / 32] = {0}; 1158 detectX86FamilyModel(EAX, &Family, &Model); 1159 getAvailableFeatures(ECX, EDX, MaxLeaf, Features); 1160 1161 unsigned Type = 0; 1162 unsigned Subtype = 0; 1163 1164 if (Vendor == SIG_INTEL) { 1165 getIntelProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1166 } else if (Vendor == SIG_AMD) { 1167 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1168 } 1169 1170 // Check subtypes first since those are more specific. 1171 #define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \ 1172 if (Subtype == X86::ENUM) \ 1173 return ARCHNAME; 1174 #include "llvm/Support/X86TargetParser.def" 1175 1176 // Now check types. 1177 #define X86_CPU_TYPE(ARCHNAME, ENUM) \ 1178 if (Type == X86::ENUM) \ 1179 return ARCHNAME; 1180 #include "llvm/Support/X86TargetParser.def" 1181 1182 return "generic"; 1183 } 1184 1185 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1186 StringRef sys::getHostCPUName() { 1187 host_basic_info_data_t hostInfo; 1188 mach_msg_type_number_t infoCount; 1189 1190 infoCount = HOST_BASIC_INFO_COUNT; 1191 mach_port_t hostPort = mach_host_self(); 1192 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1193 &infoCount); 1194 mach_port_deallocate(mach_task_self(), hostPort); 1195 1196 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1197 return "generic"; 1198 1199 switch (hostInfo.cpu_subtype) { 1200 case CPU_SUBTYPE_POWERPC_601: 1201 return "601"; 1202 case CPU_SUBTYPE_POWERPC_602: 1203 return "602"; 1204 case CPU_SUBTYPE_POWERPC_603: 1205 return "603"; 1206 case CPU_SUBTYPE_POWERPC_603e: 1207 return "603e"; 1208 case CPU_SUBTYPE_POWERPC_603ev: 1209 return "603ev"; 1210 case CPU_SUBTYPE_POWERPC_604: 1211 return "604"; 1212 case CPU_SUBTYPE_POWERPC_604e: 1213 return "604e"; 1214 case CPU_SUBTYPE_POWERPC_620: 1215 return "620"; 1216 case CPU_SUBTYPE_POWERPC_750: 1217 return "750"; 1218 case CPU_SUBTYPE_POWERPC_7400: 1219 return "7400"; 1220 case CPU_SUBTYPE_POWERPC_7450: 1221 return "7450"; 1222 case CPU_SUBTYPE_POWERPC_970: 1223 return "970"; 1224 default:; 1225 } 1226 1227 return "generic"; 1228 } 1229 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1230 StringRef sys::getHostCPUName() { 1231 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1232 StringRef Content = P ? P->getBuffer() : ""; 1233 return detail::getHostCPUNameForPowerPC(Content); 1234 } 1235 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1236 StringRef sys::getHostCPUName() { 1237 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1238 StringRef Content = P ? P->getBuffer() : ""; 1239 return detail::getHostCPUNameForARM(Content); 1240 } 1241 #elif defined(__linux__) && defined(__s390x__) 1242 StringRef sys::getHostCPUName() { 1243 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1244 StringRef Content = P ? P->getBuffer() : ""; 1245 return detail::getHostCPUNameForS390x(Content); 1246 } 1247 #elif defined(__APPLE__) && defined(__aarch64__) 1248 StringRef sys::getHostCPUName() { 1249 return "cyclone"; 1250 } 1251 #elif defined(__APPLE__) && defined(__arm__) 1252 StringRef sys::getHostCPUName() { 1253 host_basic_info_data_t hostInfo; 1254 mach_msg_type_number_t infoCount; 1255 1256 infoCount = HOST_BASIC_INFO_COUNT; 1257 mach_port_t hostPort = mach_host_self(); 1258 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1259 &infoCount); 1260 mach_port_deallocate(mach_task_self(), hostPort); 1261 1262 if (hostInfo.cpu_type != CPU_TYPE_ARM) { 1263 assert(false && "CPUType not equal to ARM should not be possible on ARM"); 1264 return "generic"; 1265 } 1266 switch (hostInfo.cpu_subtype) { 1267 case CPU_SUBTYPE_ARM_V7S: 1268 return "swift"; 1269 default:; 1270 } 1271 1272 return "generic"; 1273 } 1274 #else 1275 StringRef sys::getHostCPUName() { return "generic"; } 1276 #endif 1277 1278 #if defined(__linux__) && (defined(__i386__) || defined(__x86_64__)) 1279 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1280 // using the number of unique physical/core id pairs. The following 1281 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1282 int computeHostNumPhysicalCores() { 1283 // Enabled represents the number of physical id/core id pairs with at least 1284 // one processor id enabled by the CPU affinity mask. 1285 cpu_set_t Affinity, Enabled; 1286 if (sched_getaffinity(0, sizeof(Affinity), &Affinity) != 0) 1287 return -1; 1288 CPU_ZERO(&Enabled); 1289 1290 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1291 // mmapped because it appears to have 0 size. 1292 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1293 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1294 if (std::error_code EC = Text.getError()) { 1295 llvm::errs() << "Can't read " 1296 << "/proc/cpuinfo: " << EC.message() << "\n"; 1297 return -1; 1298 } 1299 SmallVector<StringRef, 8> strs; 1300 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1301 /*KeepEmpty=*/false); 1302 int CurProcessor = -1; 1303 int CurPhysicalId = -1; 1304 int CurSiblings = -1; 1305 int CurCoreId = -1; 1306 for (StringRef Line : strs) { 1307 std::pair<StringRef, StringRef> Data = Line.split(':'); 1308 auto Name = Data.first.trim(); 1309 auto Val = Data.second.trim(); 1310 // These fields are available if the kernel is configured with CONFIG_SMP. 1311 if (Name == "processor") 1312 Val.getAsInteger(10, CurProcessor); 1313 else if (Name == "physical id") 1314 Val.getAsInteger(10, CurPhysicalId); 1315 else if (Name == "siblings") 1316 Val.getAsInteger(10, CurSiblings); 1317 else if (Name == "core id") { 1318 Val.getAsInteger(10, CurCoreId); 1319 // The processor id corresponds to an index into cpu_set_t. 1320 if (CPU_ISSET(CurProcessor, &Affinity)) 1321 CPU_SET(CurPhysicalId * CurSiblings + CurCoreId, &Enabled); 1322 } 1323 } 1324 return CPU_COUNT(&Enabled); 1325 } 1326 #elif defined(__APPLE__) && defined(__x86_64__) 1327 #include <sys/param.h> 1328 #include <sys/sysctl.h> 1329 1330 // Gets the number of *physical cores* on the machine. 1331 int computeHostNumPhysicalCores() { 1332 uint32_t count; 1333 size_t len = sizeof(count); 1334 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1335 if (count < 1) { 1336 int nm[2]; 1337 nm[0] = CTL_HW; 1338 nm[1] = HW_AVAILCPU; 1339 sysctl(nm, 2, &count, &len, NULL, 0); 1340 if (count < 1) 1341 return -1; 1342 } 1343 return count; 1344 } 1345 #elif defined(_WIN32) && LLVM_ENABLE_THREADS != 0 1346 // Defined in llvm/lib/Support/Windows/Threading.inc 1347 int computeHostNumPhysicalCores(); 1348 #else 1349 // On other systems, return -1 to indicate unknown. 1350 static int computeHostNumPhysicalCores() { return -1; } 1351 #endif 1352 1353 int sys::getHostNumPhysicalCores() { 1354 static int NumCores = computeHostNumPhysicalCores(); 1355 return NumCores; 1356 } 1357 1358 #if defined(__i386__) || defined(_M_IX86) || \ 1359 defined(__x86_64__) || defined(_M_X64) 1360 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1361 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1362 unsigned MaxLevel; 1363 union { 1364 unsigned u[3]; 1365 char c[12]; 1366 } text; 1367 1368 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1369 MaxLevel < 1) 1370 return false; 1371 1372 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1373 1374 Features["cx8"] = (EDX >> 8) & 1; 1375 Features["cmov"] = (EDX >> 15) & 1; 1376 Features["mmx"] = (EDX >> 23) & 1; 1377 Features["fxsr"] = (EDX >> 24) & 1; 1378 Features["sse"] = (EDX >> 25) & 1; 1379 Features["sse2"] = (EDX >> 26) & 1; 1380 1381 Features["sse3"] = (ECX >> 0) & 1; 1382 Features["pclmul"] = (ECX >> 1) & 1; 1383 Features["ssse3"] = (ECX >> 9) & 1; 1384 Features["cx16"] = (ECX >> 13) & 1; 1385 Features["sse4.1"] = (ECX >> 19) & 1; 1386 Features["sse4.2"] = (ECX >> 20) & 1; 1387 Features["movbe"] = (ECX >> 22) & 1; 1388 Features["popcnt"] = (ECX >> 23) & 1; 1389 Features["aes"] = (ECX >> 25) & 1; 1390 Features["rdrnd"] = (ECX >> 30) & 1; 1391 1392 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1393 // indicates that the AVX registers will be saved and restored on context 1394 // switch, then we have full AVX support. 1395 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1396 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1397 #if defined(__APPLE__) 1398 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1399 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1400 // set right now. 1401 bool HasAVX512Save = true; 1402 #else 1403 // AVX512 requires additional context to be saved by the OS. 1404 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1405 #endif 1406 1407 Features["avx"] = HasAVXSave; 1408 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave; 1409 // Only enable XSAVE if OS has enabled support for saving YMM state. 1410 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave; 1411 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave; 1412 1413 unsigned MaxExtLevel; 1414 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1415 1416 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1417 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1418 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1); 1419 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1420 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1421 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1422 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1423 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1424 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1425 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1426 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1427 1428 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1); 1429 1430 // Miscellaneous memory related features, detected by 1431 // using the 0x80000008 leaf of the CPUID instruction 1432 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1433 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX); 1434 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1435 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1); 1436 1437 bool HasLeaf7 = 1438 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1439 1440 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1441 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1442 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1443 // AVX2 is only supported if we have the OS save support from AVX. 1444 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave; 1445 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1446 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1447 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1448 // AVX512 is only supported if the OS supports the context save for it. 1449 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1450 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1451 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1452 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1453 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1454 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1455 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1456 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1457 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1458 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1459 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1460 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1461 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1462 1463 Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1); 1464 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1465 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1466 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1); 1467 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save; 1468 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1); 1469 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1); 1470 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave; 1471 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave; 1472 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save; 1473 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save; 1474 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1475 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1); 1476 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1); 1477 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1); 1478 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1); 1479 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1); 1480 1481 Features["avx512vp2intersect"] = 1482 HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save; 1483 Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1); 1484 Features["tsxldtrk"] = HasLeaf7 && ((EDX >> 16) & 1); 1485 // There are two CPUID leafs which information associated with the pconfig 1486 // instruction: 1487 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th 1488 // bit of EDX), while the EAX=0x1b leaf returns information on the 1489 // availability of specific pconfig leafs. 1490 // The target feature here only refers to the the first of these two. 1491 // Users might need to check for the availability of specific pconfig 1492 // leaves using cpuid, since that information is ignored while 1493 // detecting features using the "-march=native" flag. 1494 // For more info, see X86 ISA docs. 1495 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1); 1496 bool HasLeaf7Subleaf1 = 1497 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1498 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save; 1499 1500 bool HasLeafD = MaxLevel >= 0xd && 1501 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1502 1503 // Only enable XSAVE if OS has enabled support for saving YMM state. 1504 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave; 1505 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave; 1506 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave; 1507 1508 bool HasLeaf14 = MaxLevel >= 0x14 && 1509 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX); 1510 1511 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1); 1512 1513 return true; 1514 } 1515 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1516 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1517 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1518 if (!P) 1519 return false; 1520 1521 SmallVector<StringRef, 32> Lines; 1522 P->getBuffer().split(Lines, "\n"); 1523 1524 SmallVector<StringRef, 32> CPUFeatures; 1525 1526 // Look for the CPU features. 1527 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1528 if (Lines[I].startswith("Features")) { 1529 Lines[I].split(CPUFeatures, ' '); 1530 break; 1531 } 1532 1533 #if defined(__aarch64__) 1534 // Keep track of which crypto features we have seen 1535 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1536 uint32_t crypto = 0; 1537 #endif 1538 1539 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1540 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1541 #if defined(__aarch64__) 1542 .Case("asimd", "neon") 1543 .Case("fp", "fp-armv8") 1544 .Case("crc32", "crc") 1545 #else 1546 .Case("half", "fp16") 1547 .Case("neon", "neon") 1548 .Case("vfpv3", "vfp3") 1549 .Case("vfpv3d16", "d16") 1550 .Case("vfpv4", "vfp4") 1551 .Case("idiva", "hwdiv-arm") 1552 .Case("idivt", "hwdiv") 1553 #endif 1554 .Default(""); 1555 1556 #if defined(__aarch64__) 1557 // We need to check crypto separately since we need all of the crypto 1558 // extensions to enable the subtarget feature 1559 if (CPUFeatures[I] == "aes") 1560 crypto |= CAP_AES; 1561 else if (CPUFeatures[I] == "pmull") 1562 crypto |= CAP_PMULL; 1563 else if (CPUFeatures[I] == "sha1") 1564 crypto |= CAP_SHA1; 1565 else if (CPUFeatures[I] == "sha2") 1566 crypto |= CAP_SHA2; 1567 #endif 1568 1569 if (LLVMFeatureStr != "") 1570 Features[LLVMFeatureStr] = true; 1571 } 1572 1573 #if defined(__aarch64__) 1574 // If we have all crypto bits we can add the feature 1575 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1576 Features["crypto"] = true; 1577 #endif 1578 1579 return true; 1580 } 1581 #elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64)) 1582 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1583 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE)) 1584 Features["neon"] = true; 1585 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE)) 1586 Features["crc"] = true; 1587 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) 1588 Features["crypto"] = true; 1589 1590 return true; 1591 } 1592 #else 1593 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1594 #endif 1595 1596 std::string sys::getProcessTriple() { 1597 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1598 Triple PT(Triple::normalize(TargetTripleString)); 1599 1600 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1601 PT = PT.get64BitArchVariant(); 1602 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1603 PT = PT.get32BitArchVariant(); 1604 1605 return PT.str(); 1606 } 1607