1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the operating system Host concept. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Support/Host.h" 15 #include "llvm/ADT/SmallSet.h" 16 #include "llvm/ADT/SmallVector.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include <assert.h> 26 #include <string.h> 27 28 // Include the platform-specific parts of this class. 29 #ifdef LLVM_ON_UNIX 30 #include "Unix/Host.inc" 31 #endif 32 #ifdef LLVM_ON_WIN32 33 #include "Windows/Host.inc" 34 #endif 35 #ifdef _MSC_VER 36 #include <intrin.h> 37 #endif 38 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 39 #include <mach/host_info.h> 40 #include <mach/mach.h> 41 #include <mach/mach_host.h> 42 #include <mach/machine.h> 43 #endif 44 45 #define DEBUG_TYPE "host-detection" 46 47 //===----------------------------------------------------------------------===// 48 // 49 // Implementations of the CPU detection routines 50 // 51 //===----------------------------------------------------------------------===// 52 53 using namespace llvm; 54 55 static std::unique_ptr<llvm::MemoryBuffer> 56 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 57 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 58 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 59 if (std::error_code EC = Text.getError()) { 60 llvm::errs() << "Can't read " 61 << "/proc/cpuinfo: " << EC.message() << "\n"; 62 return nullptr; 63 } 64 return std::move(*Text); 65 } 66 67 StringRef sys::detail::getHostCPUNameForPowerPC( 68 const StringRef &ProcCpuinfoContent) { 69 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 70 // and so we must use an operating-system interface to determine the current 71 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 72 const char *generic = "generic"; 73 74 // The cpu line is second (after the 'processor: 0' line), so if this 75 // buffer is too small then something has changed (or is wrong). 76 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 77 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 78 79 StringRef::const_iterator CIP = CPUInfoStart; 80 81 StringRef::const_iterator CPUStart = 0; 82 size_t CPULen = 0; 83 84 // We need to find the first line which starts with cpu, spaces, and a colon. 85 // After the colon, there may be some additional spaces and then the cpu type. 86 while (CIP < CPUInfoEnd && CPUStart == 0) { 87 if (CIP < CPUInfoEnd && *CIP == '\n') 88 ++CIP; 89 90 if (CIP < CPUInfoEnd && *CIP == 'c') { 91 ++CIP; 92 if (CIP < CPUInfoEnd && *CIP == 'p') { 93 ++CIP; 94 if (CIP < CPUInfoEnd && *CIP == 'u') { 95 ++CIP; 96 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 97 ++CIP; 98 99 if (CIP < CPUInfoEnd && *CIP == ':') { 100 ++CIP; 101 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 102 ++CIP; 103 104 if (CIP < CPUInfoEnd) { 105 CPUStart = CIP; 106 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 107 *CIP != ',' && *CIP != '\n')) 108 ++CIP; 109 CPULen = CIP - CPUStart; 110 } 111 } 112 } 113 } 114 } 115 116 if (CPUStart == 0) 117 while (CIP < CPUInfoEnd && *CIP != '\n') 118 ++CIP; 119 } 120 121 if (CPUStart == 0) 122 return generic; 123 124 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 125 .Case("604e", "604e") 126 .Case("604", "604") 127 .Case("7400", "7400") 128 .Case("7410", "7400") 129 .Case("7447", "7400") 130 .Case("7455", "7450") 131 .Case("G4", "g4") 132 .Case("POWER4", "970") 133 .Case("PPC970FX", "970") 134 .Case("PPC970MP", "970") 135 .Case("G5", "g5") 136 .Case("POWER5", "g5") 137 .Case("A2", "a2") 138 .Case("POWER6", "pwr6") 139 .Case("POWER7", "pwr7") 140 .Case("POWER8", "pwr8") 141 .Case("POWER8E", "pwr8") 142 .Case("POWER8NVL", "pwr8") 143 .Case("POWER9", "pwr9") 144 .Default(generic); 145 } 146 147 StringRef sys::detail::getHostCPUNameForARM( 148 const StringRef &ProcCpuinfoContent) { 149 // The cpuid register on arm is not accessible from user space. On Linux, 150 // it is exposed through the /proc/cpuinfo file. 151 152 // Read 1024 bytes from /proc/cpuinfo, which should contain the CPU part line 153 // in all cases. 154 SmallVector<StringRef, 32> Lines; 155 ProcCpuinfoContent.split(Lines, "\n"); 156 157 // Look for the CPU implementer line. 158 StringRef Implementer; 159 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 160 if (Lines[I].startswith("CPU implementer")) 161 Implementer = Lines[I].substr(15).ltrim("\t :"); 162 163 if (Implementer == "0x41") // ARM Ltd. 164 // Look for the CPU part line. 165 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 166 if (Lines[I].startswith("CPU part")) 167 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 168 // values correspond to the "Part number" in the CP15/c0 register. The 169 // contents are specified in the various processor manuals. 170 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 171 .Case("0x926", "arm926ej-s") 172 .Case("0xb02", "mpcore") 173 .Case("0xb36", "arm1136j-s") 174 .Case("0xb56", "arm1156t2-s") 175 .Case("0xb76", "arm1176jz-s") 176 .Case("0xc08", "cortex-a8") 177 .Case("0xc09", "cortex-a9") 178 .Case("0xc0f", "cortex-a15") 179 .Case("0xc20", "cortex-m0") 180 .Case("0xc23", "cortex-m3") 181 .Case("0xc24", "cortex-m4") 182 .Default("generic"); 183 184 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 185 // Look for the CPU part line. 186 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 187 if (Lines[I].startswith("CPU part")) 188 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 189 // values correspond to the "Part number" in the CP15/c0 register. The 190 // contents are specified in the various processor manuals. 191 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 192 .Case("0x06f", "krait") // APQ8064 193 .Default("generic"); 194 195 return "generic"; 196 } 197 198 StringRef sys::detail::getHostCPUNameForS390x( 199 const StringRef &ProcCpuinfoContent) { 200 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 201 202 // The "processor 0:" line comes after a fair amount of other information, 203 // including a cache breakdown, but this should be plenty. 204 SmallVector<StringRef, 32> Lines; 205 ProcCpuinfoContent.split(Lines, "\n"); 206 207 // Look for the CPU features. 208 SmallVector<StringRef, 32> CPUFeatures; 209 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 210 if (Lines[I].startswith("features")) { 211 size_t Pos = Lines[I].find(":"); 212 if (Pos != StringRef::npos) { 213 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 214 break; 215 } 216 } 217 218 // We need to check for the presence of vector support independently of 219 // the machine type, since we may only use the vector register set when 220 // supported by the kernel (and hypervisor). 221 bool HaveVectorSupport = false; 222 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 223 if (CPUFeatures[I] == "vx") 224 HaveVectorSupport = true; 225 } 226 227 // Now check the processor machine type. 228 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 229 if (Lines[I].startswith("processor ")) { 230 size_t Pos = Lines[I].find("machine = "); 231 if (Pos != StringRef::npos) { 232 Pos += sizeof("machine = ") - 1; 233 unsigned int Id; 234 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 235 if (Id >= 2964 && HaveVectorSupport) 236 return "z13"; 237 if (Id >= 2827) 238 return "zEC12"; 239 if (Id >= 2817) 240 return "z196"; 241 } 242 } 243 break; 244 } 245 } 246 247 return "generic"; 248 } 249 250 #if defined(__i386__) || defined(_M_IX86) || \ 251 defined(__x86_64__) || defined(_M_X64) 252 253 enum VendorSignatures { 254 SIG_INTEL = 0x756e6547 /* Genu */, 255 SIG_AMD = 0x68747541 /* Auth */ 256 }; 257 258 enum ProcessorVendors { 259 VENDOR_INTEL = 1, 260 VENDOR_AMD, 261 VENDOR_OTHER, 262 VENDOR_MAX 263 }; 264 265 enum ProcessorTypes { 266 INTEL_ATOM = 1, 267 INTEL_CORE2, 268 INTEL_COREI7, 269 AMDFAM10H, 270 AMDFAM15H, 271 INTEL_i386, 272 INTEL_i486, 273 INTEL_PENTIUM, 274 INTEL_PENTIUM_PRO, 275 INTEL_PENTIUM_II, 276 INTEL_PENTIUM_III, 277 INTEL_PENTIUM_IV, 278 INTEL_PENTIUM_M, 279 INTEL_CORE_DUO, 280 INTEL_XEONPHI, 281 INTEL_X86_64, 282 INTEL_NOCONA, 283 INTEL_PRESCOTT, 284 AMD_i486, 285 AMDPENTIUM, 286 AMDATHLON, 287 AMDFAM14H, 288 AMDFAM16H, 289 AMDFAM17H, 290 CPU_TYPE_MAX 291 }; 292 293 enum ProcessorSubtypes { 294 INTEL_COREI7_NEHALEM = 1, 295 INTEL_COREI7_WESTMERE, 296 INTEL_COREI7_SANDYBRIDGE, 297 AMDFAM10H_BARCELONA, 298 AMDFAM10H_SHANGHAI, 299 AMDFAM10H_ISTANBUL, 300 AMDFAM15H_BDVER1, 301 AMDFAM15H_BDVER2, 302 INTEL_PENTIUM_MMX, 303 INTEL_CORE2_65, 304 INTEL_CORE2_45, 305 INTEL_COREI7_IVYBRIDGE, 306 INTEL_COREI7_HASWELL, 307 INTEL_COREI7_BROADWELL, 308 INTEL_COREI7_SKYLAKE, 309 INTEL_COREI7_SKYLAKE_AVX512, 310 INTEL_ATOM_BONNELL, 311 INTEL_ATOM_SILVERMONT, 312 INTEL_KNIGHTS_LANDING, 313 AMDPENTIUM_K6, 314 AMDPENTIUM_K62, 315 AMDPENTIUM_K63, 316 AMDPENTIUM_GEODE, 317 AMDATHLON_TBIRD, 318 AMDATHLON_MP, 319 AMDATHLON_XP, 320 AMDATHLON_K8SSE3, 321 AMDATHLON_OPTERON, 322 AMDATHLON_FX, 323 AMDATHLON_64, 324 AMD_BTVER1, 325 AMD_BTVER2, 326 AMDFAM15H_BDVER3, 327 AMDFAM15H_BDVER4, 328 AMDFAM17H_ZNVER1, 329 CPU_SUBTYPE_MAX 330 }; 331 332 enum ProcessorFeatures { 333 FEATURE_CMOV = 0, 334 FEATURE_MMX, 335 FEATURE_POPCNT, 336 FEATURE_SSE, 337 FEATURE_SSE2, 338 FEATURE_SSE3, 339 FEATURE_SSSE3, 340 FEATURE_SSE4_1, 341 FEATURE_SSE4_2, 342 FEATURE_AVX, 343 FEATURE_AVX2, 344 FEATURE_AVX512, 345 FEATURE_AVX512SAVE, 346 FEATURE_MOVBE, 347 FEATURE_ADX, 348 FEATURE_EM64T 349 }; 350 351 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 352 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 353 // support. Consequently, for i386, the presence of CPUID is checked first 354 // via the corresponding eflags bit. 355 // Removal of cpuid.h header motivated by PR30384 356 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 357 // or test-suite, but are used in external projects e.g. libstdcxx 358 static bool isCpuIdSupported() { 359 #if defined(__GNUC__) || defined(__clang__) 360 #if defined(__i386__) 361 int __cpuid_supported; 362 __asm__(" pushfl\n" 363 " popl %%eax\n" 364 " movl %%eax,%%ecx\n" 365 " xorl $0x00200000,%%eax\n" 366 " pushl %%eax\n" 367 " popfl\n" 368 " pushfl\n" 369 " popl %%eax\n" 370 " movl $0,%0\n" 371 " cmpl %%eax,%%ecx\n" 372 " je 1f\n" 373 " movl $1,%0\n" 374 "1:" 375 : "=r"(__cpuid_supported) 376 : 377 : "eax", "ecx"); 378 if (!__cpuid_supported) 379 return false; 380 #endif 381 return true; 382 #endif 383 return true; 384 } 385 386 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 387 /// the specified arguments. If we can't run cpuid on the host, return true. 388 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 389 unsigned *rECX, unsigned *rEDX) { 390 #if defined(__GNUC__) || defined(__clang__) || defined(_MSC_VER) 391 #if defined(__GNUC__) || defined(__clang__) 392 #if defined(__x86_64__) 393 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 394 // FIXME: should we save this for Clang? 395 __asm__("movq\t%%rbx, %%rsi\n\t" 396 "cpuid\n\t" 397 "xchgq\t%%rbx, %%rsi\n\t" 398 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 399 : "a"(value)); 400 #elif defined(__i386__) 401 __asm__("movl\t%%ebx, %%esi\n\t" 402 "cpuid\n\t" 403 "xchgl\t%%ebx, %%esi\n\t" 404 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 405 : "a"(value)); 406 #else 407 assert(0 && "This method is defined only for x86."); 408 #endif 409 #elif defined(_MSC_VER) 410 // The MSVC intrinsic is portable across x86 and x64. 411 int registers[4]; 412 __cpuid(registers, value); 413 *rEAX = registers[0]; 414 *rEBX = registers[1]; 415 *rECX = registers[2]; 416 *rEDX = registers[3]; 417 #endif 418 return false; 419 #else 420 return true; 421 #endif 422 } 423 424 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 425 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 426 /// return true. 427 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 428 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 429 unsigned *rEDX) { 430 #if defined(__GNUC__) || defined(__clang__) || defined(_MSC_VER) 431 #if defined(__x86_64__) || defined(_M_X64) 432 #if defined(__GNUC__) || defined(__clang__) 433 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. 434 // FIXME: should we save this for Clang? 435 __asm__("movq\t%%rbx, %%rsi\n\t" 436 "cpuid\n\t" 437 "xchgq\t%%rbx, %%rsi\n\t" 438 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 439 : "a"(value), "c"(subleaf)); 440 #elif defined(_MSC_VER) 441 int registers[4]; 442 __cpuidex(registers, value, subleaf); 443 *rEAX = registers[0]; 444 *rEBX = registers[1]; 445 *rECX = registers[2]; 446 *rEDX = registers[3]; 447 #endif 448 #elif defined(__i386__) || defined(_M_IX86) 449 #if defined(__GNUC__) || defined(__clang__) 450 __asm__("movl\t%%ebx, %%esi\n\t" 451 "cpuid\n\t" 452 "xchgl\t%%ebx, %%esi\n\t" 453 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 454 : "a"(value), "c"(subleaf)); 455 #elif defined(_MSC_VER) 456 __asm { 457 mov eax,value 458 mov ecx,subleaf 459 cpuid 460 mov esi,rEAX 461 mov dword ptr [esi],eax 462 mov esi,rEBX 463 mov dword ptr [esi],ebx 464 mov esi,rECX 465 mov dword ptr [esi],ecx 466 mov esi,rEDX 467 mov dword ptr [esi],edx 468 } 469 #endif 470 #else 471 assert(0 && "This method is defined only for x86."); 472 #endif 473 return false; 474 #else 475 return true; 476 #endif 477 } 478 479 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 480 #if defined(__GNUC__) || defined(__clang__) 481 // Check xgetbv; this uses a .byte sequence instead of the instruction 482 // directly because older assemblers do not include support for xgetbv and 483 // there is no easy way to conditionally compile based on the assembler used. 484 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 485 return false; 486 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 487 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 488 *rEAX = Result; 489 *rEDX = Result >> 32; 490 return false; 491 #else 492 return true; 493 #endif 494 } 495 496 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 497 unsigned *Model) { 498 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 499 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 500 if (*Family == 6 || *Family == 0xf) { 501 if (*Family == 0xf) 502 // Examine extended family ID if family ID is F. 503 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 504 // Examine extended model ID if family ID is 6 or F. 505 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 506 } 507 } 508 509 static void 510 getIntelProcessorTypeAndSubtype(unsigned int Family, unsigned int Model, 511 unsigned int Brand_id, unsigned int Features, 512 unsigned *Type, unsigned *Subtype) { 513 if (Brand_id != 0) 514 return; 515 switch (Family) { 516 case 3: 517 *Type = INTEL_i386; 518 break; 519 case 4: 520 switch (Model) { 521 case 0: // Intel486 DX processors 522 case 1: // Intel486 DX processors 523 case 2: // Intel486 SX processors 524 case 3: // Intel487 processors, IntelDX2 OverDrive processors, 525 // IntelDX2 processors 526 case 4: // Intel486 SL processor 527 case 5: // IntelSX2 processors 528 case 7: // Write-Back Enhanced IntelDX2 processors 529 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors 530 default: 531 *Type = INTEL_i486; 532 break; 533 } 534 break; 535 case 5: 536 switch (Model) { 537 case 1: // Pentium OverDrive processor for Pentium processor (60, 66), 538 // Pentium processors (60, 66) 539 case 2: // Pentium OverDrive processor for Pentium processor (75, 90, 540 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133, 541 // 150, 166, 200) 542 case 3: // Pentium OverDrive processors for Intel486 processor-based 543 // systems 544 *Type = INTEL_PENTIUM; 545 break; 546 case 4: // Pentium OverDrive processor with MMX technology for Pentium 547 // processor (75, 90, 100, 120, 133), Pentium processor with 548 // MMX technology (166, 200) 549 *Type = INTEL_PENTIUM; 550 *Subtype = INTEL_PENTIUM_MMX; 551 break; 552 default: 553 *Type = INTEL_PENTIUM; 554 break; 555 } 556 break; 557 case 6: 558 switch (Model) { 559 case 0x01: // Pentium Pro processor 560 *Type = INTEL_PENTIUM_PRO; 561 break; 562 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 563 // model 03 564 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 565 // model 05, and Intel Celeron processor, model 05 566 case 0x06: // Celeron processor, model 06 567 *Type = INTEL_PENTIUM_II; 568 break; 569 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 570 // processor, model 07 571 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 572 // model 08, and Celeron processor, model 08 573 case 0x0a: // Pentium III Xeon processor, model 0Ah 574 case 0x0b: // Pentium III processor, model 0Bh 575 *Type = INTEL_PENTIUM_III; 576 break; 577 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 578 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 579 // 0Dh. All processors are manufactured using the 90 nm process. 580 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 581 // Integrated Processor with Intel QuickAssist Technology 582 *Type = INTEL_PENTIUM_M; 583 break; 584 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 585 // 0Eh. All processors are manufactured using the 65 nm process. 586 *Type = INTEL_CORE_DUO; 587 break; // yonah 588 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 589 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 590 // mobile processor, Intel Core 2 Extreme processor, Intel 591 // Pentium Dual-Core processor, Intel Xeon processor, model 592 // 0Fh. All processors are manufactured using the 65 nm process. 593 case 0x16: // Intel Celeron processor model 16h. All processors are 594 // manufactured using the 65 nm process 595 *Type = INTEL_CORE2; // "core2" 596 *Subtype = INTEL_CORE2_65; 597 break; 598 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 599 // 17h. All processors are manufactured using the 45 nm process. 600 // 601 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 602 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 603 // the 45 nm process. 604 *Type = INTEL_CORE2; // "penryn" 605 *Subtype = INTEL_CORE2_45; 606 break; 607 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 608 // processors are manufactured using the 45 nm process. 609 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 610 // As found in a Summer 2010 model iMac. 611 case 0x1f: 612 case 0x2e: // Nehalem EX 613 *Type = INTEL_COREI7; // "nehalem" 614 *Subtype = INTEL_COREI7_NEHALEM; 615 break; 616 case 0x25: // Intel Core i7, laptop version. 617 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 618 // processors are manufactured using the 32 nm process. 619 case 0x2f: // Westmere EX 620 *Type = INTEL_COREI7; // "westmere" 621 *Subtype = INTEL_COREI7_WESTMERE; 622 break; 623 case 0x2a: // Intel Core i7 processor. All processors are manufactured 624 // using the 32 nm process. 625 case 0x2d: 626 *Type = INTEL_COREI7; //"sandybridge" 627 *Subtype = INTEL_COREI7_SANDYBRIDGE; 628 break; 629 case 0x3a: 630 case 0x3e: // Ivy Bridge EP 631 *Type = INTEL_COREI7; // "ivybridge" 632 *Subtype = INTEL_COREI7_IVYBRIDGE; 633 break; 634 635 // Haswell: 636 case 0x3c: 637 case 0x3f: 638 case 0x45: 639 case 0x46: 640 *Type = INTEL_COREI7; // "haswell" 641 *Subtype = INTEL_COREI7_HASWELL; 642 break; 643 644 // Broadwell: 645 case 0x3d: 646 case 0x47: 647 case 0x4f: 648 case 0x56: 649 *Type = INTEL_COREI7; // "broadwell" 650 *Subtype = INTEL_COREI7_BROADWELL; 651 break; 652 653 // Skylake: 654 case 0x4e: // Skylake mobile 655 case 0x5e: // Skylake desktop 656 case 0x8e: // Kaby Lake mobile 657 case 0x9e: // Kaby Lake desktop 658 *Type = INTEL_COREI7; // "skylake" 659 *Subtype = INTEL_COREI7_SKYLAKE; 660 break; 661 662 // Skylake Xeon: 663 case 0x55: 664 *Type = INTEL_COREI7; 665 // Check that we really have AVX512 666 if (Features & (1 << FEATURE_AVX512)) { 667 *Subtype = INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 668 } else { 669 *Subtype = INTEL_COREI7_SKYLAKE; // "skylake" 670 } 671 break; 672 673 case 0x1c: // Most 45 nm Intel Atom processors 674 case 0x26: // 45 nm Atom Lincroft 675 case 0x27: // 32 nm Atom Medfield 676 case 0x35: // 32 nm Atom Midview 677 case 0x36: // 32 nm Atom Midview 678 *Type = INTEL_ATOM; 679 *Subtype = INTEL_ATOM_BONNELL; 680 break; // "bonnell" 681 682 // Atom Silvermont codes from the Intel software optimization guide. 683 case 0x37: 684 case 0x4a: 685 case 0x4d: 686 case 0x5a: 687 case 0x5d: 688 case 0x4c: // really airmont 689 *Type = INTEL_ATOM; 690 *Subtype = INTEL_ATOM_SILVERMONT; 691 break; // "silvermont" 692 693 case 0x57: 694 *Type = INTEL_XEONPHI; // knl 695 *Subtype = INTEL_KNIGHTS_LANDING; 696 break; 697 698 default: // Unknown family 6 CPU, try to guess. 699 if (Features & (1 << FEATURE_AVX512)) { 700 *Type = INTEL_XEONPHI; // knl 701 *Subtype = INTEL_KNIGHTS_LANDING; 702 break; 703 } 704 if (Features & (1 << FEATURE_ADX)) { 705 *Type = INTEL_COREI7; 706 *Subtype = INTEL_COREI7_BROADWELL; 707 break; 708 } 709 if (Features & (1 << FEATURE_AVX2)) { 710 *Type = INTEL_COREI7; 711 *Subtype = INTEL_COREI7_HASWELL; 712 break; 713 } 714 if (Features & (1 << FEATURE_AVX)) { 715 *Type = INTEL_COREI7; 716 *Subtype = INTEL_COREI7_SANDYBRIDGE; 717 break; 718 } 719 if (Features & (1 << FEATURE_SSE4_2)) { 720 if (Features & (1 << FEATURE_MOVBE)) { 721 *Type = INTEL_ATOM; 722 *Subtype = INTEL_ATOM_SILVERMONT; 723 } else { 724 *Type = INTEL_COREI7; 725 *Subtype = INTEL_COREI7_NEHALEM; 726 } 727 break; 728 } 729 if (Features & (1 << FEATURE_SSE4_1)) { 730 *Type = INTEL_CORE2; // "penryn" 731 *Subtype = INTEL_CORE2_45; 732 break; 733 } 734 if (Features & (1 << FEATURE_SSSE3)) { 735 if (Features & (1 << FEATURE_MOVBE)) { 736 *Type = INTEL_ATOM; 737 *Subtype = INTEL_ATOM_BONNELL; // "bonnell" 738 } else { 739 *Type = INTEL_CORE2; // "core2" 740 *Subtype = INTEL_CORE2_65; 741 } 742 break; 743 } 744 if (Features & (1 << FEATURE_EM64T)) { 745 *Type = INTEL_X86_64; 746 break; // x86-64 747 } 748 if (Features & (1 << FEATURE_SSE2)) { 749 *Type = INTEL_PENTIUM_M; 750 break; 751 } 752 if (Features & (1 << FEATURE_SSE)) { 753 *Type = INTEL_PENTIUM_III; 754 break; 755 } 756 if (Features & (1 << FEATURE_MMX)) { 757 *Type = INTEL_PENTIUM_II; 758 break; 759 } 760 *Type = INTEL_PENTIUM_PRO; 761 break; 762 } 763 break; 764 case 15: { 765 switch (Model) { 766 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are 767 // model 00h and manufactured using the 0.18 micron process. 768 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon 769 // processor MP, and Intel Celeron processor. All processors are 770 // model 01h and manufactured using the 0.18 micron process. 771 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M, 772 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron 773 // processor, and Mobile Intel Celeron processor. All processors 774 // are model 02h and manufactured using the 0.13 micron process. 775 *Type = 776 ((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV); 777 break; 778 779 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D 780 // processor. All processors are model 03h and manufactured using 781 // the 90 nm process. 782 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition, 783 // Pentium D processor, Intel Xeon processor, Intel Xeon 784 // processor MP, Intel Celeron D processor. All processors are 785 // model 04h and manufactured using the 90 nm process. 786 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor 787 // Extreme Edition, Intel Xeon processor, Intel Xeon processor 788 // MP, Intel Celeron D processor. All processors are model 06h 789 // and manufactured using the 65 nm process. 790 *Type = 791 ((Features & (1 << FEATURE_EM64T)) ? INTEL_NOCONA : INTEL_PRESCOTT); 792 break; 793 794 default: 795 *Type = 796 ((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV); 797 break; 798 } 799 break; 800 } 801 default: 802 break; /*"generic"*/ 803 } 804 } 805 806 static void getAMDProcessorTypeAndSubtype(unsigned int Family, 807 unsigned int Model, 808 unsigned int Features, 809 unsigned *Type, 810 unsigned *Subtype) { 811 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 812 // appears to be no way to generate the wide variety of AMD-specific targets 813 // from the information returned from CPUID. 814 switch (Family) { 815 case 4: 816 *Type = AMD_i486; 817 break; 818 case 5: 819 *Type = AMDPENTIUM; 820 switch (Model) { 821 case 6: 822 case 7: 823 *Subtype = AMDPENTIUM_K6; 824 break; // "k6" 825 case 8: 826 *Subtype = AMDPENTIUM_K62; 827 break; // "k6-2" 828 case 9: 829 case 13: 830 *Subtype = AMDPENTIUM_K63; 831 break; // "k6-3" 832 case 10: 833 *Subtype = AMDPENTIUM_GEODE; 834 break; // "geode" 835 } 836 break; 837 case 6: 838 *Type = AMDATHLON; 839 switch (Model) { 840 case 4: 841 *Subtype = AMDATHLON_TBIRD; 842 break; // "athlon-tbird" 843 case 6: 844 case 7: 845 case 8: 846 *Subtype = AMDATHLON_MP; 847 break; // "athlon-mp" 848 case 10: 849 *Subtype = AMDATHLON_XP; 850 break; // "athlon-xp" 851 } 852 break; 853 case 15: 854 *Type = AMDATHLON; 855 if (Features & (1 << FEATURE_SSE3)) { 856 *Subtype = AMDATHLON_K8SSE3; 857 break; // "k8-sse3" 858 } 859 switch (Model) { 860 case 1: 861 *Subtype = AMDATHLON_OPTERON; 862 break; // "opteron" 863 case 5: 864 *Subtype = AMDATHLON_FX; 865 break; // "athlon-fx"; also opteron 866 default: 867 *Subtype = AMDATHLON_64; 868 break; // "athlon64" 869 } 870 break; 871 case 16: 872 *Type = AMDFAM10H; // "amdfam10" 873 switch (Model) { 874 case 2: 875 *Subtype = AMDFAM10H_BARCELONA; 876 break; 877 case 4: 878 *Subtype = AMDFAM10H_SHANGHAI; 879 break; 880 case 8: 881 *Subtype = AMDFAM10H_ISTANBUL; 882 break; 883 } 884 break; 885 case 20: 886 *Type = AMDFAM14H; 887 *Subtype = AMD_BTVER1; 888 break; // "btver1"; 889 case 21: 890 *Type = AMDFAM15H; 891 if (!(Features & 892 (1 << FEATURE_AVX))) { // If no AVX support, provide a sane fallback. 893 *Subtype = AMD_BTVER1; 894 break; // "btver1" 895 } 896 if (Model >= 0x50 && Model <= 0x6f) { 897 *Subtype = AMDFAM15H_BDVER4; 898 break; // "bdver4"; 50h-6Fh: Excavator 899 } 900 if (Model >= 0x30 && Model <= 0x3f) { 901 *Subtype = AMDFAM15H_BDVER3; 902 break; // "bdver3"; 30h-3Fh: Steamroller 903 } 904 if (Model >= 0x10 && Model <= 0x1f) { 905 *Subtype = AMDFAM15H_BDVER2; 906 break; // "bdver2"; 10h-1Fh: Piledriver 907 } 908 if (Model <= 0x0f) { 909 *Subtype = AMDFAM15H_BDVER1; 910 break; // "bdver1"; 00h-0Fh: Bulldozer 911 } 912 break; 913 case 22: 914 *Type = AMDFAM16H; 915 if (!(Features & 916 (1 << FEATURE_AVX))) { // If no AVX support provide a sane fallback. 917 *Subtype = AMD_BTVER1; 918 break; // "btver1"; 919 } 920 *Subtype = AMD_BTVER2; 921 break; // "btver2" 922 case 23: 923 *Type = AMDFAM17H; 924 if (Features & (1 << FEATURE_ADX)) { 925 *Subtype = AMDFAM17H_ZNVER1; 926 break; // "znver1" 927 } 928 *Subtype = AMD_BTVER1; 929 break; 930 default: 931 break; // "generic" 932 } 933 } 934 935 static unsigned getAvailableFeatures(unsigned int ECX, unsigned int EDX, 936 unsigned MaxLeaf) { 937 unsigned Features = 0; 938 unsigned int EAX, EBX; 939 Features |= (((EDX >> 23) & 1) << FEATURE_MMX); 940 Features |= (((EDX >> 25) & 1) << FEATURE_SSE); 941 Features |= (((EDX >> 26) & 1) << FEATURE_SSE2); 942 Features |= (((ECX >> 0) & 1) << FEATURE_SSE3); 943 Features |= (((ECX >> 9) & 1) << FEATURE_SSSE3); 944 Features |= (((ECX >> 19) & 1) << FEATURE_SSE4_1); 945 Features |= (((ECX >> 20) & 1) << FEATURE_SSE4_2); 946 Features |= (((ECX >> 22) & 1) << FEATURE_MOVBE); 947 948 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 949 // indicates that the AVX registers will be saved and restored on context 950 // switch, then we have full AVX support. 951 const unsigned AVXBits = (1 << 27) | (1 << 28); 952 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 953 ((EAX & 0x6) == 0x6); 954 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 955 bool HasLeaf7 = 956 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 957 bool HasADX = HasLeaf7 && ((EBX >> 19) & 1); 958 bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20); 959 bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1); 960 Features |= (HasAVX << FEATURE_AVX); 961 Features |= (HasAVX2 << FEATURE_AVX2); 962 Features |= (HasAVX512 << FEATURE_AVX512); 963 Features |= (HasAVX512Save << FEATURE_AVX512SAVE); 964 Features |= (HasADX << FEATURE_ADX); 965 966 getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 967 Features |= (((EDX >> 29) & 0x1) << FEATURE_EM64T); 968 return Features; 969 } 970 971 StringRef sys::getHostCPUName() { 972 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 973 unsigned MaxLeaf, Vendor; 974 975 #if defined(__GNUC__) || defined(__clang__) 976 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here 977 // and simplify it to not invoke __cpuid (like cpu_model.c in 978 // compiler-rt/lib/builtins/cpu_model.c? 979 // Opting for the second option. 980 if(!isCpuIdSupported()) 981 return "generic"; 982 #endif 983 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX)) 984 return "generic"; 985 if (getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX)) 986 return "generic"; 987 988 unsigned Brand_id = EBX & 0xff; 989 unsigned Family = 0, Model = 0; 990 unsigned Features = 0; 991 detectX86FamilyModel(EAX, &Family, &Model); 992 Features = getAvailableFeatures(ECX, EDX, MaxLeaf); 993 994 unsigned Type; 995 unsigned Subtype; 996 997 if (Vendor == SIG_INTEL) { 998 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, &Type, 999 &Subtype); 1000 switch (Type) { 1001 case INTEL_i386: 1002 return "i386"; 1003 case INTEL_i486: 1004 return "i486"; 1005 case INTEL_PENTIUM: 1006 if (Subtype == INTEL_PENTIUM_MMX) 1007 return "pentium-mmx"; 1008 return "pentium"; 1009 case INTEL_PENTIUM_PRO: 1010 return "pentiumpro"; 1011 case INTEL_PENTIUM_II: 1012 return "pentium2"; 1013 case INTEL_PENTIUM_III: 1014 return "pentium3"; 1015 case INTEL_PENTIUM_IV: 1016 return "pentium4"; 1017 case INTEL_PENTIUM_M: 1018 return "pentium-m"; 1019 case INTEL_CORE_DUO: 1020 return "yonah"; 1021 case INTEL_CORE2: 1022 switch (Subtype) { 1023 case INTEL_CORE2_65: 1024 return "core2"; 1025 case INTEL_CORE2_45: 1026 return "penryn"; 1027 default: 1028 return "core2"; 1029 } 1030 case INTEL_COREI7: 1031 switch (Subtype) { 1032 case INTEL_COREI7_NEHALEM: 1033 return "nehalem"; 1034 case INTEL_COREI7_WESTMERE: 1035 return "westmere"; 1036 case INTEL_COREI7_SANDYBRIDGE: 1037 return "sandybridge"; 1038 case INTEL_COREI7_IVYBRIDGE: 1039 return "ivybridge"; 1040 case INTEL_COREI7_HASWELL: 1041 return "haswell"; 1042 case INTEL_COREI7_BROADWELL: 1043 return "broadwell"; 1044 case INTEL_COREI7_SKYLAKE: 1045 return "skylake"; 1046 case INTEL_COREI7_SKYLAKE_AVX512: 1047 return "skylake-avx512"; 1048 default: 1049 return "corei7"; 1050 } 1051 case INTEL_ATOM: 1052 switch (Subtype) { 1053 case INTEL_ATOM_BONNELL: 1054 return "bonnell"; 1055 case INTEL_ATOM_SILVERMONT: 1056 return "silvermont"; 1057 default: 1058 return "atom"; 1059 } 1060 case INTEL_XEONPHI: 1061 return "knl"; /*update for more variants added*/ 1062 case INTEL_X86_64: 1063 return "x86-64"; 1064 case INTEL_NOCONA: 1065 return "nocona"; 1066 case INTEL_PRESCOTT: 1067 return "prescott"; 1068 default: 1069 return "generic"; 1070 } 1071 } else if (Vendor == SIG_AMD) { 1072 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1073 switch (Type) { 1074 case AMD_i486: 1075 return "i486"; 1076 case AMDPENTIUM: 1077 switch (Subtype) { 1078 case AMDPENTIUM_K6: 1079 return "k6"; 1080 case AMDPENTIUM_K62: 1081 return "k6-2"; 1082 case AMDPENTIUM_K63: 1083 return "k6-3"; 1084 case AMDPENTIUM_GEODE: 1085 return "geode"; 1086 default: 1087 return "pentium"; 1088 } 1089 case AMDATHLON: 1090 switch (Subtype) { 1091 case AMDATHLON_TBIRD: 1092 return "athlon-tbird"; 1093 case AMDATHLON_MP: 1094 return "athlon-mp"; 1095 case AMDATHLON_XP: 1096 return "athlon-xp"; 1097 case AMDATHLON_K8SSE3: 1098 return "k8-sse3"; 1099 case AMDATHLON_OPTERON: 1100 return "opteron"; 1101 case AMDATHLON_FX: 1102 return "athlon-fx"; 1103 case AMDATHLON_64: 1104 return "athlon64"; 1105 default: 1106 return "athlon"; 1107 } 1108 case AMDFAM10H: 1109 if(Subtype == AMDFAM10H_BARCELONA) 1110 return "barcelona"; 1111 return "amdfam10"; 1112 case AMDFAM14H: 1113 return "btver1"; 1114 case AMDFAM15H: 1115 switch (Subtype) { 1116 case AMDFAM15H_BDVER1: 1117 return "bdver1"; 1118 case AMDFAM15H_BDVER2: 1119 return "bdver2"; 1120 case AMDFAM15H_BDVER3: 1121 return "bdver3"; 1122 case AMDFAM15H_BDVER4: 1123 return "bdver4"; 1124 case AMD_BTVER1: 1125 return "btver1"; 1126 default: 1127 return "amdfam15"; 1128 } 1129 case AMDFAM16H: 1130 switch (Subtype) { 1131 case AMD_BTVER1: 1132 return "btver1"; 1133 case AMD_BTVER2: 1134 return "btver2"; 1135 default: 1136 return "amdfam16"; 1137 } 1138 case AMDFAM17H: 1139 switch (Subtype) { 1140 case AMD_BTVER1: 1141 return "btver1"; 1142 case AMDFAM17H_ZNVER1: 1143 return "znver1"; 1144 default: 1145 return "amdfam17"; 1146 } 1147 default: 1148 return "generic"; 1149 } 1150 } 1151 return "generic"; 1152 } 1153 1154 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1155 StringRef sys::getHostCPUName() { 1156 host_basic_info_data_t hostInfo; 1157 mach_msg_type_number_t infoCount; 1158 1159 infoCount = HOST_BASIC_INFO_COUNT; 1160 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo, 1161 &infoCount); 1162 1163 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1164 return "generic"; 1165 1166 switch (hostInfo.cpu_subtype) { 1167 case CPU_SUBTYPE_POWERPC_601: 1168 return "601"; 1169 case CPU_SUBTYPE_POWERPC_602: 1170 return "602"; 1171 case CPU_SUBTYPE_POWERPC_603: 1172 return "603"; 1173 case CPU_SUBTYPE_POWERPC_603e: 1174 return "603e"; 1175 case CPU_SUBTYPE_POWERPC_603ev: 1176 return "603ev"; 1177 case CPU_SUBTYPE_POWERPC_604: 1178 return "604"; 1179 case CPU_SUBTYPE_POWERPC_604e: 1180 return "604e"; 1181 case CPU_SUBTYPE_POWERPC_620: 1182 return "620"; 1183 case CPU_SUBTYPE_POWERPC_750: 1184 return "750"; 1185 case CPU_SUBTYPE_POWERPC_7400: 1186 return "7400"; 1187 case CPU_SUBTYPE_POWERPC_7450: 1188 return "7450"; 1189 case CPU_SUBTYPE_POWERPC_970: 1190 return "970"; 1191 default:; 1192 } 1193 1194 return "generic"; 1195 } 1196 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1197 StringRef sys::getHostCPUName() { 1198 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1199 const StringRef& Content = P ? P->getBuffer() : ""; 1200 return detail::getHostCPUNameForPowerPC(Content); 1201 } 1202 #elif defined(__linux__) && defined(__arm__) 1203 StringRef sys::getHostCPUName() { 1204 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1205 const StringRef& Content = P ? P->getBuffer() : ""; 1206 return detail::getHostCPUNameForARM(Content); 1207 } 1208 #elif defined(__linux__) && defined(__s390x__) 1209 StringRef sys::getHostCPUName() { 1210 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1211 const StringRef& Content = P ? P->getBuffer() : ""; 1212 return detail::getHostCPUNameForS390x(Content); 1213 } 1214 #else 1215 StringRef sys::getHostCPUName() { return "generic"; } 1216 #endif 1217 1218 #if defined(__linux__) && defined(__x86_64__) 1219 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1220 // using the number of unique physical/core id pairs. The following 1221 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1222 static int computeHostNumPhysicalCores() { 1223 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1224 // mmapped because it appears to have 0 size. 1225 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1226 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1227 if (std::error_code EC = Text.getError()) { 1228 llvm::errs() << "Can't read " 1229 << "/proc/cpuinfo: " << EC.message() << "\n"; 1230 } 1231 SmallVector<StringRef, 8> strs; 1232 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1233 /*KeepEmpty=*/false); 1234 int CurPhysicalId = -1; 1235 int CurCoreId = -1; 1236 SmallSet<std::pair<int, int>, 32> UniqueItems; 1237 for (auto &Line : strs) { 1238 Line = Line.trim(); 1239 if (!Line.startswith("physical id") && !Line.startswith("core id")) 1240 continue; 1241 std::pair<StringRef, StringRef> Data = Line.split(':'); 1242 auto Name = Data.first.trim(); 1243 auto Val = Data.second.trim(); 1244 if (Name == "physical id") { 1245 assert(CurPhysicalId == -1 && 1246 "Expected a core id before seeing another physical id"); 1247 Val.getAsInteger(10, CurPhysicalId); 1248 } 1249 if (Name == "core id") { 1250 assert(CurCoreId == -1 && 1251 "Expected a physical id before seeing another core id"); 1252 Val.getAsInteger(10, CurCoreId); 1253 } 1254 if (CurPhysicalId != -1 && CurCoreId != -1) { 1255 UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId)); 1256 CurPhysicalId = -1; 1257 CurCoreId = -1; 1258 } 1259 } 1260 return UniqueItems.size(); 1261 } 1262 #elif defined(__APPLE__) && defined(__x86_64__) 1263 #include <sys/param.h> 1264 #include <sys/sysctl.h> 1265 1266 // Gets the number of *physical cores* on the machine. 1267 static int computeHostNumPhysicalCores() { 1268 uint32_t count; 1269 size_t len = sizeof(count); 1270 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1271 if (count < 1) { 1272 int nm[2]; 1273 nm[0] = CTL_HW; 1274 nm[1] = HW_AVAILCPU; 1275 sysctl(nm, 2, &count, &len, NULL, 0); 1276 if (count < 1) 1277 return -1; 1278 } 1279 return count; 1280 } 1281 #else 1282 // On other systems, return -1 to indicate unknown. 1283 static int computeHostNumPhysicalCores() { return -1; } 1284 #endif 1285 1286 int sys::getHostNumPhysicalCores() { 1287 static int NumCores = computeHostNumPhysicalCores(); 1288 return NumCores; 1289 } 1290 1291 #if defined(__i386__) || defined(_M_IX86) || \ 1292 defined(__x86_64__) || defined(_M_X64) 1293 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1294 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1295 unsigned MaxLevel; 1296 union { 1297 unsigned u[3]; 1298 char c[12]; 1299 } text; 1300 1301 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1302 MaxLevel < 1) 1303 return false; 1304 1305 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1306 1307 Features["cmov"] = (EDX >> 15) & 1; 1308 Features["mmx"] = (EDX >> 23) & 1; 1309 Features["sse"] = (EDX >> 25) & 1; 1310 Features["sse2"] = (EDX >> 26) & 1; 1311 Features["sse3"] = (ECX >> 0) & 1; 1312 Features["ssse3"] = (ECX >> 9) & 1; 1313 Features["sse4.1"] = (ECX >> 19) & 1; 1314 Features["sse4.2"] = (ECX >> 20) & 1; 1315 1316 Features["pclmul"] = (ECX >> 1) & 1; 1317 Features["cx16"] = (ECX >> 13) & 1; 1318 Features["movbe"] = (ECX >> 22) & 1; 1319 Features["popcnt"] = (ECX >> 23) & 1; 1320 Features["aes"] = (ECX >> 25) & 1; 1321 Features["rdrnd"] = (ECX >> 30) & 1; 1322 1323 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1324 // indicates that the AVX registers will be saved and restored on context 1325 // switch, then we have full AVX support. 1326 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1327 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1328 Features["avx"] = HasAVXSave; 1329 Features["fma"] = HasAVXSave && (ECX >> 12) & 1; 1330 Features["f16c"] = HasAVXSave && (ECX >> 29) & 1; 1331 1332 // Only enable XSAVE if OS has enabled support for saving YMM state. 1333 Features["xsave"] = HasAVXSave && (ECX >> 26) & 1; 1334 1335 // AVX512 requires additional context to be saved by the OS. 1336 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1337 1338 unsigned MaxExtLevel; 1339 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1340 1341 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1342 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1343 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1344 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1345 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1346 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1347 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1348 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1349 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1350 1351 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1352 !getX86CpuIDAndInfoEx(0x80000008,0x0, &EAX, &EBX, &ECX, &EDX); 1353 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1354 1355 bool HasLeaf7 = 1356 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1357 1358 // AVX2 is only supported if we have the OS save support from AVX. 1359 Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1); 1360 1361 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1362 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1363 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1364 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1365 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1366 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1367 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1368 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1369 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1370 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1371 1372 // AVX512 is only supported if the OS supports the context save for it. 1373 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1374 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1375 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1376 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1377 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1378 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1379 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1380 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1381 1382 Features["prefetchwt1"] = HasLeaf7 && (ECX & 1); 1383 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1384 // Enable protection keys 1385 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1386 1387 bool HasLeafD = MaxLevel >= 0xd && 1388 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1389 1390 // Only enable XSAVE if OS has enabled support for saving YMM state. 1391 Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1); 1392 Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1); 1393 Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1); 1394 1395 return true; 1396 } 1397 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1398 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1399 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1400 if (!P) 1401 return false; 1402 1403 SmallVector<StringRef, 32> Lines; 1404 P->getBuffer().split(Lines, "\n"); 1405 1406 SmallVector<StringRef, 32> CPUFeatures; 1407 1408 // Look for the CPU features. 1409 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1410 if (Lines[I].startswith("Features")) { 1411 Lines[I].split(CPUFeatures, ' '); 1412 break; 1413 } 1414 1415 #if defined(__aarch64__) 1416 // Keep track of which crypto features we have seen 1417 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1418 uint32_t crypto = 0; 1419 #endif 1420 1421 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1422 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1423 #if defined(__aarch64__) 1424 .Case("asimd", "neon") 1425 .Case("fp", "fp-armv8") 1426 .Case("crc32", "crc") 1427 #else 1428 .Case("half", "fp16") 1429 .Case("neon", "neon") 1430 .Case("vfpv3", "vfp3") 1431 .Case("vfpv3d16", "d16") 1432 .Case("vfpv4", "vfp4") 1433 .Case("idiva", "hwdiv-arm") 1434 .Case("idivt", "hwdiv") 1435 #endif 1436 .Default(""); 1437 1438 #if defined(__aarch64__) 1439 // We need to check crypto separately since we need all of the crypto 1440 // extensions to enable the subtarget feature 1441 if (CPUFeatures[I] == "aes") 1442 crypto |= CAP_AES; 1443 else if (CPUFeatures[I] == "pmull") 1444 crypto |= CAP_PMULL; 1445 else if (CPUFeatures[I] == "sha1") 1446 crypto |= CAP_SHA1; 1447 else if (CPUFeatures[I] == "sha2") 1448 crypto |= CAP_SHA2; 1449 #endif 1450 1451 if (LLVMFeatureStr != "") 1452 Features[LLVMFeatureStr] = true; 1453 } 1454 1455 #if defined(__aarch64__) 1456 // If we have all crypto bits we can add the feature 1457 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1458 Features["crypto"] = true; 1459 #endif 1460 1461 return true; 1462 } 1463 #else 1464 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1465 #endif 1466 1467 std::string sys::getProcessTriple() { 1468 Triple PT(Triple::normalize(LLVM_HOST_TRIPLE)); 1469 1470 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1471 PT = PT.get64BitArchVariant(); 1472 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1473 PT = PT.get32BitArchVariant(); 1474 1475 return PT.str(); 1476 } 1477