1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the operating system Host concept. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/Host.h" 14 #include "llvm/Support/TargetParser.h" 15 #include "llvm/ADT/SmallSet.h" 16 #include "llvm/ADT/SmallVector.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/llvm-config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include <assert.h> 26 #include <string.h> 27 28 // Include the platform-specific parts of this class. 29 #ifdef LLVM_ON_UNIX 30 #include "Unix/Host.inc" 31 #endif 32 #ifdef _WIN32 33 #include "Windows/Host.inc" 34 #endif 35 #ifdef _MSC_VER 36 #include <intrin.h> 37 #endif 38 #if defined(__APPLE__) && (!defined(__x86_64__)) 39 #include <mach/host_info.h> 40 #include <mach/mach.h> 41 #include <mach/mach_host.h> 42 #include <mach/machine.h> 43 #endif 44 45 #define DEBUG_TYPE "host-detection" 46 47 //===----------------------------------------------------------------------===// 48 // 49 // Implementations of the CPU detection routines 50 // 51 //===----------------------------------------------------------------------===// 52 53 using namespace llvm; 54 55 static std::unique_ptr<llvm::MemoryBuffer> 56 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 57 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 58 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 59 if (std::error_code EC = Text.getError()) { 60 llvm::errs() << "Can't read " 61 << "/proc/cpuinfo: " << EC.message() << "\n"; 62 return nullptr; 63 } 64 return std::move(*Text); 65 } 66 67 StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) { 68 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 69 // and so we must use an operating-system interface to determine the current 70 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 71 const char *generic = "generic"; 72 73 // The cpu line is second (after the 'processor: 0' line), so if this 74 // buffer is too small then something has changed (or is wrong). 75 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 76 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 77 78 StringRef::const_iterator CIP = CPUInfoStart; 79 80 StringRef::const_iterator CPUStart = 0; 81 size_t CPULen = 0; 82 83 // We need to find the first line which starts with cpu, spaces, and a colon. 84 // After the colon, there may be some additional spaces and then the cpu type. 85 while (CIP < CPUInfoEnd && CPUStart == 0) { 86 if (CIP < CPUInfoEnd && *CIP == '\n') 87 ++CIP; 88 89 if (CIP < CPUInfoEnd && *CIP == 'c') { 90 ++CIP; 91 if (CIP < CPUInfoEnd && *CIP == 'p') { 92 ++CIP; 93 if (CIP < CPUInfoEnd && *CIP == 'u') { 94 ++CIP; 95 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 96 ++CIP; 97 98 if (CIP < CPUInfoEnd && *CIP == ':') { 99 ++CIP; 100 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 101 ++CIP; 102 103 if (CIP < CPUInfoEnd) { 104 CPUStart = CIP; 105 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 106 *CIP != ',' && *CIP != '\n')) 107 ++CIP; 108 CPULen = CIP - CPUStart; 109 } 110 } 111 } 112 } 113 } 114 115 if (CPUStart == 0) 116 while (CIP < CPUInfoEnd && *CIP != '\n') 117 ++CIP; 118 } 119 120 if (CPUStart == 0) 121 return generic; 122 123 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 124 .Case("604e", "604e") 125 .Case("604", "604") 126 .Case("7400", "7400") 127 .Case("7410", "7400") 128 .Case("7447", "7400") 129 .Case("7455", "7450") 130 .Case("G4", "g4") 131 .Case("POWER4", "970") 132 .Case("PPC970FX", "970") 133 .Case("PPC970MP", "970") 134 .Case("G5", "g5") 135 .Case("POWER5", "g5") 136 .Case("A2", "a2") 137 .Case("POWER6", "pwr6") 138 .Case("POWER7", "pwr7") 139 .Case("POWER8", "pwr8") 140 .Case("POWER8E", "pwr8") 141 .Case("POWER8NVL", "pwr8") 142 .Case("POWER9", "pwr9") 143 // FIXME: If we get a simulator or machine with the capabilities of 144 // mcpu=future, we should revisit this and add the name reported by the 145 // simulator/machine. 146 .Default(generic); 147 } 148 149 StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { 150 // The cpuid register on arm is not accessible from user space. On Linux, 151 // it is exposed through the /proc/cpuinfo file. 152 153 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 154 // in all cases. 155 SmallVector<StringRef, 32> Lines; 156 ProcCpuinfoContent.split(Lines, "\n"); 157 158 // Look for the CPU implementer line. 159 StringRef Implementer; 160 StringRef Hardware; 161 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 162 if (Lines[I].startswith("CPU implementer")) 163 Implementer = Lines[I].substr(15).ltrim("\t :"); 164 if (Lines[I].startswith("Hardware")) 165 Hardware = Lines[I].substr(8).ltrim("\t :"); 166 } 167 168 if (Implementer == "0x41") { // ARM Ltd. 169 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 170 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 171 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 172 return "cortex-a53"; 173 174 175 // Look for the CPU part line. 176 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 177 if (Lines[I].startswith("CPU part")) 178 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 179 // values correspond to the "Part number" in the CP15/c0 register. The 180 // contents are specified in the various processor manuals. 181 // This corresponds to the Main ID Register in Technical Reference Manuals. 182 // and is used in programs like sys-utils 183 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 184 .Case("0x926", "arm926ej-s") 185 .Case("0xb02", "mpcore") 186 .Case("0xb36", "arm1136j-s") 187 .Case("0xb56", "arm1156t2-s") 188 .Case("0xb76", "arm1176jz-s") 189 .Case("0xc08", "cortex-a8") 190 .Case("0xc09", "cortex-a9") 191 .Case("0xc0f", "cortex-a15") 192 .Case("0xc20", "cortex-m0") 193 .Case("0xc23", "cortex-m3") 194 .Case("0xc24", "cortex-m4") 195 .Case("0xd02", "cortex-a34") 196 .Case("0xd04", "cortex-a35") 197 .Case("0xd03", "cortex-a53") 198 .Case("0xd07", "cortex-a57") 199 .Case("0xd08", "cortex-a72") 200 .Case("0xd09", "cortex-a73") 201 .Case("0xd0a", "cortex-a75") 202 .Case("0xd0b", "cortex-a76") 203 .Default("generic"); 204 } 205 206 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium. 207 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 208 if (Lines[I].startswith("CPU part")) { 209 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 210 .Case("0x516", "thunderx2t99") 211 .Case("0x0516", "thunderx2t99") 212 .Case("0xaf", "thunderx2t99") 213 .Case("0x0af", "thunderx2t99") 214 .Case("0xa1", "thunderxt88") 215 .Case("0x0a1", "thunderxt88") 216 .Default("generic"); 217 } 218 } 219 } 220 221 if (Implementer == "0x48") // HiSilicon Technologies, Inc. 222 // Look for the CPU part line. 223 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 224 if (Lines[I].startswith("CPU part")) 225 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 226 // values correspond to the "Part number" in the CP15/c0 register. The 227 // contents are specified in the various processor manuals. 228 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 229 .Case("0xd01", "tsv110") 230 .Default("generic"); 231 232 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 233 // Look for the CPU part line. 234 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 235 if (Lines[I].startswith("CPU part")) 236 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 237 // values correspond to the "Part number" in the CP15/c0 register. The 238 // contents are specified in the various processor manuals. 239 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 240 .Case("0x06f", "krait") // APQ8064 241 .Case("0x201", "kryo") 242 .Case("0x205", "kryo") 243 .Case("0x211", "kryo") 244 .Case("0x800", "cortex-a73") 245 .Case("0x801", "cortex-a73") 246 .Case("0x802", "cortex-a73") 247 .Case("0x803", "cortex-a73") 248 .Case("0x804", "cortex-a73") 249 .Case("0x805", "cortex-a73") 250 .Case("0xc00", "falkor") 251 .Case("0xc01", "saphira") 252 .Default("generic"); 253 254 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. 255 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow 256 // any predictive pattern across variants and parts. 257 unsigned Variant = 0, Part = 0; 258 259 // Look for the CPU variant line, whose value is a 1 digit hexadecimal 260 // number, corresponding to the Variant bits in the CP15/C0 register. 261 for (auto I : Lines) 262 if (I.consume_front("CPU variant")) 263 I.ltrim("\t :").getAsInteger(0, Variant); 264 265 // Look for the CPU part line, whose value is a 3 digit hexadecimal 266 // number, corresponding to the PartNum bits in the CP15/C0 register. 267 for (auto I : Lines) 268 if (I.consume_front("CPU part")) 269 I.ltrim("\t :").getAsInteger(0, Part); 270 271 unsigned Exynos = (Variant << 12) | Part; 272 switch (Exynos) { 273 default: 274 // Default by falling through to Exynos M3. 275 LLVM_FALLTHROUGH; 276 case 0x1002: 277 return "exynos-m3"; 278 case 0x1003: 279 return "exynos-m4"; 280 } 281 } 282 283 return "generic"; 284 } 285 286 StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { 287 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 288 289 // The "processor 0:" line comes after a fair amount of other information, 290 // including a cache breakdown, but this should be plenty. 291 SmallVector<StringRef, 32> Lines; 292 ProcCpuinfoContent.split(Lines, "\n"); 293 294 // Look for the CPU features. 295 SmallVector<StringRef, 32> CPUFeatures; 296 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 297 if (Lines[I].startswith("features")) { 298 size_t Pos = Lines[I].find(":"); 299 if (Pos != StringRef::npos) { 300 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 301 break; 302 } 303 } 304 305 // We need to check for the presence of vector support independently of 306 // the machine type, since we may only use the vector register set when 307 // supported by the kernel (and hypervisor). 308 bool HaveVectorSupport = false; 309 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 310 if (CPUFeatures[I] == "vx") 311 HaveVectorSupport = true; 312 } 313 314 // Now check the processor machine type. 315 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 316 if (Lines[I].startswith("processor ")) { 317 size_t Pos = Lines[I].find("machine = "); 318 if (Pos != StringRef::npos) { 319 Pos += sizeof("machine = ") - 1; 320 unsigned int Id; 321 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 322 if (Id >= 8561 && HaveVectorSupport) 323 return "z15"; 324 if (Id >= 3906 && HaveVectorSupport) 325 return "z14"; 326 if (Id >= 2964 && HaveVectorSupport) 327 return "z13"; 328 if (Id >= 2827) 329 return "zEC12"; 330 if (Id >= 2817) 331 return "z196"; 332 } 333 } 334 break; 335 } 336 } 337 338 return "generic"; 339 } 340 341 StringRef sys::detail::getHostCPUNameForBPF() { 342 #if !defined(__linux__) || !defined(__x86_64__) 343 return "generic"; 344 #else 345 uint8_t v3_insns[40] __attribute__ ((aligned (8))) = 346 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 347 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 348 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 349 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 350 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 351 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 352 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 353 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 354 /* BPF_EXIT_INSN() */ 355 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 356 357 uint8_t v2_insns[40] __attribute__ ((aligned (8))) = 358 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 359 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 360 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 361 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 362 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 363 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 364 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 365 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 366 /* BPF_EXIT_INSN() */ 367 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 368 369 struct bpf_prog_load_attr { 370 uint32_t prog_type; 371 uint32_t insn_cnt; 372 uint64_t insns; 373 uint64_t license; 374 uint32_t log_level; 375 uint32_t log_size; 376 uint64_t log_buf; 377 uint32_t kern_version; 378 uint32_t prog_flags; 379 } attr = {}; 380 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 381 attr.insn_cnt = 5; 382 attr.insns = (uint64_t)v3_insns; 383 attr.license = (uint64_t)"DUMMY"; 384 385 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, 386 sizeof(attr)); 387 if (fd >= 0) { 388 close(fd); 389 return "v3"; 390 } 391 392 /* Clear the whole attr in case its content changed by syscall. */ 393 memset(&attr, 0, sizeof(attr)); 394 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 395 attr.insn_cnt = 5; 396 attr.insns = (uint64_t)v2_insns; 397 attr.license = (uint64_t)"DUMMY"; 398 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 399 if (fd >= 0) { 400 close(fd); 401 return "v2"; 402 } 403 return "v1"; 404 #endif 405 } 406 407 #if defined(__i386__) || defined(_M_IX86) || \ 408 defined(__x86_64__) || defined(_M_X64) 409 410 enum VendorSignatures { 411 SIG_INTEL = 0x756e6547 /* Genu */, 412 SIG_AMD = 0x68747541 /* Auth */ 413 }; 414 415 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 416 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 417 // support. Consequently, for i386, the presence of CPUID is checked first 418 // via the corresponding eflags bit. 419 // Removal of cpuid.h header motivated by PR30384 420 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 421 // or test-suite, but are used in external projects e.g. libstdcxx 422 static bool isCpuIdSupported() { 423 #if defined(__GNUC__) || defined(__clang__) 424 #if defined(__i386__) 425 int __cpuid_supported; 426 __asm__(" pushfl\n" 427 " popl %%eax\n" 428 " movl %%eax,%%ecx\n" 429 " xorl $0x00200000,%%eax\n" 430 " pushl %%eax\n" 431 " popfl\n" 432 " pushfl\n" 433 " popl %%eax\n" 434 " movl $0,%0\n" 435 " cmpl %%eax,%%ecx\n" 436 " je 1f\n" 437 " movl $1,%0\n" 438 "1:" 439 : "=r"(__cpuid_supported) 440 : 441 : "eax", "ecx"); 442 if (!__cpuid_supported) 443 return false; 444 #endif 445 return true; 446 #endif 447 return true; 448 } 449 450 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 451 /// the specified arguments. If we can't run cpuid on the host, return true. 452 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 453 unsigned *rECX, unsigned *rEDX) { 454 #if defined(__GNUC__) || defined(__clang__) 455 #if defined(__x86_64__) 456 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 457 // FIXME: should we save this for Clang? 458 __asm__("movq\t%%rbx, %%rsi\n\t" 459 "cpuid\n\t" 460 "xchgq\t%%rbx, %%rsi\n\t" 461 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 462 : "a"(value)); 463 return false; 464 #elif defined(__i386__) 465 __asm__("movl\t%%ebx, %%esi\n\t" 466 "cpuid\n\t" 467 "xchgl\t%%ebx, %%esi\n\t" 468 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 469 : "a"(value)); 470 return false; 471 #else 472 return true; 473 #endif 474 #elif defined(_MSC_VER) 475 // The MSVC intrinsic is portable across x86 and x64. 476 int registers[4]; 477 __cpuid(registers, value); 478 *rEAX = registers[0]; 479 *rEBX = registers[1]; 480 *rECX = registers[2]; 481 *rEDX = registers[3]; 482 return false; 483 #else 484 return true; 485 #endif 486 } 487 488 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 489 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 490 /// return true. 491 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 492 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 493 unsigned *rEDX) { 494 #if defined(__GNUC__) || defined(__clang__) 495 #if defined(__x86_64__) 496 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 497 // FIXME: should we save this for Clang? 498 __asm__("movq\t%%rbx, %%rsi\n\t" 499 "cpuid\n\t" 500 "xchgq\t%%rbx, %%rsi\n\t" 501 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 502 : "a"(value), "c"(subleaf)); 503 return false; 504 #elif defined(__i386__) 505 __asm__("movl\t%%ebx, %%esi\n\t" 506 "cpuid\n\t" 507 "xchgl\t%%ebx, %%esi\n\t" 508 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 509 : "a"(value), "c"(subleaf)); 510 return false; 511 #else 512 return true; 513 #endif 514 #elif defined(_MSC_VER) 515 int registers[4]; 516 __cpuidex(registers, value, subleaf); 517 *rEAX = registers[0]; 518 *rEBX = registers[1]; 519 *rECX = registers[2]; 520 *rEDX = registers[3]; 521 return false; 522 #else 523 return true; 524 #endif 525 } 526 527 // Read control register 0 (XCR0). Used to detect features such as AVX. 528 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 529 #if defined(__GNUC__) || defined(__clang__) 530 // Check xgetbv; this uses a .byte sequence instead of the instruction 531 // directly because older assemblers do not include support for xgetbv and 532 // there is no easy way to conditionally compile based on the assembler used. 533 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 534 return false; 535 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 536 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 537 *rEAX = Result; 538 *rEDX = Result >> 32; 539 return false; 540 #else 541 return true; 542 #endif 543 } 544 545 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 546 unsigned *Model) { 547 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 548 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 549 if (*Family == 6 || *Family == 0xf) { 550 if (*Family == 0xf) 551 // Examine extended family ID if family ID is F. 552 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 553 // Examine extended model ID if family ID is 6 or F. 554 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 555 } 556 } 557 558 static void 559 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 560 unsigned Brand_id, unsigned Features, 561 unsigned Features2, unsigned Features3, 562 unsigned *Type, unsigned *Subtype) { 563 if (Brand_id != 0) 564 return; 565 switch (Family) { 566 case 3: 567 *Type = X86::INTEL_i386; 568 break; 569 case 4: 570 *Type = X86::INTEL_i486; 571 break; 572 case 5: 573 if (Features & (1 << X86::FEATURE_MMX)) { 574 *Type = X86::INTEL_PENTIUM_MMX; 575 break; 576 } 577 *Type = X86::INTEL_PENTIUM; 578 break; 579 case 6: 580 switch (Model) { 581 case 0x01: // Pentium Pro processor 582 *Type = X86::INTEL_PENTIUM_PRO; 583 break; 584 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 585 // model 03 586 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 587 // model 05, and Intel Celeron processor, model 05 588 case 0x06: // Celeron processor, model 06 589 *Type = X86::INTEL_PENTIUM_II; 590 break; 591 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 592 // processor, model 07 593 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 594 // model 08, and Celeron processor, model 08 595 case 0x0a: // Pentium III Xeon processor, model 0Ah 596 case 0x0b: // Pentium III processor, model 0Bh 597 *Type = X86::INTEL_PENTIUM_III; 598 break; 599 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 600 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 601 // 0Dh. All processors are manufactured using the 90 nm process. 602 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 603 // Integrated Processor with Intel QuickAssist Technology 604 *Type = X86::INTEL_PENTIUM_M; 605 break; 606 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 607 // 0Eh. All processors are manufactured using the 65 nm process. 608 *Type = X86::INTEL_CORE_DUO; 609 break; // yonah 610 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 611 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 612 // mobile processor, Intel Core 2 Extreme processor, Intel 613 // Pentium Dual-Core processor, Intel Xeon processor, model 614 // 0Fh. All processors are manufactured using the 65 nm process. 615 case 0x16: // Intel Celeron processor model 16h. All processors are 616 // manufactured using the 65 nm process 617 *Type = X86::INTEL_CORE2; // "core2" 618 *Subtype = X86::INTEL_CORE2_65; 619 break; 620 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 621 // 17h. All processors are manufactured using the 45 nm process. 622 // 623 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 624 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 625 // the 45 nm process. 626 *Type = X86::INTEL_CORE2; // "penryn" 627 *Subtype = X86::INTEL_CORE2_45; 628 break; 629 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 630 // processors are manufactured using the 45 nm process. 631 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 632 // As found in a Summer 2010 model iMac. 633 case 0x1f: 634 case 0x2e: // Nehalem EX 635 *Type = X86::INTEL_COREI7; // "nehalem" 636 *Subtype = X86::INTEL_COREI7_NEHALEM; 637 break; 638 case 0x25: // Intel Core i7, laptop version. 639 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 640 // processors are manufactured using the 32 nm process. 641 case 0x2f: // Westmere EX 642 *Type = X86::INTEL_COREI7; // "westmere" 643 *Subtype = X86::INTEL_COREI7_WESTMERE; 644 break; 645 case 0x2a: // Intel Core i7 processor. All processors are manufactured 646 // using the 32 nm process. 647 case 0x2d: 648 *Type = X86::INTEL_COREI7; //"sandybridge" 649 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 650 break; 651 case 0x3a: 652 case 0x3e: // Ivy Bridge EP 653 *Type = X86::INTEL_COREI7; // "ivybridge" 654 *Subtype = X86::INTEL_COREI7_IVYBRIDGE; 655 break; 656 657 // Haswell: 658 case 0x3c: 659 case 0x3f: 660 case 0x45: 661 case 0x46: 662 *Type = X86::INTEL_COREI7; // "haswell" 663 *Subtype = X86::INTEL_COREI7_HASWELL; 664 break; 665 666 // Broadwell: 667 case 0x3d: 668 case 0x47: 669 case 0x4f: 670 case 0x56: 671 *Type = X86::INTEL_COREI7; // "broadwell" 672 *Subtype = X86::INTEL_COREI7_BROADWELL; 673 break; 674 675 // Skylake: 676 case 0x4e: // Skylake mobile 677 case 0x5e: // Skylake desktop 678 case 0x8e: // Kaby Lake mobile 679 case 0x9e: // Kaby Lake desktop 680 *Type = X86::INTEL_COREI7; // "skylake" 681 *Subtype = X86::INTEL_COREI7_SKYLAKE; 682 break; 683 684 // Skylake Xeon: 685 case 0x55: 686 *Type = X86::INTEL_COREI7; 687 if (Features2 & (1 << (X86::FEATURE_AVX512BF16 - 32))) 688 *Subtype = X86::INTEL_COREI7_COOPERLAKE; // "cooperlake" 689 else if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) 690 *Subtype = X86::INTEL_COREI7_CASCADELAKE; // "cascadelake" 691 else 692 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 693 break; 694 695 // Cannonlake: 696 case 0x66: 697 *Type = X86::INTEL_COREI7; 698 *Subtype = X86::INTEL_COREI7_CANNONLAKE; // "cannonlake" 699 break; 700 701 // Icelake: 702 case 0x7d: 703 case 0x7e: 704 *Type = X86::INTEL_COREI7; 705 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; // "icelake-client" 706 break; 707 708 // Icelake Xeon: 709 case 0x6a: 710 case 0x6c: 711 *Type = X86::INTEL_COREI7; 712 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; // "icelake-server" 713 break; 714 715 case 0x1c: // Most 45 nm Intel Atom processors 716 case 0x26: // 45 nm Atom Lincroft 717 case 0x27: // 32 nm Atom Medfield 718 case 0x35: // 32 nm Atom Midview 719 case 0x36: // 32 nm Atom Midview 720 *Type = X86::INTEL_BONNELL; 721 break; // "bonnell" 722 723 // Atom Silvermont codes from the Intel software optimization guide. 724 case 0x37: 725 case 0x4a: 726 case 0x4d: 727 case 0x5a: 728 case 0x5d: 729 case 0x4c: // really airmont 730 *Type = X86::INTEL_SILVERMONT; 731 break; // "silvermont" 732 // Goldmont: 733 case 0x5c: // Apollo Lake 734 case 0x5f: // Denverton 735 *Type = X86::INTEL_GOLDMONT; 736 break; // "goldmont" 737 case 0x7a: 738 *Type = X86::INTEL_GOLDMONT_PLUS; 739 break; 740 case 0x86: 741 *Type = X86::INTEL_TREMONT; 742 break; 743 744 case 0x57: 745 *Type = X86::INTEL_KNL; // knl 746 break; 747 748 case 0x85: 749 *Type = X86::INTEL_KNM; // knm 750 break; 751 752 default: // Unknown family 6 CPU, try to guess. 753 // TODO detect tigerlake host 754 if (Features3 & (1 << (X86::FEATURE_AVX512VP2INTERSECT - 64))) { 755 *Type = X86::INTEL_COREI7; 756 *Subtype = X86::INTEL_COREI7_TIGERLAKE; 757 break; 758 } 759 760 if (Features & (1 << X86::FEATURE_AVX512VBMI2)) { 761 *Type = X86::INTEL_COREI7; 762 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; 763 break; 764 } 765 766 if (Features & (1 << X86::FEATURE_AVX512VBMI)) { 767 *Type = X86::INTEL_COREI7; 768 *Subtype = X86::INTEL_COREI7_CANNONLAKE; 769 break; 770 } 771 772 if (Features2 & (1 << (X86::FEATURE_AVX512BF16 - 32))) { 773 *Type = X86::INTEL_COREI7; 774 *Subtype = X86::INTEL_COREI7_COOPERLAKE; 775 break; 776 } 777 778 if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) { 779 *Type = X86::INTEL_COREI7; 780 *Subtype = X86::INTEL_COREI7_CASCADELAKE; 781 break; 782 } 783 784 if (Features & (1 << X86::FEATURE_AVX512VL)) { 785 *Type = X86::INTEL_COREI7; 786 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; 787 break; 788 } 789 790 if (Features & (1 << X86::FEATURE_AVX512ER)) { 791 *Type = X86::INTEL_KNL; // knl 792 break; 793 } 794 795 if (Features3 & (1 << (X86::FEATURE_CLFLUSHOPT - 64))) { 796 if (Features3 & (1 << (X86::FEATURE_SHA - 64))) { 797 *Type = X86::INTEL_GOLDMONT; 798 } else { 799 *Type = X86::INTEL_COREI7; 800 *Subtype = X86::INTEL_COREI7_SKYLAKE; 801 } 802 break; 803 } 804 if (Features3 & (1 << (X86::FEATURE_ADX - 64))) { 805 *Type = X86::INTEL_COREI7; 806 *Subtype = X86::INTEL_COREI7_BROADWELL; 807 break; 808 } 809 if (Features & (1 << X86::FEATURE_AVX2)) { 810 *Type = X86::INTEL_COREI7; 811 *Subtype = X86::INTEL_COREI7_HASWELL; 812 break; 813 } 814 if (Features & (1 << X86::FEATURE_AVX)) { 815 *Type = X86::INTEL_COREI7; 816 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 817 break; 818 } 819 if (Features & (1 << X86::FEATURE_SSE4_2)) { 820 if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { 821 *Type = X86::INTEL_SILVERMONT; 822 } else { 823 *Type = X86::INTEL_COREI7; 824 *Subtype = X86::INTEL_COREI7_NEHALEM; 825 } 826 break; 827 } 828 if (Features & (1 << X86::FEATURE_SSE4_1)) { 829 *Type = X86::INTEL_CORE2; // "penryn" 830 *Subtype = X86::INTEL_CORE2_45; 831 break; 832 } 833 if (Features & (1 << X86::FEATURE_SSSE3)) { 834 if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { 835 *Type = X86::INTEL_BONNELL; // "bonnell" 836 } else { 837 *Type = X86::INTEL_CORE2; // "core2" 838 *Subtype = X86::INTEL_CORE2_65; 839 } 840 break; 841 } 842 if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { 843 *Type = X86::INTEL_CORE2; // "core2" 844 *Subtype = X86::INTEL_CORE2_65; 845 break; 846 } 847 if (Features & (1 << X86::FEATURE_SSE3)) { 848 *Type = X86::INTEL_CORE_DUO; 849 break; 850 } 851 if (Features & (1 << X86::FEATURE_SSE2)) { 852 *Type = X86::INTEL_PENTIUM_M; 853 break; 854 } 855 if (Features & (1 << X86::FEATURE_SSE)) { 856 *Type = X86::INTEL_PENTIUM_III; 857 break; 858 } 859 if (Features & (1 << X86::FEATURE_MMX)) { 860 *Type = X86::INTEL_PENTIUM_II; 861 break; 862 } 863 *Type = X86::INTEL_PENTIUM_PRO; 864 break; 865 } 866 break; 867 case 15: { 868 if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { 869 *Type = X86::INTEL_NOCONA; 870 break; 871 } 872 if (Features & (1 << X86::FEATURE_SSE3)) { 873 *Type = X86::INTEL_PRESCOTT; 874 break; 875 } 876 *Type = X86::INTEL_PENTIUM_IV; 877 break; 878 } 879 default: 880 break; /*"generic"*/ 881 } 882 } 883 884 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 885 unsigned Features, unsigned *Type, 886 unsigned *Subtype) { 887 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 888 // appears to be no way to generate the wide variety of AMD-specific targets 889 // from the information returned from CPUID. 890 switch (Family) { 891 case 4: 892 *Type = X86::AMD_i486; 893 break; 894 case 5: 895 *Type = X86::AMDPENTIUM; 896 switch (Model) { 897 case 6: 898 case 7: 899 *Subtype = X86::AMDPENTIUM_K6; 900 break; // "k6" 901 case 8: 902 *Subtype = X86::AMDPENTIUM_K62; 903 break; // "k6-2" 904 case 9: 905 case 13: 906 *Subtype = X86::AMDPENTIUM_K63; 907 break; // "k6-3" 908 case 10: 909 *Subtype = X86::AMDPENTIUM_GEODE; 910 break; // "geode" 911 } 912 break; 913 case 6: 914 if (Features & (1 << X86::FEATURE_SSE)) { 915 *Type = X86::AMD_ATHLON_XP; 916 break; // "athlon-xp" 917 } 918 *Type = X86::AMD_ATHLON; 919 break; // "athlon" 920 case 15: 921 if (Features & (1 << X86::FEATURE_SSE3)) { 922 *Type = X86::AMD_K8SSE3; 923 break; // "k8-sse3" 924 } 925 *Type = X86::AMD_K8; 926 break; // "k8" 927 case 16: 928 *Type = X86::AMDFAM10H; // "amdfam10" 929 switch (Model) { 930 case 2: 931 *Subtype = X86::AMDFAM10H_BARCELONA; 932 break; 933 case 4: 934 *Subtype = X86::AMDFAM10H_SHANGHAI; 935 break; 936 case 8: 937 *Subtype = X86::AMDFAM10H_ISTANBUL; 938 break; 939 } 940 break; 941 case 20: 942 *Type = X86::AMD_BTVER1; 943 break; // "btver1"; 944 case 21: 945 *Type = X86::AMDFAM15H; 946 if (Model >= 0x60 && Model <= 0x7f) { 947 *Subtype = X86::AMDFAM15H_BDVER4; 948 break; // "bdver4"; 60h-7Fh: Excavator 949 } 950 if (Model >= 0x30 && Model <= 0x3f) { 951 *Subtype = X86::AMDFAM15H_BDVER3; 952 break; // "bdver3"; 30h-3Fh: Steamroller 953 } 954 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) { 955 *Subtype = X86::AMDFAM15H_BDVER2; 956 break; // "bdver2"; 02h, 10h-1Fh: Piledriver 957 } 958 if (Model <= 0x0f) { 959 *Subtype = X86::AMDFAM15H_BDVER1; 960 break; // "bdver1"; 00h-0Fh: Bulldozer 961 } 962 break; 963 case 22: 964 *Type = X86::AMD_BTVER2; 965 break; // "btver2" 966 case 23: 967 *Type = X86::AMDFAM17H; 968 if ((Model >= 0x30 && Model <= 0x3f) || Model == 0x71) { 969 *Subtype = X86::AMDFAM17H_ZNVER2; 970 break; // "znver2"; 30h-3fh, 71h: Zen2 971 } 972 if (Model <= 0x0f) { 973 *Subtype = X86::AMDFAM17H_ZNVER1; 974 break; // "znver1"; 00h-0Fh: Zen1 975 } 976 break; 977 default: 978 break; // "generic" 979 } 980 } 981 982 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 983 unsigned *FeaturesOut, unsigned *Features2Out, 984 unsigned *Features3Out) { 985 unsigned Features = 0; 986 unsigned Features2 = 0; 987 unsigned Features3 = 0; 988 unsigned EAX, EBX; 989 990 auto setFeature = [&](unsigned F) { 991 if (F < 32) 992 Features |= 1U << (F & 0x1f); 993 else if (F < 64) 994 Features2 |= 1U << ((F - 32) & 0x1f); 995 else if (F < 96) 996 Features3 |= 1U << ((F - 64) & 0x1f); 997 else 998 llvm_unreachable("Unexpected FeatureBit"); 999 }; 1000 1001 if ((EDX >> 15) & 1) 1002 setFeature(X86::FEATURE_CMOV); 1003 if ((EDX >> 23) & 1) 1004 setFeature(X86::FEATURE_MMX); 1005 if ((EDX >> 25) & 1) 1006 setFeature(X86::FEATURE_SSE); 1007 if ((EDX >> 26) & 1) 1008 setFeature(X86::FEATURE_SSE2); 1009 1010 if ((ECX >> 0) & 1) 1011 setFeature(X86::FEATURE_SSE3); 1012 if ((ECX >> 1) & 1) 1013 setFeature(X86::FEATURE_PCLMUL); 1014 if ((ECX >> 9) & 1) 1015 setFeature(X86::FEATURE_SSSE3); 1016 if ((ECX >> 12) & 1) 1017 setFeature(X86::FEATURE_FMA); 1018 if ((ECX >> 19) & 1) 1019 setFeature(X86::FEATURE_SSE4_1); 1020 if ((ECX >> 20) & 1) 1021 setFeature(X86::FEATURE_SSE4_2); 1022 if ((ECX >> 23) & 1) 1023 setFeature(X86::FEATURE_POPCNT); 1024 if ((ECX >> 25) & 1) 1025 setFeature(X86::FEATURE_AES); 1026 1027 if ((ECX >> 22) & 1) 1028 setFeature(X86::FEATURE_MOVBE); 1029 1030 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1031 // indicates that the AVX registers will be saved and restored on context 1032 // switch, then we have full AVX support. 1033 const unsigned AVXBits = (1 << 27) | (1 << 28); 1034 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 1035 ((EAX & 0x6) == 0x6); 1036 #if defined(__APPLE__) 1037 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1038 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1039 // set right now. 1040 bool HasAVX512Save = true; 1041 #else 1042 // AVX512 requires additional context to be saved by the OS. 1043 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 1044 #endif 1045 1046 if (HasAVX) 1047 setFeature(X86::FEATURE_AVX); 1048 1049 bool HasLeaf7 = 1050 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1051 1052 if (HasLeaf7 && ((EBX >> 3) & 1)) 1053 setFeature(X86::FEATURE_BMI); 1054 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 1055 setFeature(X86::FEATURE_AVX2); 1056 if (HasLeaf7 && ((EBX >> 8) & 1)) 1057 setFeature(X86::FEATURE_BMI2); 1058 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 1059 setFeature(X86::FEATURE_AVX512F); 1060 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 1061 setFeature(X86::FEATURE_AVX512DQ); 1062 if (HasLeaf7 && ((EBX >> 19) & 1)) 1063 setFeature(X86::FEATURE_ADX); 1064 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 1065 setFeature(X86::FEATURE_AVX512IFMA); 1066 if (HasLeaf7 && ((EBX >> 23) & 1)) 1067 setFeature(X86::FEATURE_CLFLUSHOPT); 1068 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 1069 setFeature(X86::FEATURE_AVX512PF); 1070 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 1071 setFeature(X86::FEATURE_AVX512ER); 1072 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 1073 setFeature(X86::FEATURE_AVX512CD); 1074 if (HasLeaf7 && ((EBX >> 29) & 1)) 1075 setFeature(X86::FEATURE_SHA); 1076 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 1077 setFeature(X86::FEATURE_AVX512BW); 1078 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 1079 setFeature(X86::FEATURE_AVX512VL); 1080 1081 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 1082 setFeature(X86::FEATURE_AVX512VBMI); 1083 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save) 1084 setFeature(X86::FEATURE_AVX512VBMI2); 1085 if (HasLeaf7 && ((ECX >> 8) & 1)) 1086 setFeature(X86::FEATURE_GFNI); 1087 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX) 1088 setFeature(X86::FEATURE_VPCLMULQDQ); 1089 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save) 1090 setFeature(X86::FEATURE_AVX512VNNI); 1091 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save) 1092 setFeature(X86::FEATURE_AVX512BITALG); 1093 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1094 setFeature(X86::FEATURE_AVX512VPOPCNTDQ); 1095 1096 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1097 setFeature(X86::FEATURE_AVX5124VNNIW); 1098 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1099 setFeature(X86::FEATURE_AVX5124FMAPS); 1100 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save) 1101 setFeature(X86::FEATURE_AVX512VP2INTERSECT); 1102 1103 bool HasLeaf7Subleaf1 = 1104 MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1105 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save) 1106 setFeature(X86::FEATURE_AVX512BF16); 1107 1108 unsigned MaxExtLevel; 1109 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1110 1111 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1112 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1113 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1114 setFeature(X86::FEATURE_SSE4_A); 1115 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1116 setFeature(X86::FEATURE_XOP); 1117 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1118 setFeature(X86::FEATURE_FMA4); 1119 1120 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1121 setFeature(X86::FEATURE_EM64T); 1122 1123 *FeaturesOut = Features; 1124 *Features2Out = Features2; 1125 *Features3Out = Features3; 1126 } 1127 1128 StringRef sys::getHostCPUName() { 1129 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1130 unsigned MaxLeaf, Vendor; 1131 1132 #if defined(__GNUC__) || defined(__clang__) 1133 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here 1134 // and simplify it to not invoke __cpuid (like cpu_model.c in 1135 // compiler-rt/lib/builtins/cpu_model.c? 1136 // Opting for the second option. 1137 if(!isCpuIdSupported()) 1138 return "generic"; 1139 #endif 1140 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) 1141 return "generic"; 1142 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1143 1144 unsigned Brand_id = EBX & 0xff; 1145 unsigned Family = 0, Model = 0; 1146 unsigned Features = 0, Features2 = 0, Features3 = 0; 1147 detectX86FamilyModel(EAX, &Family, &Model); 1148 getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2, &Features3); 1149 1150 unsigned Type = 0; 1151 unsigned Subtype = 0; 1152 1153 if (Vendor == SIG_INTEL) { 1154 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, 1155 Features2, Features3, &Type, &Subtype); 1156 } else if (Vendor == SIG_AMD) { 1157 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1158 } 1159 1160 // Check subtypes first since those are more specific. 1161 #define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \ 1162 if (Subtype == X86::ENUM) \ 1163 return ARCHNAME; 1164 #include "llvm/Support/X86TargetParser.def" 1165 1166 // Now check types. 1167 #define X86_CPU_TYPE(ARCHNAME, ENUM) \ 1168 if (Type == X86::ENUM) \ 1169 return ARCHNAME; 1170 #include "llvm/Support/X86TargetParser.def" 1171 1172 return "generic"; 1173 } 1174 1175 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1176 StringRef sys::getHostCPUName() { 1177 host_basic_info_data_t hostInfo; 1178 mach_msg_type_number_t infoCount; 1179 1180 infoCount = HOST_BASIC_INFO_COUNT; 1181 mach_port_t hostPort = mach_host_self(); 1182 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1183 &infoCount); 1184 mach_port_deallocate(mach_task_self(), hostPort); 1185 1186 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1187 return "generic"; 1188 1189 switch (hostInfo.cpu_subtype) { 1190 case CPU_SUBTYPE_POWERPC_601: 1191 return "601"; 1192 case CPU_SUBTYPE_POWERPC_602: 1193 return "602"; 1194 case CPU_SUBTYPE_POWERPC_603: 1195 return "603"; 1196 case CPU_SUBTYPE_POWERPC_603e: 1197 return "603e"; 1198 case CPU_SUBTYPE_POWERPC_603ev: 1199 return "603ev"; 1200 case CPU_SUBTYPE_POWERPC_604: 1201 return "604"; 1202 case CPU_SUBTYPE_POWERPC_604e: 1203 return "604e"; 1204 case CPU_SUBTYPE_POWERPC_620: 1205 return "620"; 1206 case CPU_SUBTYPE_POWERPC_750: 1207 return "750"; 1208 case CPU_SUBTYPE_POWERPC_7400: 1209 return "7400"; 1210 case CPU_SUBTYPE_POWERPC_7450: 1211 return "7450"; 1212 case CPU_SUBTYPE_POWERPC_970: 1213 return "970"; 1214 default:; 1215 } 1216 1217 return "generic"; 1218 } 1219 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1220 StringRef sys::getHostCPUName() { 1221 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1222 StringRef Content = P ? P->getBuffer() : ""; 1223 return detail::getHostCPUNameForPowerPC(Content); 1224 } 1225 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1226 StringRef sys::getHostCPUName() { 1227 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1228 StringRef Content = P ? P->getBuffer() : ""; 1229 return detail::getHostCPUNameForARM(Content); 1230 } 1231 #elif defined(__linux__) && defined(__s390x__) 1232 StringRef sys::getHostCPUName() { 1233 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1234 StringRef Content = P ? P->getBuffer() : ""; 1235 return detail::getHostCPUNameForS390x(Content); 1236 } 1237 #elif defined(__APPLE__) && defined(__aarch64__) 1238 StringRef sys::getHostCPUName() { 1239 return "cyclone"; 1240 } 1241 #elif defined(__APPLE__) && defined(__arm__) 1242 StringRef sys::getHostCPUName() { 1243 host_basic_info_data_t hostInfo; 1244 mach_msg_type_number_t infoCount; 1245 1246 infoCount = HOST_BASIC_INFO_COUNT; 1247 mach_port_t hostPort = mach_host_self(); 1248 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1249 &infoCount); 1250 mach_port_deallocate(mach_task_self(), hostPort); 1251 1252 if (hostInfo.cpu_type != CPU_TYPE_ARM) { 1253 assert(false && "CPUType not equal to ARM should not be possible on ARM"); 1254 return "generic"; 1255 } 1256 switch (hostInfo.cpu_subtype) { 1257 case CPU_SUBTYPE_ARM_V7S: 1258 return "swift"; 1259 default:; 1260 } 1261 1262 return "generic"; 1263 } 1264 #else 1265 StringRef sys::getHostCPUName() { return "generic"; } 1266 #endif 1267 1268 #if defined(__linux__) && defined(__x86_64__) 1269 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1270 // using the number of unique physical/core id pairs. The following 1271 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1272 int computeHostNumPhysicalCores() { 1273 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1274 // mmapped because it appears to have 0 size. 1275 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1276 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1277 if (std::error_code EC = Text.getError()) { 1278 llvm::errs() << "Can't read " 1279 << "/proc/cpuinfo: " << EC.message() << "\n"; 1280 return -1; 1281 } 1282 SmallVector<StringRef, 8> strs; 1283 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1284 /*KeepEmpty=*/false); 1285 int CurPhysicalId = -1; 1286 int CurCoreId = -1; 1287 SmallSet<std::pair<int, int>, 32> UniqueItems; 1288 for (auto &Line : strs) { 1289 Line = Line.trim(); 1290 if (!Line.startswith("physical id") && !Line.startswith("core id")) 1291 continue; 1292 std::pair<StringRef, StringRef> Data = Line.split(':'); 1293 auto Name = Data.first.trim(); 1294 auto Val = Data.second.trim(); 1295 if (Name == "physical id") { 1296 assert(CurPhysicalId == -1 && 1297 "Expected a core id before seeing another physical id"); 1298 Val.getAsInteger(10, CurPhysicalId); 1299 } 1300 if (Name == "core id") { 1301 assert(CurCoreId == -1 && 1302 "Expected a physical id before seeing another core id"); 1303 Val.getAsInteger(10, CurCoreId); 1304 } 1305 if (CurPhysicalId != -1 && CurCoreId != -1) { 1306 UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId)); 1307 CurPhysicalId = -1; 1308 CurCoreId = -1; 1309 } 1310 } 1311 return UniqueItems.size(); 1312 } 1313 #elif defined(__APPLE__) && defined(__x86_64__) 1314 #include <sys/param.h> 1315 #include <sys/sysctl.h> 1316 1317 // Gets the number of *physical cores* on the machine. 1318 int computeHostNumPhysicalCores() { 1319 uint32_t count; 1320 size_t len = sizeof(count); 1321 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1322 if (count < 1) { 1323 int nm[2]; 1324 nm[0] = CTL_HW; 1325 nm[1] = HW_AVAILCPU; 1326 sysctl(nm, 2, &count, &len, NULL, 0); 1327 if (count < 1) 1328 return -1; 1329 } 1330 return count; 1331 } 1332 #elif defined(_WIN32) && LLVM_ENABLE_THREADS != 0 1333 // Defined in llvm/lib/Support/Windows/Threading.inc 1334 int computeHostNumPhysicalCores(); 1335 #else 1336 // On other systems, return -1 to indicate unknown. 1337 static int computeHostNumPhysicalCores() { return -1; } 1338 #endif 1339 1340 int sys::getHostNumPhysicalCores() { 1341 static int NumCores = computeHostNumPhysicalCores(); 1342 return NumCores; 1343 } 1344 1345 #if defined(__i386__) || defined(_M_IX86) || \ 1346 defined(__x86_64__) || defined(_M_X64) 1347 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1348 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1349 unsigned MaxLevel; 1350 union { 1351 unsigned u[3]; 1352 char c[12]; 1353 } text; 1354 1355 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1356 MaxLevel < 1) 1357 return false; 1358 1359 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1360 1361 Features["cx8"] = (EDX >> 8) & 1; 1362 Features["cmov"] = (EDX >> 15) & 1; 1363 Features["mmx"] = (EDX >> 23) & 1; 1364 Features["fxsr"] = (EDX >> 24) & 1; 1365 Features["sse"] = (EDX >> 25) & 1; 1366 Features["sse2"] = (EDX >> 26) & 1; 1367 1368 Features["sse3"] = (ECX >> 0) & 1; 1369 Features["pclmul"] = (ECX >> 1) & 1; 1370 Features["ssse3"] = (ECX >> 9) & 1; 1371 Features["cx16"] = (ECX >> 13) & 1; 1372 Features["sse4.1"] = (ECX >> 19) & 1; 1373 Features["sse4.2"] = (ECX >> 20) & 1; 1374 Features["movbe"] = (ECX >> 22) & 1; 1375 Features["popcnt"] = (ECX >> 23) & 1; 1376 Features["aes"] = (ECX >> 25) & 1; 1377 Features["rdrnd"] = (ECX >> 30) & 1; 1378 1379 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1380 // indicates that the AVX registers will be saved and restored on context 1381 // switch, then we have full AVX support. 1382 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1383 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1384 #if defined(__APPLE__) 1385 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1386 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1387 // set right now. 1388 bool HasAVX512Save = true; 1389 #else 1390 // AVX512 requires additional context to be saved by the OS. 1391 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1392 #endif 1393 1394 Features["avx"] = HasAVXSave; 1395 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave; 1396 // Only enable XSAVE if OS has enabled support for saving YMM state. 1397 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave; 1398 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave; 1399 1400 unsigned MaxExtLevel; 1401 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1402 1403 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1404 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1405 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1); 1406 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1407 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1408 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1409 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1410 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1411 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1412 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1413 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1414 1415 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1); 1416 1417 // Miscellaneous memory related features, detected by 1418 // using the 0x80000008 leaf of the CPUID instruction 1419 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1420 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX); 1421 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1422 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1); 1423 1424 bool HasLeaf7 = 1425 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1426 1427 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1428 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1429 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1430 // AVX2 is only supported if we have the OS save support from AVX. 1431 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave; 1432 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1433 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1434 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1435 // AVX512 is only supported if the OS supports the context save for it. 1436 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1437 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1438 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1439 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1440 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1441 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1442 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1443 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1444 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1445 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1446 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1447 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1448 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1449 1450 Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1); 1451 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1452 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1453 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1); 1454 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save; 1455 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1); 1456 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1); 1457 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave; 1458 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave; 1459 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save; 1460 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save; 1461 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1462 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1); 1463 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1); 1464 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1); 1465 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1); 1466 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1); 1467 1468 // There are two CPUID leafs which information associated with the pconfig 1469 // instruction: 1470 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th 1471 // bit of EDX), while the EAX=0x1b leaf returns information on the 1472 // availability of specific pconfig leafs. 1473 // The target feature here only refers to the the first of these two. 1474 // Users might need to check for the availability of specific pconfig 1475 // leaves using cpuid, since that information is ignored while 1476 // detecting features using the "-march=native" flag. 1477 // For more info, see X86 ISA docs. 1478 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1); 1479 bool HasLeaf7Subleaf1 = 1480 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1481 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save; 1482 1483 bool HasLeafD = MaxLevel >= 0xd && 1484 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1485 1486 // Only enable XSAVE if OS has enabled support for saving YMM state. 1487 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave; 1488 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave; 1489 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave; 1490 1491 bool HasLeaf14 = MaxLevel >= 0x14 && 1492 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX); 1493 1494 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1); 1495 1496 return true; 1497 } 1498 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1499 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1500 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1501 if (!P) 1502 return false; 1503 1504 SmallVector<StringRef, 32> Lines; 1505 P->getBuffer().split(Lines, "\n"); 1506 1507 SmallVector<StringRef, 32> CPUFeatures; 1508 1509 // Look for the CPU features. 1510 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1511 if (Lines[I].startswith("Features")) { 1512 Lines[I].split(CPUFeatures, ' '); 1513 break; 1514 } 1515 1516 #if defined(__aarch64__) 1517 // Keep track of which crypto features we have seen 1518 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1519 uint32_t crypto = 0; 1520 #endif 1521 1522 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1523 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1524 #if defined(__aarch64__) 1525 .Case("asimd", "neon") 1526 .Case("fp", "fp-armv8") 1527 .Case("crc32", "crc") 1528 #else 1529 .Case("half", "fp16") 1530 .Case("neon", "neon") 1531 .Case("vfpv3", "vfp3") 1532 .Case("vfpv3d16", "d16") 1533 .Case("vfpv4", "vfp4") 1534 .Case("idiva", "hwdiv-arm") 1535 .Case("idivt", "hwdiv") 1536 #endif 1537 .Default(""); 1538 1539 #if defined(__aarch64__) 1540 // We need to check crypto separately since we need all of the crypto 1541 // extensions to enable the subtarget feature 1542 if (CPUFeatures[I] == "aes") 1543 crypto |= CAP_AES; 1544 else if (CPUFeatures[I] == "pmull") 1545 crypto |= CAP_PMULL; 1546 else if (CPUFeatures[I] == "sha1") 1547 crypto |= CAP_SHA1; 1548 else if (CPUFeatures[I] == "sha2") 1549 crypto |= CAP_SHA2; 1550 #endif 1551 1552 if (LLVMFeatureStr != "") 1553 Features[LLVMFeatureStr] = true; 1554 } 1555 1556 #if defined(__aarch64__) 1557 // If we have all crypto bits we can add the feature 1558 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1559 Features["crypto"] = true; 1560 #endif 1561 1562 return true; 1563 } 1564 #elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64)) 1565 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1566 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE)) 1567 Features["neon"] = true; 1568 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE)) 1569 Features["crc"] = true; 1570 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) 1571 Features["crypto"] = true; 1572 1573 return true; 1574 } 1575 #else 1576 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1577 #endif 1578 1579 std::string sys::getProcessTriple() { 1580 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1581 Triple PT(Triple::normalize(TargetTripleString)); 1582 1583 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1584 PT = PT.get64BitArchVariant(); 1585 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1586 PT = PT.get32BitArchVariant(); 1587 1588 return PT.str(); 1589 } 1590