1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the operating system Host concept. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/Host.h" 14 #include "llvm/ADT/SmallSet.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringMap.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/llvm-config.h" 21 #include "llvm/Support/BCD.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/FileSystem.h" 24 #include "llvm/Support/MemoryBuffer.h" 25 #include "llvm/Support/X86TargetParser.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <assert.h> 28 #include <string.h> 29 30 // Include the platform-specific parts of this class. 31 #ifdef LLVM_ON_UNIX 32 #include "Unix/Host.inc" 33 #include <sched.h> 34 #endif 35 #ifdef _WIN32 36 #include "Windows/Host.inc" 37 #endif 38 #ifdef _MSC_VER 39 #include <intrin.h> 40 #endif 41 #if defined(__APPLE__) && (!defined(__x86_64__)) 42 #include <mach/host_info.h> 43 #include <mach/mach.h> 44 #include <mach/mach_host.h> 45 #include <mach/machine.h> 46 #endif 47 #ifdef _AIX 48 #include <sys/systemcfg.h> 49 #endif 50 51 #define DEBUG_TYPE "host-detection" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // Implementations of the CPU detection routines 56 // 57 //===----------------------------------------------------------------------===// 58 59 using namespace llvm; 60 61 static std::unique_ptr<llvm::MemoryBuffer> 62 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 63 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 64 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 65 if (std::error_code EC = Text.getError()) { 66 llvm::errs() << "Can't read " 67 << "/proc/cpuinfo: " << EC.message() << "\n"; 68 return nullptr; 69 } 70 return std::move(*Text); 71 } 72 73 StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) { 74 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 75 // and so we must use an operating-system interface to determine the current 76 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 77 const char *generic = "generic"; 78 79 // The cpu line is second (after the 'processor: 0' line), so if this 80 // buffer is too small then something has changed (or is wrong). 81 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 82 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 83 84 StringRef::const_iterator CIP = CPUInfoStart; 85 86 StringRef::const_iterator CPUStart = nullptr; 87 size_t CPULen = 0; 88 89 // We need to find the first line which starts with cpu, spaces, and a colon. 90 // After the colon, there may be some additional spaces and then the cpu type. 91 while (CIP < CPUInfoEnd && CPUStart == nullptr) { 92 if (CIP < CPUInfoEnd && *CIP == '\n') 93 ++CIP; 94 95 if (CIP < CPUInfoEnd && *CIP == 'c') { 96 ++CIP; 97 if (CIP < CPUInfoEnd && *CIP == 'p') { 98 ++CIP; 99 if (CIP < CPUInfoEnd && *CIP == 'u') { 100 ++CIP; 101 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 102 ++CIP; 103 104 if (CIP < CPUInfoEnd && *CIP == ':') { 105 ++CIP; 106 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 107 ++CIP; 108 109 if (CIP < CPUInfoEnd) { 110 CPUStart = CIP; 111 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 112 *CIP != ',' && *CIP != '\n')) 113 ++CIP; 114 CPULen = CIP - CPUStart; 115 } 116 } 117 } 118 } 119 } 120 121 if (CPUStart == nullptr) 122 while (CIP < CPUInfoEnd && *CIP != '\n') 123 ++CIP; 124 } 125 126 if (CPUStart == nullptr) 127 return generic; 128 129 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 130 .Case("604e", "604e") 131 .Case("604", "604") 132 .Case("7400", "7400") 133 .Case("7410", "7400") 134 .Case("7447", "7400") 135 .Case("7455", "7450") 136 .Case("G4", "g4") 137 .Case("POWER4", "970") 138 .Case("PPC970FX", "970") 139 .Case("PPC970MP", "970") 140 .Case("G5", "g5") 141 .Case("POWER5", "g5") 142 .Case("A2", "a2") 143 .Case("POWER6", "pwr6") 144 .Case("POWER7", "pwr7") 145 .Case("POWER8", "pwr8") 146 .Case("POWER8E", "pwr8") 147 .Case("POWER8NVL", "pwr8") 148 .Case("POWER9", "pwr9") 149 .Case("POWER10", "pwr10") 150 // FIXME: If we get a simulator or machine with the capabilities of 151 // mcpu=future, we should revisit this and add the name reported by the 152 // simulator/machine. 153 .Default(generic); 154 } 155 156 StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { 157 // The cpuid register on arm is not accessible from user space. On Linux, 158 // it is exposed through the /proc/cpuinfo file. 159 160 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 161 // in all cases. 162 SmallVector<StringRef, 32> Lines; 163 ProcCpuinfoContent.split(Lines, "\n"); 164 165 // Look for the CPU implementer line. 166 StringRef Implementer; 167 StringRef Hardware; 168 StringRef Part; 169 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 170 if (Lines[I].startswith("CPU implementer")) 171 Implementer = Lines[I].substr(15).ltrim("\t :"); 172 if (Lines[I].startswith("Hardware")) 173 Hardware = Lines[I].substr(8).ltrim("\t :"); 174 if (Lines[I].startswith("CPU part")) 175 Part = Lines[I].substr(8).ltrim("\t :"); 176 } 177 178 if (Implementer == "0x41") { // ARM Ltd. 179 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 180 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 181 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 182 return "cortex-a53"; 183 184 185 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 186 // values correspond to the "Part number" in the CP15/c0 register. The 187 // contents are specified in the various processor manuals. 188 // This corresponds to the Main ID Register in Technical Reference Manuals. 189 // and is used in programs like sys-utils 190 return StringSwitch<const char *>(Part) 191 .Case("0x926", "arm926ej-s") 192 .Case("0xb02", "mpcore") 193 .Case("0xb36", "arm1136j-s") 194 .Case("0xb56", "arm1156t2-s") 195 .Case("0xb76", "arm1176jz-s") 196 .Case("0xc08", "cortex-a8") 197 .Case("0xc09", "cortex-a9") 198 .Case("0xc0f", "cortex-a15") 199 .Case("0xc20", "cortex-m0") 200 .Case("0xc23", "cortex-m3") 201 .Case("0xc24", "cortex-m4") 202 .Case("0xd22", "cortex-m55") 203 .Case("0xd02", "cortex-a34") 204 .Case("0xd04", "cortex-a35") 205 .Case("0xd03", "cortex-a53") 206 .Case("0xd07", "cortex-a57") 207 .Case("0xd08", "cortex-a72") 208 .Case("0xd09", "cortex-a73") 209 .Case("0xd0a", "cortex-a75") 210 .Case("0xd0b", "cortex-a76") 211 .Case("0xd0d", "cortex-a77") 212 .Case("0xd41", "cortex-a78") 213 .Case("0xd44", "cortex-x1") 214 .Case("0xd0c", "neoverse-n1") 215 .Case("0xd49", "neoverse-n2") 216 .Case("0xd40", "neoverse-v1") 217 .Default("generic"); 218 } 219 220 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium. 221 return StringSwitch<const char *>(Part) 222 .Case("0x516", "thunderx2t99") 223 .Case("0x0516", "thunderx2t99") 224 .Case("0xaf", "thunderx2t99") 225 .Case("0x0af", "thunderx2t99") 226 .Case("0xa1", "thunderxt88") 227 .Case("0x0a1", "thunderxt88") 228 .Default("generic"); 229 } 230 231 if (Implementer == "0x46") { // Fujitsu Ltd. 232 return StringSwitch<const char *>(Part) 233 .Case("0x001", "a64fx") 234 .Default("generic"); 235 } 236 237 if (Implementer == "0x4e") { // NVIDIA Corporation 238 return StringSwitch<const char *>(Part) 239 .Case("0x004", "carmel") 240 .Default("generic"); 241 } 242 243 if (Implementer == "0x48") // HiSilicon Technologies, Inc. 244 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 245 // values correspond to the "Part number" in the CP15/c0 register. The 246 // contents are specified in the various processor manuals. 247 return StringSwitch<const char *>(Part) 248 .Case("0xd01", "tsv110") 249 .Default("generic"); 250 251 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 252 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 253 // values correspond to the "Part number" in the CP15/c0 register. The 254 // contents are specified in the various processor manuals. 255 return StringSwitch<const char *>(Part) 256 .Case("0x06f", "krait") // APQ8064 257 .Case("0x201", "kryo") 258 .Case("0x205", "kryo") 259 .Case("0x211", "kryo") 260 .Case("0x800", "cortex-a73") // Kryo 2xx Gold 261 .Case("0x801", "cortex-a73") // Kryo 2xx Silver 262 .Case("0x802", "cortex-a75") // Kryo 3xx Gold 263 .Case("0x803", "cortex-a75") // Kryo 3xx Silver 264 .Case("0x804", "cortex-a76") // Kryo 4xx Gold 265 .Case("0x805", "cortex-a76") // Kryo 4xx/5xx Silver 266 .Case("0xc00", "falkor") 267 .Case("0xc01", "saphira") 268 .Default("generic"); 269 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. 270 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow 271 // any predictive pattern across variants and parts. 272 unsigned Variant = 0, Part = 0; 273 274 // Look for the CPU variant line, whose value is a 1 digit hexadecimal 275 // number, corresponding to the Variant bits in the CP15/C0 register. 276 for (auto I : Lines) 277 if (I.consume_front("CPU variant")) 278 I.ltrim("\t :").getAsInteger(0, Variant); 279 280 // Look for the CPU part line, whose value is a 3 digit hexadecimal 281 // number, corresponding to the PartNum bits in the CP15/C0 register. 282 for (auto I : Lines) 283 if (I.consume_front("CPU part")) 284 I.ltrim("\t :").getAsInteger(0, Part); 285 286 unsigned Exynos = (Variant << 12) | Part; 287 switch (Exynos) { 288 default: 289 // Default by falling through to Exynos M3. 290 LLVM_FALLTHROUGH; 291 case 0x1002: 292 return "exynos-m3"; 293 case 0x1003: 294 return "exynos-m4"; 295 } 296 } 297 298 return "generic"; 299 } 300 301 namespace { 302 StringRef getCPUNameFromS390Model(unsigned int Id, bool HaveVectorSupport) { 303 switch (Id) { 304 case 2064: // z900 not supported by LLVM 305 case 2066: 306 case 2084: // z990 not supported by LLVM 307 case 2086: 308 case 2094: // z9-109 not supported by LLVM 309 case 2096: 310 return "generic"; 311 case 2097: 312 case 2098: 313 return "z10"; 314 case 2817: 315 case 2818: 316 return "z196"; 317 case 2827: 318 case 2828: 319 return "zEC12"; 320 case 2964: 321 case 2965: 322 return HaveVectorSupport? "z13" : "zEC12"; 323 case 3906: 324 case 3907: 325 return HaveVectorSupport? "z14" : "zEC12"; 326 case 8561: 327 case 8562: 328 return HaveVectorSupport? "z15" : "zEC12"; 329 case 3931: 330 case 3932: 331 default: 332 return HaveVectorSupport? "arch14" : "zEC12"; 333 } 334 } 335 } // end anonymous namespace 336 337 StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { 338 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 339 340 // The "processor 0:" line comes after a fair amount of other information, 341 // including a cache breakdown, but this should be plenty. 342 SmallVector<StringRef, 32> Lines; 343 ProcCpuinfoContent.split(Lines, "\n"); 344 345 // Look for the CPU features. 346 SmallVector<StringRef, 32> CPUFeatures; 347 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 348 if (Lines[I].startswith("features")) { 349 size_t Pos = Lines[I].find(':'); 350 if (Pos != StringRef::npos) { 351 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 352 break; 353 } 354 } 355 356 // We need to check for the presence of vector support independently of 357 // the machine type, since we may only use the vector register set when 358 // supported by the kernel (and hypervisor). 359 bool HaveVectorSupport = false; 360 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 361 if (CPUFeatures[I] == "vx") 362 HaveVectorSupport = true; 363 } 364 365 // Now check the processor machine type. 366 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 367 if (Lines[I].startswith("processor ")) { 368 size_t Pos = Lines[I].find("machine = "); 369 if (Pos != StringRef::npos) { 370 Pos += sizeof("machine = ") - 1; 371 unsigned int Id; 372 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) 373 return getCPUNameFromS390Model(Id, HaveVectorSupport); 374 } 375 break; 376 } 377 } 378 379 return "generic"; 380 } 381 382 StringRef sys::detail::getHostCPUNameForBPF() { 383 #if !defined(__linux__) || !defined(__x86_64__) 384 return "generic"; 385 #else 386 uint8_t v3_insns[40] __attribute__ ((aligned (8))) = 387 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 388 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 389 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 390 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 391 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 392 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 393 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 394 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 395 /* BPF_EXIT_INSN() */ 396 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 397 398 uint8_t v2_insns[40] __attribute__ ((aligned (8))) = 399 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 400 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 401 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 402 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 403 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 404 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 405 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 406 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 407 /* BPF_EXIT_INSN() */ 408 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 409 410 struct bpf_prog_load_attr { 411 uint32_t prog_type; 412 uint32_t insn_cnt; 413 uint64_t insns; 414 uint64_t license; 415 uint32_t log_level; 416 uint32_t log_size; 417 uint64_t log_buf; 418 uint32_t kern_version; 419 uint32_t prog_flags; 420 } attr = {}; 421 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 422 attr.insn_cnt = 5; 423 attr.insns = (uint64_t)v3_insns; 424 attr.license = (uint64_t)"DUMMY"; 425 426 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, 427 sizeof(attr)); 428 if (fd >= 0) { 429 close(fd); 430 return "v3"; 431 } 432 433 /* Clear the whole attr in case its content changed by syscall. */ 434 memset(&attr, 0, sizeof(attr)); 435 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 436 attr.insn_cnt = 5; 437 attr.insns = (uint64_t)v2_insns; 438 attr.license = (uint64_t)"DUMMY"; 439 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 440 if (fd >= 0) { 441 close(fd); 442 return "v2"; 443 } 444 return "v1"; 445 #endif 446 } 447 448 #if defined(__i386__) || defined(_M_IX86) || \ 449 defined(__x86_64__) || defined(_M_X64) 450 451 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 452 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 453 // support. Consequently, for i386, the presence of CPUID is checked first 454 // via the corresponding eflags bit. 455 // Removal of cpuid.h header motivated by PR30384 456 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 457 // or test-suite, but are used in external projects e.g. libstdcxx 458 static bool isCpuIdSupported() { 459 #if defined(__GNUC__) || defined(__clang__) 460 #if defined(__i386__) 461 int __cpuid_supported; 462 __asm__(" pushfl\n" 463 " popl %%eax\n" 464 " movl %%eax,%%ecx\n" 465 " xorl $0x00200000,%%eax\n" 466 " pushl %%eax\n" 467 " popfl\n" 468 " pushfl\n" 469 " popl %%eax\n" 470 " movl $0,%0\n" 471 " cmpl %%eax,%%ecx\n" 472 " je 1f\n" 473 " movl $1,%0\n" 474 "1:" 475 : "=r"(__cpuid_supported) 476 : 477 : "eax", "ecx"); 478 if (!__cpuid_supported) 479 return false; 480 #endif 481 return true; 482 #endif 483 return true; 484 } 485 486 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 487 /// the specified arguments. If we can't run cpuid on the host, return true. 488 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 489 unsigned *rECX, unsigned *rEDX) { 490 #if defined(__GNUC__) || defined(__clang__) 491 #if defined(__x86_64__) 492 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 493 // FIXME: should we save this for Clang? 494 __asm__("movq\t%%rbx, %%rsi\n\t" 495 "cpuid\n\t" 496 "xchgq\t%%rbx, %%rsi\n\t" 497 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 498 : "a"(value)); 499 return false; 500 #elif defined(__i386__) 501 __asm__("movl\t%%ebx, %%esi\n\t" 502 "cpuid\n\t" 503 "xchgl\t%%ebx, %%esi\n\t" 504 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 505 : "a"(value)); 506 return false; 507 #else 508 return true; 509 #endif 510 #elif defined(_MSC_VER) 511 // The MSVC intrinsic is portable across x86 and x64. 512 int registers[4]; 513 __cpuid(registers, value); 514 *rEAX = registers[0]; 515 *rEBX = registers[1]; 516 *rECX = registers[2]; 517 *rEDX = registers[3]; 518 return false; 519 #else 520 return true; 521 #endif 522 } 523 524 namespace llvm { 525 namespace sys { 526 namespace detail { 527 namespace x86 { 528 529 VendorSignatures getVendorSignature(unsigned *MaxLeaf) { 530 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 531 if (MaxLeaf == nullptr) 532 MaxLeaf = &EAX; 533 else 534 *MaxLeaf = 0; 535 536 if (!isCpuIdSupported()) 537 return VendorSignatures::UNKNOWN; 538 539 if (getX86CpuIDAndInfo(0, MaxLeaf, &EBX, &ECX, &EDX) || *MaxLeaf < 1) 540 return VendorSignatures::UNKNOWN; 541 542 // "Genu ineI ntel" 543 if (EBX == 0x756e6547 && EDX == 0x49656e69 && ECX == 0x6c65746e) 544 return VendorSignatures::GENUINE_INTEL; 545 546 // "Auth enti cAMD" 547 if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163) 548 return VendorSignatures::AUTHENTIC_AMD; 549 550 return VendorSignatures::UNKNOWN; 551 } 552 553 } // namespace x86 554 } // namespace detail 555 } // namespace sys 556 } // namespace llvm 557 558 using namespace llvm::sys::detail::x86; 559 560 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 561 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 562 /// return true. 563 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 564 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 565 unsigned *rEDX) { 566 #if defined(__GNUC__) || defined(__clang__) 567 #if defined(__x86_64__) 568 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 569 // FIXME: should we save this for Clang? 570 __asm__("movq\t%%rbx, %%rsi\n\t" 571 "cpuid\n\t" 572 "xchgq\t%%rbx, %%rsi\n\t" 573 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 574 : "a"(value), "c"(subleaf)); 575 return false; 576 #elif defined(__i386__) 577 __asm__("movl\t%%ebx, %%esi\n\t" 578 "cpuid\n\t" 579 "xchgl\t%%ebx, %%esi\n\t" 580 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 581 : "a"(value), "c"(subleaf)); 582 return false; 583 #else 584 return true; 585 #endif 586 #elif defined(_MSC_VER) 587 int registers[4]; 588 __cpuidex(registers, value, subleaf); 589 *rEAX = registers[0]; 590 *rEBX = registers[1]; 591 *rECX = registers[2]; 592 *rEDX = registers[3]; 593 return false; 594 #else 595 return true; 596 #endif 597 } 598 599 // Read control register 0 (XCR0). Used to detect features such as AVX. 600 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 601 #if defined(__GNUC__) || defined(__clang__) 602 // Check xgetbv; this uses a .byte sequence instead of the instruction 603 // directly because older assemblers do not include support for xgetbv and 604 // there is no easy way to conditionally compile based on the assembler used. 605 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 606 return false; 607 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 608 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 609 *rEAX = Result; 610 *rEDX = Result >> 32; 611 return false; 612 #else 613 return true; 614 #endif 615 } 616 617 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 618 unsigned *Model) { 619 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 620 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 621 if (*Family == 6 || *Family == 0xf) { 622 if (*Family == 0xf) 623 // Examine extended family ID if family ID is F. 624 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 625 // Examine extended model ID if family ID is 6 or F. 626 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 627 } 628 } 629 630 static StringRef 631 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 632 const unsigned *Features, 633 unsigned *Type, unsigned *Subtype) { 634 auto testFeature = [&](unsigned F) { 635 return (Features[F / 32] & (1U << (F % 32))) != 0; 636 }; 637 638 StringRef CPU; 639 640 switch (Family) { 641 case 3: 642 CPU = "i386"; 643 break; 644 case 4: 645 CPU = "i486"; 646 break; 647 case 5: 648 if (testFeature(X86::FEATURE_MMX)) { 649 CPU = "pentium-mmx"; 650 break; 651 } 652 CPU = "pentium"; 653 break; 654 case 6: 655 switch (Model) { 656 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 657 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 658 // mobile processor, Intel Core 2 Extreme processor, Intel 659 // Pentium Dual-Core processor, Intel Xeon processor, model 660 // 0Fh. All processors are manufactured using the 65 nm process. 661 case 0x16: // Intel Celeron processor model 16h. All processors are 662 // manufactured using the 65 nm process 663 CPU = "core2"; 664 *Type = X86::INTEL_CORE2; 665 break; 666 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 667 // 17h. All processors are manufactured using the 45 nm process. 668 // 669 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 670 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 671 // the 45 nm process. 672 CPU = "penryn"; 673 *Type = X86::INTEL_CORE2; 674 break; 675 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 676 // processors are manufactured using the 45 nm process. 677 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 678 // As found in a Summer 2010 model iMac. 679 case 0x1f: 680 case 0x2e: // Nehalem EX 681 CPU = "nehalem"; 682 *Type = X86::INTEL_COREI7; 683 *Subtype = X86::INTEL_COREI7_NEHALEM; 684 break; 685 case 0x25: // Intel Core i7, laptop version. 686 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 687 // processors are manufactured using the 32 nm process. 688 case 0x2f: // Westmere EX 689 CPU = "westmere"; 690 *Type = X86::INTEL_COREI7; 691 *Subtype = X86::INTEL_COREI7_WESTMERE; 692 break; 693 case 0x2a: // Intel Core i7 processor. All processors are manufactured 694 // using the 32 nm process. 695 case 0x2d: 696 CPU = "sandybridge"; 697 *Type = X86::INTEL_COREI7; 698 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 699 break; 700 case 0x3a: 701 case 0x3e: // Ivy Bridge EP 702 CPU = "ivybridge"; 703 *Type = X86::INTEL_COREI7; 704 *Subtype = X86::INTEL_COREI7_IVYBRIDGE; 705 break; 706 707 // Haswell: 708 case 0x3c: 709 case 0x3f: 710 case 0x45: 711 case 0x46: 712 CPU = "haswell"; 713 *Type = X86::INTEL_COREI7; 714 *Subtype = X86::INTEL_COREI7_HASWELL; 715 break; 716 717 // Broadwell: 718 case 0x3d: 719 case 0x47: 720 case 0x4f: 721 case 0x56: 722 CPU = "broadwell"; 723 *Type = X86::INTEL_COREI7; 724 *Subtype = X86::INTEL_COREI7_BROADWELL; 725 break; 726 727 // Skylake: 728 case 0x4e: // Skylake mobile 729 case 0x5e: // Skylake desktop 730 case 0x8e: // Kaby Lake mobile 731 case 0x9e: // Kaby Lake desktop 732 case 0xa5: // Comet Lake-H/S 733 case 0xa6: // Comet Lake-U 734 CPU = "skylake"; 735 *Type = X86::INTEL_COREI7; 736 *Subtype = X86::INTEL_COREI7_SKYLAKE; 737 break; 738 739 // Rocketlake: 740 case 0xa7: 741 CPU = "rocketlake"; 742 *Type = X86::INTEL_COREI7; 743 *Subtype = X86::INTEL_COREI7_ROCKETLAKE; 744 break; 745 746 // Skylake Xeon: 747 case 0x55: 748 *Type = X86::INTEL_COREI7; 749 if (testFeature(X86::FEATURE_AVX512BF16)) { 750 CPU = "cooperlake"; 751 *Subtype = X86::INTEL_COREI7_COOPERLAKE; 752 } else if (testFeature(X86::FEATURE_AVX512VNNI)) { 753 CPU = "cascadelake"; 754 *Subtype = X86::INTEL_COREI7_CASCADELAKE; 755 } else { 756 CPU = "skylake-avx512"; 757 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; 758 } 759 break; 760 761 // Cannonlake: 762 case 0x66: 763 CPU = "cannonlake"; 764 *Type = X86::INTEL_COREI7; 765 *Subtype = X86::INTEL_COREI7_CANNONLAKE; 766 break; 767 768 // Icelake: 769 case 0x7d: 770 case 0x7e: 771 CPU = "icelake-client"; 772 *Type = X86::INTEL_COREI7; 773 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; 774 break; 775 776 // Tigerlake: 777 case 0x8c: 778 case 0x8d: 779 CPU = "tigerlake"; 780 *Type = X86::INTEL_COREI7; 781 *Subtype = X86::INTEL_COREI7_TIGERLAKE; 782 break; 783 784 // Alderlake: 785 case 0x97: 786 case 0x9a: 787 CPU = "alderlake"; 788 *Type = X86::INTEL_COREI7; 789 *Subtype = X86::INTEL_COREI7_ALDERLAKE; 790 break; 791 792 // Icelake Xeon: 793 case 0x6a: 794 case 0x6c: 795 CPU = "icelake-server"; 796 *Type = X86::INTEL_COREI7; 797 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; 798 break; 799 800 // Sapphire Rapids: 801 case 0x8f: 802 CPU = "sapphirerapids"; 803 *Type = X86::INTEL_COREI7; 804 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS; 805 break; 806 807 case 0x1c: // Most 45 nm Intel Atom processors 808 case 0x26: // 45 nm Atom Lincroft 809 case 0x27: // 32 nm Atom Medfield 810 case 0x35: // 32 nm Atom Midview 811 case 0x36: // 32 nm Atom Midview 812 CPU = "bonnell"; 813 *Type = X86::INTEL_BONNELL; 814 break; 815 816 // Atom Silvermont codes from the Intel software optimization guide. 817 case 0x37: 818 case 0x4a: 819 case 0x4d: 820 case 0x5a: 821 case 0x5d: 822 case 0x4c: // really airmont 823 CPU = "silvermont"; 824 *Type = X86::INTEL_SILVERMONT; 825 break; 826 // Goldmont: 827 case 0x5c: // Apollo Lake 828 case 0x5f: // Denverton 829 CPU = "goldmont"; 830 *Type = X86::INTEL_GOLDMONT; 831 break; 832 case 0x7a: 833 CPU = "goldmont-plus"; 834 *Type = X86::INTEL_GOLDMONT_PLUS; 835 break; 836 case 0x86: 837 CPU = "tremont"; 838 *Type = X86::INTEL_TREMONT; 839 break; 840 841 // Xeon Phi (Knights Landing + Knights Mill): 842 case 0x57: 843 CPU = "knl"; 844 *Type = X86::INTEL_KNL; 845 break; 846 case 0x85: 847 CPU = "knm"; 848 *Type = X86::INTEL_KNM; 849 break; 850 851 default: // Unknown family 6 CPU, try to guess. 852 // Don't both with Type/Subtype here, they aren't used by the caller. 853 // They're used above to keep the code in sync with compiler-rt. 854 // TODO detect tigerlake host from model 855 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) { 856 CPU = "tigerlake"; 857 } else if (testFeature(X86::FEATURE_AVX512VBMI2)) { 858 CPU = "icelake-client"; 859 } else if (testFeature(X86::FEATURE_AVX512VBMI)) { 860 CPU = "cannonlake"; 861 } else if (testFeature(X86::FEATURE_AVX512BF16)) { 862 CPU = "cooperlake"; 863 } else if (testFeature(X86::FEATURE_AVX512VNNI)) { 864 CPU = "cascadelake"; 865 } else if (testFeature(X86::FEATURE_AVX512VL)) { 866 CPU = "skylake-avx512"; 867 } else if (testFeature(X86::FEATURE_AVX512ER)) { 868 CPU = "knl"; 869 } else if (testFeature(X86::FEATURE_CLFLUSHOPT)) { 870 if (testFeature(X86::FEATURE_SHA)) 871 CPU = "goldmont"; 872 else 873 CPU = "skylake"; 874 } else if (testFeature(X86::FEATURE_ADX)) { 875 CPU = "broadwell"; 876 } else if (testFeature(X86::FEATURE_AVX2)) { 877 CPU = "haswell"; 878 } else if (testFeature(X86::FEATURE_AVX)) { 879 CPU = "sandybridge"; 880 } else if (testFeature(X86::FEATURE_SSE4_2)) { 881 if (testFeature(X86::FEATURE_MOVBE)) 882 CPU = "silvermont"; 883 else 884 CPU = "nehalem"; 885 } else if (testFeature(X86::FEATURE_SSE4_1)) { 886 CPU = "penryn"; 887 } else if (testFeature(X86::FEATURE_SSSE3)) { 888 if (testFeature(X86::FEATURE_MOVBE)) 889 CPU = "bonnell"; 890 else 891 CPU = "core2"; 892 } else if (testFeature(X86::FEATURE_64BIT)) { 893 CPU = "core2"; 894 } else if (testFeature(X86::FEATURE_SSE3)) { 895 CPU = "yonah"; 896 } else if (testFeature(X86::FEATURE_SSE2)) { 897 CPU = "pentium-m"; 898 } else if (testFeature(X86::FEATURE_SSE)) { 899 CPU = "pentium3"; 900 } else if (testFeature(X86::FEATURE_MMX)) { 901 CPU = "pentium2"; 902 } else { 903 CPU = "pentiumpro"; 904 } 905 break; 906 } 907 break; 908 case 15: { 909 if (testFeature(X86::FEATURE_64BIT)) { 910 CPU = "nocona"; 911 break; 912 } 913 if (testFeature(X86::FEATURE_SSE3)) { 914 CPU = "prescott"; 915 break; 916 } 917 CPU = "pentium4"; 918 break; 919 } 920 default: 921 break; // Unknown. 922 } 923 924 return CPU; 925 } 926 927 static StringRef 928 getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 929 const unsigned *Features, 930 unsigned *Type, unsigned *Subtype) { 931 auto testFeature = [&](unsigned F) { 932 return (Features[F / 32] & (1U << (F % 32))) != 0; 933 }; 934 935 StringRef CPU; 936 937 switch (Family) { 938 case 4: 939 CPU = "i486"; 940 break; 941 case 5: 942 CPU = "pentium"; 943 switch (Model) { 944 case 6: 945 case 7: 946 CPU = "k6"; 947 break; 948 case 8: 949 CPU = "k6-2"; 950 break; 951 case 9: 952 case 13: 953 CPU = "k6-3"; 954 break; 955 case 10: 956 CPU = "geode"; 957 break; 958 } 959 break; 960 case 6: 961 if (testFeature(X86::FEATURE_SSE)) { 962 CPU = "athlon-xp"; 963 break; 964 } 965 CPU = "athlon"; 966 break; 967 case 15: 968 if (testFeature(X86::FEATURE_SSE3)) { 969 CPU = "k8-sse3"; 970 break; 971 } 972 CPU = "k8"; 973 break; 974 case 16: 975 CPU = "amdfam10"; 976 *Type = X86::AMDFAM10H; // "amdfam10" 977 switch (Model) { 978 case 2: 979 *Subtype = X86::AMDFAM10H_BARCELONA; 980 break; 981 case 4: 982 *Subtype = X86::AMDFAM10H_SHANGHAI; 983 break; 984 case 8: 985 *Subtype = X86::AMDFAM10H_ISTANBUL; 986 break; 987 } 988 break; 989 case 20: 990 CPU = "btver1"; 991 *Type = X86::AMD_BTVER1; 992 break; 993 case 21: 994 CPU = "bdver1"; 995 *Type = X86::AMDFAM15H; 996 if (Model >= 0x60 && Model <= 0x7f) { 997 CPU = "bdver4"; 998 *Subtype = X86::AMDFAM15H_BDVER4; 999 break; // 60h-7Fh: Excavator 1000 } 1001 if (Model >= 0x30 && Model <= 0x3f) { 1002 CPU = "bdver3"; 1003 *Subtype = X86::AMDFAM15H_BDVER3; 1004 break; // 30h-3Fh: Steamroller 1005 } 1006 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) { 1007 CPU = "bdver2"; 1008 *Subtype = X86::AMDFAM15H_BDVER2; 1009 break; // 02h, 10h-1Fh: Piledriver 1010 } 1011 if (Model <= 0x0f) { 1012 *Subtype = X86::AMDFAM15H_BDVER1; 1013 break; // 00h-0Fh: Bulldozer 1014 } 1015 break; 1016 case 22: 1017 CPU = "btver2"; 1018 *Type = X86::AMD_BTVER2; 1019 break; 1020 case 23: 1021 CPU = "znver1"; 1022 *Type = X86::AMDFAM17H; 1023 if ((Model >= 0x30 && Model <= 0x3f) || Model == 0x71) { 1024 CPU = "znver2"; 1025 *Subtype = X86::AMDFAM17H_ZNVER2; 1026 break; // 30h-3fh, 71h: Zen2 1027 } 1028 if (Model <= 0x0f) { 1029 *Subtype = X86::AMDFAM17H_ZNVER1; 1030 break; // 00h-0Fh: Zen1 1031 } 1032 break; 1033 case 25: 1034 CPU = "znver3"; 1035 *Type = X86::AMDFAM19H; 1036 if (Model <= 0x0f) { 1037 *Subtype = X86::AMDFAM19H_ZNVER3; 1038 break; // 00h-0Fh: Zen3 1039 } 1040 break; 1041 default: 1042 break; // Unknown AMD CPU. 1043 } 1044 1045 return CPU; 1046 } 1047 1048 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 1049 unsigned *Features) { 1050 unsigned EAX, EBX; 1051 1052 auto setFeature = [&](unsigned F) { 1053 Features[F / 32] |= 1U << (F % 32); 1054 }; 1055 1056 if ((EDX >> 15) & 1) 1057 setFeature(X86::FEATURE_CMOV); 1058 if ((EDX >> 23) & 1) 1059 setFeature(X86::FEATURE_MMX); 1060 if ((EDX >> 25) & 1) 1061 setFeature(X86::FEATURE_SSE); 1062 if ((EDX >> 26) & 1) 1063 setFeature(X86::FEATURE_SSE2); 1064 1065 if ((ECX >> 0) & 1) 1066 setFeature(X86::FEATURE_SSE3); 1067 if ((ECX >> 1) & 1) 1068 setFeature(X86::FEATURE_PCLMUL); 1069 if ((ECX >> 9) & 1) 1070 setFeature(X86::FEATURE_SSSE3); 1071 if ((ECX >> 12) & 1) 1072 setFeature(X86::FEATURE_FMA); 1073 if ((ECX >> 19) & 1) 1074 setFeature(X86::FEATURE_SSE4_1); 1075 if ((ECX >> 20) & 1) { 1076 setFeature(X86::FEATURE_SSE4_2); 1077 setFeature(X86::FEATURE_CRC32); 1078 } 1079 if ((ECX >> 23) & 1) 1080 setFeature(X86::FEATURE_POPCNT); 1081 if ((ECX >> 25) & 1) 1082 setFeature(X86::FEATURE_AES); 1083 1084 if ((ECX >> 22) & 1) 1085 setFeature(X86::FEATURE_MOVBE); 1086 1087 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1088 // indicates that the AVX registers will be saved and restored on context 1089 // switch, then we have full AVX support. 1090 const unsigned AVXBits = (1 << 27) | (1 << 28); 1091 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 1092 ((EAX & 0x6) == 0x6); 1093 #if defined(__APPLE__) 1094 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1095 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1096 // set right now. 1097 bool HasAVX512Save = true; 1098 #else 1099 // AVX512 requires additional context to be saved by the OS. 1100 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 1101 #endif 1102 1103 if (HasAVX) 1104 setFeature(X86::FEATURE_AVX); 1105 1106 bool HasLeaf7 = 1107 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1108 1109 if (HasLeaf7 && ((EBX >> 3) & 1)) 1110 setFeature(X86::FEATURE_BMI); 1111 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 1112 setFeature(X86::FEATURE_AVX2); 1113 if (HasLeaf7 && ((EBX >> 8) & 1)) 1114 setFeature(X86::FEATURE_BMI2); 1115 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 1116 setFeature(X86::FEATURE_AVX512F); 1117 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 1118 setFeature(X86::FEATURE_AVX512DQ); 1119 if (HasLeaf7 && ((EBX >> 19) & 1)) 1120 setFeature(X86::FEATURE_ADX); 1121 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 1122 setFeature(X86::FEATURE_AVX512IFMA); 1123 if (HasLeaf7 && ((EBX >> 23) & 1)) 1124 setFeature(X86::FEATURE_CLFLUSHOPT); 1125 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 1126 setFeature(X86::FEATURE_AVX512PF); 1127 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 1128 setFeature(X86::FEATURE_AVX512ER); 1129 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 1130 setFeature(X86::FEATURE_AVX512CD); 1131 if (HasLeaf7 && ((EBX >> 29) & 1)) 1132 setFeature(X86::FEATURE_SHA); 1133 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 1134 setFeature(X86::FEATURE_AVX512BW); 1135 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 1136 setFeature(X86::FEATURE_AVX512VL); 1137 1138 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 1139 setFeature(X86::FEATURE_AVX512VBMI); 1140 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save) 1141 setFeature(X86::FEATURE_AVX512VBMI2); 1142 if (HasLeaf7 && ((ECX >> 8) & 1)) 1143 setFeature(X86::FEATURE_GFNI); 1144 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX) 1145 setFeature(X86::FEATURE_VPCLMULQDQ); 1146 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save) 1147 setFeature(X86::FEATURE_AVX512VNNI); 1148 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save) 1149 setFeature(X86::FEATURE_AVX512BITALG); 1150 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1151 setFeature(X86::FEATURE_AVX512VPOPCNTDQ); 1152 1153 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1154 setFeature(X86::FEATURE_AVX5124VNNIW); 1155 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1156 setFeature(X86::FEATURE_AVX5124FMAPS); 1157 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save) 1158 setFeature(X86::FEATURE_AVX512VP2INTERSECT); 1159 1160 bool HasLeaf7Subleaf1 = 1161 MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1162 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save) 1163 setFeature(X86::FEATURE_AVX512BF16); 1164 1165 unsigned MaxExtLevel; 1166 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1167 1168 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1169 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1170 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1171 setFeature(X86::FEATURE_SSE4_A); 1172 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1173 setFeature(X86::FEATURE_XOP); 1174 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1175 setFeature(X86::FEATURE_FMA4); 1176 1177 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1178 setFeature(X86::FEATURE_64BIT); 1179 } 1180 1181 StringRef sys::getHostCPUName() { 1182 unsigned MaxLeaf = 0; 1183 const VendorSignatures Vendor = getVendorSignature(&MaxLeaf); 1184 if (Vendor == VendorSignatures::UNKNOWN) 1185 return "generic"; 1186 1187 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1188 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1189 1190 unsigned Family = 0, Model = 0; 1191 unsigned Features[(X86::CPU_FEATURE_MAX + 31) / 32] = {0}; 1192 detectX86FamilyModel(EAX, &Family, &Model); 1193 getAvailableFeatures(ECX, EDX, MaxLeaf, Features); 1194 1195 // These aren't consumed in this file, but we try to keep some source code the 1196 // same or similar to compiler-rt. 1197 unsigned Type = 0; 1198 unsigned Subtype = 0; 1199 1200 StringRef CPU; 1201 1202 if (Vendor == VendorSignatures::GENUINE_INTEL) { 1203 CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &Type, 1204 &Subtype); 1205 } else if (Vendor == VendorSignatures::AUTHENTIC_AMD) { 1206 CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, 1207 &Subtype); 1208 } 1209 1210 if (!CPU.empty()) 1211 return CPU; 1212 1213 return "generic"; 1214 } 1215 1216 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1217 StringRef sys::getHostCPUName() { 1218 host_basic_info_data_t hostInfo; 1219 mach_msg_type_number_t infoCount; 1220 1221 infoCount = HOST_BASIC_INFO_COUNT; 1222 mach_port_t hostPort = mach_host_self(); 1223 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1224 &infoCount); 1225 mach_port_deallocate(mach_task_self(), hostPort); 1226 1227 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1228 return "generic"; 1229 1230 switch (hostInfo.cpu_subtype) { 1231 case CPU_SUBTYPE_POWERPC_601: 1232 return "601"; 1233 case CPU_SUBTYPE_POWERPC_602: 1234 return "602"; 1235 case CPU_SUBTYPE_POWERPC_603: 1236 return "603"; 1237 case CPU_SUBTYPE_POWERPC_603e: 1238 return "603e"; 1239 case CPU_SUBTYPE_POWERPC_603ev: 1240 return "603ev"; 1241 case CPU_SUBTYPE_POWERPC_604: 1242 return "604"; 1243 case CPU_SUBTYPE_POWERPC_604e: 1244 return "604e"; 1245 case CPU_SUBTYPE_POWERPC_620: 1246 return "620"; 1247 case CPU_SUBTYPE_POWERPC_750: 1248 return "750"; 1249 case CPU_SUBTYPE_POWERPC_7400: 1250 return "7400"; 1251 case CPU_SUBTYPE_POWERPC_7450: 1252 return "7450"; 1253 case CPU_SUBTYPE_POWERPC_970: 1254 return "970"; 1255 default:; 1256 } 1257 1258 return "generic"; 1259 } 1260 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1261 StringRef sys::getHostCPUName() { 1262 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1263 StringRef Content = P ? P->getBuffer() : ""; 1264 return detail::getHostCPUNameForPowerPC(Content); 1265 } 1266 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1267 StringRef sys::getHostCPUName() { 1268 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1269 StringRef Content = P ? P->getBuffer() : ""; 1270 return detail::getHostCPUNameForARM(Content); 1271 } 1272 #elif defined(__linux__) && defined(__s390x__) 1273 StringRef sys::getHostCPUName() { 1274 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1275 StringRef Content = P ? P->getBuffer() : ""; 1276 return detail::getHostCPUNameForS390x(Content); 1277 } 1278 #elif defined(__MVS__) 1279 StringRef sys::getHostCPUName() { 1280 // Get pointer to Communications Vector Table (CVT). 1281 // The pointer is located at offset 16 of the Prefixed Save Area (PSA). 1282 // It is stored as 31 bit pointer and will be zero-extended to 64 bit. 1283 int *StartToCVTOffset = reinterpret_cast<int *>(0x10); 1284 // Since its stored as a 31-bit pointer, get the 4 bytes from the start 1285 // of address. 1286 int ReadValue = *StartToCVTOffset; 1287 // Explicitly clear the high order bit. 1288 ReadValue = (ReadValue & 0x7FFFFFFF); 1289 char *CVT = reinterpret_cast<char *>(ReadValue); 1290 // The model number is located in the CVT prefix at offset -6 and stored as 1291 // signless packed decimal. 1292 uint16_t Id = *(uint16_t *)&CVT[-6]; 1293 // Convert number to integer. 1294 Id = decodePackedBCD<uint16_t>(Id, false); 1295 // Check for vector support. It's stored in field CVTFLAG5 (offset 244), 1296 // bit CVTVEF (X'80'). The facilities list is part of the PSA but the vector 1297 // extension can only be used if bit CVTVEF is on. 1298 bool HaveVectorSupport = CVT[244] & 0x80; 1299 return getCPUNameFromS390Model(Id, HaveVectorSupport); 1300 } 1301 #elif defined(__APPLE__) && defined(__aarch64__) 1302 StringRef sys::getHostCPUName() { 1303 return "cyclone"; 1304 } 1305 #elif defined(__APPLE__) && defined(__arm__) 1306 StringRef sys::getHostCPUName() { 1307 host_basic_info_data_t hostInfo; 1308 mach_msg_type_number_t infoCount; 1309 1310 infoCount = HOST_BASIC_INFO_COUNT; 1311 mach_port_t hostPort = mach_host_self(); 1312 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1313 &infoCount); 1314 mach_port_deallocate(mach_task_self(), hostPort); 1315 1316 if (hostInfo.cpu_type != CPU_TYPE_ARM) { 1317 assert(false && "CPUType not equal to ARM should not be possible on ARM"); 1318 return "generic"; 1319 } 1320 switch (hostInfo.cpu_subtype) { 1321 case CPU_SUBTYPE_ARM_V7S: 1322 return "swift"; 1323 default:; 1324 } 1325 1326 return "generic"; 1327 } 1328 #elif defined(_AIX) 1329 StringRef sys::getHostCPUName() { 1330 switch (_system_configuration.implementation) { 1331 case POWER_4: 1332 if (_system_configuration.version == PV_4_3) 1333 return "970"; 1334 return "pwr4"; 1335 case POWER_5: 1336 if (_system_configuration.version == PV_5) 1337 return "pwr5"; 1338 return "pwr5x"; 1339 case POWER_6: 1340 if (_system_configuration.version == PV_6_Compat) 1341 return "pwr6"; 1342 return "pwr6x"; 1343 case POWER_7: 1344 return "pwr7"; 1345 case POWER_8: 1346 return "pwr8"; 1347 case POWER_9: 1348 return "pwr9"; 1349 // TODO: simplify this once the macro is available in all OS levels. 1350 #ifdef POWER_10 1351 case POWER_10: 1352 #else 1353 case 0x40000: 1354 #endif 1355 return "pwr10"; 1356 default: 1357 return "generic"; 1358 } 1359 } 1360 #elif defined(__riscv) 1361 StringRef sys::getHostCPUName() { 1362 #if __riscv_xlen == 64 1363 return "generic-rv64"; 1364 #elif __riscv_xlen == 32 1365 return "generic-rv32"; 1366 #else 1367 #error "Unhandled value of __riscv_xlen" 1368 #endif 1369 } 1370 #else 1371 StringRef sys::getHostCPUName() { return "generic"; } 1372 namespace llvm { 1373 namespace sys { 1374 namespace detail { 1375 namespace x86 { 1376 1377 VendorSignatures getVendorSignature(unsigned *MaxLeaf) { 1378 return VendorSignatures::UNKNOWN; 1379 } 1380 1381 } // namespace x86 1382 } // namespace detail 1383 } // namespace sys 1384 } // namespace llvm 1385 #endif 1386 1387 #if defined(__linux__) && (defined(__i386__) || defined(__x86_64__)) 1388 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1389 // using the number of unique physical/core id pairs. The following 1390 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1391 int computeHostNumPhysicalCores() { 1392 // Enabled represents the number of physical id/core id pairs with at least 1393 // one processor id enabled by the CPU affinity mask. 1394 cpu_set_t Affinity, Enabled; 1395 if (sched_getaffinity(0, sizeof(Affinity), &Affinity) != 0) 1396 return -1; 1397 CPU_ZERO(&Enabled); 1398 1399 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1400 // mmapped because it appears to have 0 size. 1401 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1402 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1403 if (std::error_code EC = Text.getError()) { 1404 llvm::errs() << "Can't read " 1405 << "/proc/cpuinfo: " << EC.message() << "\n"; 1406 return -1; 1407 } 1408 SmallVector<StringRef, 8> strs; 1409 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1410 /*KeepEmpty=*/false); 1411 int CurProcessor = -1; 1412 int CurPhysicalId = -1; 1413 int CurSiblings = -1; 1414 int CurCoreId = -1; 1415 for (StringRef Line : strs) { 1416 std::pair<StringRef, StringRef> Data = Line.split(':'); 1417 auto Name = Data.first.trim(); 1418 auto Val = Data.second.trim(); 1419 // These fields are available if the kernel is configured with CONFIG_SMP. 1420 if (Name == "processor") 1421 Val.getAsInteger(10, CurProcessor); 1422 else if (Name == "physical id") 1423 Val.getAsInteger(10, CurPhysicalId); 1424 else if (Name == "siblings") 1425 Val.getAsInteger(10, CurSiblings); 1426 else if (Name == "core id") { 1427 Val.getAsInteger(10, CurCoreId); 1428 // The processor id corresponds to an index into cpu_set_t. 1429 if (CPU_ISSET(CurProcessor, &Affinity)) 1430 CPU_SET(CurPhysicalId * CurSiblings + CurCoreId, &Enabled); 1431 } 1432 } 1433 return CPU_COUNT(&Enabled); 1434 } 1435 #elif defined(__linux__) && defined(__powerpc__) 1436 int computeHostNumPhysicalCores() { 1437 cpu_set_t Affinity; 1438 if (sched_getaffinity(0, sizeof(Affinity), &Affinity) == 0) 1439 return CPU_COUNT(&Affinity); 1440 1441 // The call to sched_getaffinity() may have failed because the Affinity 1442 // mask is too small for the number of CPU's on the system (i.e. the 1443 // system has more than 1024 CPUs). Allocate a mask large enough for 1444 // twice as many CPUs. 1445 cpu_set_t *DynAffinity; 1446 DynAffinity = CPU_ALLOC(2048); 1447 if (sched_getaffinity(0, CPU_ALLOC_SIZE(2048), DynAffinity) == 0) { 1448 int NumCPUs = CPU_COUNT(DynAffinity); 1449 CPU_FREE(DynAffinity); 1450 return NumCPUs; 1451 } 1452 return -1; 1453 } 1454 #elif defined(__linux__) && defined(__s390x__) 1455 int computeHostNumPhysicalCores() { return sysconf(_SC_NPROCESSORS_ONLN); } 1456 #elif defined(__APPLE__) 1457 #include <sys/param.h> 1458 #include <sys/sysctl.h> 1459 1460 // Gets the number of *physical cores* on the machine. 1461 int computeHostNumPhysicalCores() { 1462 uint32_t count; 1463 size_t len = sizeof(count); 1464 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1465 if (count < 1) { 1466 int nm[2]; 1467 nm[0] = CTL_HW; 1468 nm[1] = HW_AVAILCPU; 1469 sysctl(nm, 2, &count, &len, NULL, 0); 1470 if (count < 1) 1471 return -1; 1472 } 1473 return count; 1474 } 1475 #elif defined(__MVS__) 1476 int computeHostNumPhysicalCores() { 1477 enum { 1478 // Byte offset of the pointer to the Communications Vector Table (CVT) in 1479 // the Prefixed Save Area (PSA). The table entry is a 31-bit pointer and 1480 // will be zero-extended to uintptr_t. 1481 FLCCVT = 16, 1482 // Byte offset of the pointer to the Common System Data Area (CSD) in the 1483 // CVT. The table entry is a 31-bit pointer and will be zero-extended to 1484 // uintptr_t. 1485 CVTCSD = 660, 1486 // Byte offset to the number of live CPs in the LPAR, stored as a signed 1487 // 32-bit value in the table. 1488 CSD_NUMBER_ONLINE_STANDARD_CPS = 264, 1489 }; 1490 char *PSA = 0; 1491 char *CVT = reinterpret_cast<char *>( 1492 static_cast<uintptr_t>(reinterpret_cast<unsigned int &>(PSA[FLCCVT]))); 1493 char *CSD = reinterpret_cast<char *>( 1494 static_cast<uintptr_t>(reinterpret_cast<unsigned int &>(CVT[CVTCSD]))); 1495 return reinterpret_cast<int &>(CSD[CSD_NUMBER_ONLINE_STANDARD_CPS]); 1496 } 1497 #elif defined(_WIN32) && LLVM_ENABLE_THREADS != 0 1498 // Defined in llvm/lib/Support/Windows/Threading.inc 1499 int computeHostNumPhysicalCores(); 1500 #else 1501 // On other systems, return -1 to indicate unknown. 1502 static int computeHostNumPhysicalCores() { return -1; } 1503 #endif 1504 1505 int sys::getHostNumPhysicalCores() { 1506 static int NumCores = computeHostNumPhysicalCores(); 1507 return NumCores; 1508 } 1509 1510 #if defined(__i386__) || defined(_M_IX86) || \ 1511 defined(__x86_64__) || defined(_M_X64) 1512 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1513 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1514 unsigned MaxLevel; 1515 1516 if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1) 1517 return false; 1518 1519 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1520 1521 Features["cx8"] = (EDX >> 8) & 1; 1522 Features["cmov"] = (EDX >> 15) & 1; 1523 Features["mmx"] = (EDX >> 23) & 1; 1524 Features["fxsr"] = (EDX >> 24) & 1; 1525 Features["sse"] = (EDX >> 25) & 1; 1526 Features["sse2"] = (EDX >> 26) & 1; 1527 1528 Features["sse3"] = (ECX >> 0) & 1; 1529 Features["pclmul"] = (ECX >> 1) & 1; 1530 Features["ssse3"] = (ECX >> 9) & 1; 1531 Features["cx16"] = (ECX >> 13) & 1; 1532 Features["sse4.1"] = (ECX >> 19) & 1; 1533 Features["sse4.2"] = (ECX >> 20) & 1; 1534 Features["crc32"] = Features["sse4.2"]; 1535 Features["movbe"] = (ECX >> 22) & 1; 1536 Features["popcnt"] = (ECX >> 23) & 1; 1537 Features["aes"] = (ECX >> 25) & 1; 1538 Features["rdrnd"] = (ECX >> 30) & 1; 1539 1540 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1541 // indicates that the AVX registers will be saved and restored on context 1542 // switch, then we have full AVX support. 1543 bool HasXSave = ((ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX); 1544 bool HasAVXSave = HasXSave && ((ECX >> 28) & 1) && ((EAX & 0x6) == 0x6); 1545 #if defined(__APPLE__) 1546 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1547 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1548 // set right now. 1549 bool HasAVX512Save = true; 1550 #else 1551 // AVX512 requires additional context to be saved by the OS. 1552 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1553 #endif 1554 // AMX requires additional context to be saved by the OS. 1555 const unsigned AMXBits = (1 << 17) | (1 << 18); 1556 bool HasAMXSave = HasXSave && ((EAX & AMXBits) == AMXBits); 1557 1558 Features["avx"] = HasAVXSave; 1559 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave; 1560 // Only enable XSAVE if OS has enabled support for saving YMM state. 1561 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave; 1562 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave; 1563 1564 unsigned MaxExtLevel; 1565 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1566 1567 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1568 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1569 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1); 1570 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1571 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1572 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1573 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1574 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1575 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1576 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1577 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1578 1579 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1); 1580 1581 // Miscellaneous memory related features, detected by 1582 // using the 0x80000008 leaf of the CPUID instruction 1583 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1584 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX); 1585 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1586 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1); 1587 1588 bool HasLeaf7 = 1589 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1590 1591 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1592 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1593 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1594 // AVX2 is only supported if we have the OS save support from AVX. 1595 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave; 1596 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1597 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1598 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1599 // AVX512 is only supported if the OS supports the context save for it. 1600 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1601 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1602 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1603 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1604 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1605 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1606 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1607 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1608 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1609 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1610 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1611 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1612 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1613 1614 Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1); 1615 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1616 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1617 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1); 1618 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save; 1619 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1); 1620 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1); 1621 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave; 1622 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave; 1623 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save; 1624 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save; 1625 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1626 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1); 1627 Features["kl"] = HasLeaf7 && ((ECX >> 23) & 1); // key locker 1628 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1); 1629 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1); 1630 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1); 1631 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1); 1632 1633 Features["uintr"] = HasLeaf7 && ((EDX >> 5) & 1); 1634 Features["avx512vp2intersect"] = 1635 HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save; 1636 Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1); 1637 Features["tsxldtrk"] = HasLeaf7 && ((EDX >> 16) & 1); 1638 // There are two CPUID leafs which information associated with the pconfig 1639 // instruction: 1640 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th 1641 // bit of EDX), while the EAX=0x1b leaf returns information on the 1642 // availability of specific pconfig leafs. 1643 // The target feature here only refers to the the first of these two. 1644 // Users might need to check for the availability of specific pconfig 1645 // leaves using cpuid, since that information is ignored while 1646 // detecting features using the "-march=native" flag. 1647 // For more info, see X86 ISA docs. 1648 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1); 1649 Features["amx-bf16"] = HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave; 1650 Features["avx512fp16"] = HasLeaf7 && ((EDX >> 23) & 1) && HasAVX512Save; 1651 Features["amx-tile"] = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave; 1652 Features["amx-int8"] = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave; 1653 bool HasLeaf7Subleaf1 = 1654 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1655 Features["avxvnni"] = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave; 1656 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save; 1657 Features["hreset"] = HasLeaf7Subleaf1 && ((EAX >> 22) & 1); 1658 1659 bool HasLeafD = MaxLevel >= 0xd && 1660 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1661 1662 // Only enable XSAVE if OS has enabled support for saving YMM state. 1663 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave; 1664 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave; 1665 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave; 1666 1667 bool HasLeaf14 = MaxLevel >= 0x14 && 1668 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX); 1669 1670 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1); 1671 1672 bool HasLeaf19 = 1673 MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX); 1674 Features["widekl"] = HasLeaf7 && HasLeaf19 && ((EBX >> 2) & 1); 1675 1676 return true; 1677 } 1678 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1679 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1680 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1681 if (!P) 1682 return false; 1683 1684 SmallVector<StringRef, 32> Lines; 1685 P->getBuffer().split(Lines, "\n"); 1686 1687 SmallVector<StringRef, 32> CPUFeatures; 1688 1689 // Look for the CPU features. 1690 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1691 if (Lines[I].startswith("Features")) { 1692 Lines[I].split(CPUFeatures, ' '); 1693 break; 1694 } 1695 1696 #if defined(__aarch64__) 1697 // Keep track of which crypto features we have seen 1698 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1699 uint32_t crypto = 0; 1700 #endif 1701 1702 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1703 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1704 #if defined(__aarch64__) 1705 .Case("asimd", "neon") 1706 .Case("fp", "fp-armv8") 1707 .Case("crc32", "crc") 1708 #else 1709 .Case("half", "fp16") 1710 .Case("neon", "neon") 1711 .Case("vfpv3", "vfp3") 1712 .Case("vfpv3d16", "d16") 1713 .Case("vfpv4", "vfp4") 1714 .Case("idiva", "hwdiv-arm") 1715 .Case("idivt", "hwdiv") 1716 #endif 1717 .Default(""); 1718 1719 #if defined(__aarch64__) 1720 // We need to check crypto separately since we need all of the crypto 1721 // extensions to enable the subtarget feature 1722 if (CPUFeatures[I] == "aes") 1723 crypto |= CAP_AES; 1724 else if (CPUFeatures[I] == "pmull") 1725 crypto |= CAP_PMULL; 1726 else if (CPUFeatures[I] == "sha1") 1727 crypto |= CAP_SHA1; 1728 else if (CPUFeatures[I] == "sha2") 1729 crypto |= CAP_SHA2; 1730 #endif 1731 1732 if (LLVMFeatureStr != "") 1733 Features[LLVMFeatureStr] = true; 1734 } 1735 1736 #if defined(__aarch64__) 1737 // If we have all crypto bits we can add the feature 1738 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1739 Features["crypto"] = true; 1740 #endif 1741 1742 return true; 1743 } 1744 #elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64)) 1745 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1746 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE)) 1747 Features["neon"] = true; 1748 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE)) 1749 Features["crc"] = true; 1750 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) 1751 Features["crypto"] = true; 1752 1753 return true; 1754 } 1755 #else 1756 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1757 #endif 1758 1759 std::string sys::getProcessTriple() { 1760 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1761 Triple PT(Triple::normalize(TargetTripleString)); 1762 1763 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1764 PT = PT.get64BitArchVariant(); 1765 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1766 PT = PT.get32BitArchVariant(); 1767 1768 return PT.str(); 1769 } 1770