1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the operating system Host concept. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Support/Host.h" 15 #include "llvm/ADT/SmallSet.h" 16 #include "llvm/ADT/SmallVector.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include <assert.h> 26 #include <string.h> 27 28 // Include the platform-specific parts of this class. 29 #ifdef LLVM_ON_UNIX 30 #include "Unix/Host.inc" 31 #endif 32 #ifdef LLVM_ON_WIN32 33 #include "Windows/Host.inc" 34 #endif 35 #ifdef _MSC_VER 36 #include <intrin.h> 37 #endif 38 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 39 #include <mach/host_info.h> 40 #include <mach/mach.h> 41 #include <mach/mach_host.h> 42 #include <mach/machine.h> 43 #endif 44 45 #define DEBUG_TYPE "host-detection" 46 47 //===----------------------------------------------------------------------===// 48 // 49 // Implementations of the CPU detection routines 50 // 51 //===----------------------------------------------------------------------===// 52 53 using namespace llvm; 54 55 static std::unique_ptr<llvm::MemoryBuffer> 56 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 57 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 58 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 59 if (std::error_code EC = Text.getError()) { 60 llvm::errs() << "Can't read " 61 << "/proc/cpuinfo: " << EC.message() << "\n"; 62 return nullptr; 63 } 64 return std::move(*Text); 65 } 66 67 StringRef sys::detail::getHostCPUNameForPowerPC( 68 const StringRef &ProcCpuinfoContent) { 69 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 70 // and so we must use an operating-system interface to determine the current 71 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 72 const char *generic = "generic"; 73 74 // The cpu line is second (after the 'processor: 0' line), so if this 75 // buffer is too small then something has changed (or is wrong). 76 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 77 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 78 79 StringRef::const_iterator CIP = CPUInfoStart; 80 81 StringRef::const_iterator CPUStart = 0; 82 size_t CPULen = 0; 83 84 // We need to find the first line which starts with cpu, spaces, and a colon. 85 // After the colon, there may be some additional spaces and then the cpu type. 86 while (CIP < CPUInfoEnd && CPUStart == 0) { 87 if (CIP < CPUInfoEnd && *CIP == '\n') 88 ++CIP; 89 90 if (CIP < CPUInfoEnd && *CIP == 'c') { 91 ++CIP; 92 if (CIP < CPUInfoEnd && *CIP == 'p') { 93 ++CIP; 94 if (CIP < CPUInfoEnd && *CIP == 'u') { 95 ++CIP; 96 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 97 ++CIP; 98 99 if (CIP < CPUInfoEnd && *CIP == ':') { 100 ++CIP; 101 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 102 ++CIP; 103 104 if (CIP < CPUInfoEnd) { 105 CPUStart = CIP; 106 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 107 *CIP != ',' && *CIP != '\n')) 108 ++CIP; 109 CPULen = CIP - CPUStart; 110 } 111 } 112 } 113 } 114 } 115 116 if (CPUStart == 0) 117 while (CIP < CPUInfoEnd && *CIP != '\n') 118 ++CIP; 119 } 120 121 if (CPUStart == 0) 122 return generic; 123 124 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 125 .Case("604e", "604e") 126 .Case("604", "604") 127 .Case("7400", "7400") 128 .Case("7410", "7400") 129 .Case("7447", "7400") 130 .Case("7455", "7450") 131 .Case("G4", "g4") 132 .Case("POWER4", "970") 133 .Case("PPC970FX", "970") 134 .Case("PPC970MP", "970") 135 .Case("G5", "g5") 136 .Case("POWER5", "g5") 137 .Case("A2", "a2") 138 .Case("POWER6", "pwr6") 139 .Case("POWER7", "pwr7") 140 .Case("POWER8", "pwr8") 141 .Case("POWER8E", "pwr8") 142 .Case("POWER8NVL", "pwr8") 143 .Case("POWER9", "pwr9") 144 .Default(generic); 145 } 146 147 StringRef sys::detail::getHostCPUNameForARM( 148 const StringRef &ProcCpuinfoContent) { 149 // The cpuid register on arm is not accessible from user space. On Linux, 150 // it is exposed through the /proc/cpuinfo file. 151 152 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 153 // in all cases. 154 SmallVector<StringRef, 32> Lines; 155 ProcCpuinfoContent.split(Lines, "\n"); 156 157 // Look for the CPU implementer line. 158 StringRef Implementer; 159 StringRef Hardware; 160 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 161 if (Lines[I].startswith("CPU implementer")) 162 Implementer = Lines[I].substr(15).ltrim("\t :"); 163 if (Lines[I].startswith("Hardware")) 164 Hardware = Lines[I].substr(8).ltrim("\t :"); 165 } 166 167 if (Implementer == "0x41") { // ARM Ltd. 168 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 169 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 170 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 171 return "cortex-a53"; 172 173 174 // Look for the CPU part line. 175 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 176 if (Lines[I].startswith("CPU part")) 177 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 178 // values correspond to the "Part number" in the CP15/c0 register. The 179 // contents are specified in the various processor manuals. 180 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 181 .Case("0x926", "arm926ej-s") 182 .Case("0xb02", "mpcore") 183 .Case("0xb36", "arm1136j-s") 184 .Case("0xb56", "arm1156t2-s") 185 .Case("0xb76", "arm1176jz-s") 186 .Case("0xc08", "cortex-a8") 187 .Case("0xc09", "cortex-a9") 188 .Case("0xc0f", "cortex-a15") 189 .Case("0xc20", "cortex-m0") 190 .Case("0xc23", "cortex-m3") 191 .Case("0xc24", "cortex-m4") 192 .Case("0xd04", "cortex-a35") 193 .Case("0xd03", "cortex-a53") 194 .Case("0xd07", "cortex-a57") 195 .Case("0xd08", "cortex-a72") 196 .Case("0xd09", "cortex-a73") 197 .Default("generic"); 198 } 199 200 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 201 // Look for the CPU part line. 202 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 203 if (Lines[I].startswith("CPU part")) 204 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 205 // values correspond to the "Part number" in the CP15/c0 register. The 206 // contents are specified in the various processor manuals. 207 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 208 .Case("0x06f", "krait") // APQ8064 209 .Case("0x201", "kryo") 210 .Case("0x205", "kryo") 211 .Default("generic"); 212 213 return "generic"; 214 } 215 216 StringRef sys::detail::getHostCPUNameForS390x( 217 const StringRef &ProcCpuinfoContent) { 218 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 219 220 // The "processor 0:" line comes after a fair amount of other information, 221 // including a cache breakdown, but this should be plenty. 222 SmallVector<StringRef, 32> Lines; 223 ProcCpuinfoContent.split(Lines, "\n"); 224 225 // Look for the CPU features. 226 SmallVector<StringRef, 32> CPUFeatures; 227 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 228 if (Lines[I].startswith("features")) { 229 size_t Pos = Lines[I].find(":"); 230 if (Pos != StringRef::npos) { 231 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 232 break; 233 } 234 } 235 236 // We need to check for the presence of vector support independently of 237 // the machine type, since we may only use the vector register set when 238 // supported by the kernel (and hypervisor). 239 bool HaveVectorSupport = false; 240 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 241 if (CPUFeatures[I] == "vx") 242 HaveVectorSupport = true; 243 } 244 245 // Now check the processor machine type. 246 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 247 if (Lines[I].startswith("processor ")) { 248 size_t Pos = Lines[I].find("machine = "); 249 if (Pos != StringRef::npos) { 250 Pos += sizeof("machine = ") - 1; 251 unsigned int Id; 252 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 253 if (Id >= 3906 && HaveVectorSupport) 254 return "z14"; 255 if (Id >= 2964 && HaveVectorSupport) 256 return "z13"; 257 if (Id >= 2827) 258 return "zEC12"; 259 if (Id >= 2817) 260 return "z196"; 261 } 262 } 263 break; 264 } 265 } 266 267 return "generic"; 268 } 269 270 #if defined(__i386__) || defined(_M_IX86) || \ 271 defined(__x86_64__) || defined(_M_X64) 272 273 enum VendorSignatures { 274 SIG_INTEL = 0x756e6547 /* Genu */, 275 SIG_AMD = 0x68747541 /* Auth */ 276 }; 277 278 enum ProcessorVendors { 279 VENDOR_INTEL = 1, 280 VENDOR_AMD, 281 VENDOR_OTHER, 282 VENDOR_MAX 283 }; 284 285 enum ProcessorTypes { 286 INTEL_BONNELL = 1, 287 INTEL_CORE2, 288 INTEL_COREI7, 289 AMDFAM10H, 290 AMDFAM15H, 291 INTEL_SILVERMONT, 292 INTEL_KNL, 293 AMD_BTVER1, 294 AMD_BTVER2, 295 AMDFAM17H, 296 // Entries below this are not in libgcc/compiler-rt. 297 INTEL_i386, 298 INTEL_i486, 299 INTEL_PENTIUM, 300 INTEL_PENTIUM_PRO, 301 INTEL_PENTIUM_II, 302 INTEL_PENTIUM_III, 303 INTEL_PENTIUM_IV, 304 INTEL_PENTIUM_M, 305 INTEL_CORE_DUO, 306 INTEL_X86_64, 307 INTEL_NOCONA, 308 INTEL_PRESCOTT, 309 AMD_i486, 310 AMDPENTIUM, 311 AMDATHLON, 312 INTEL_GOLDMONT, 313 CPU_TYPE_MAX 314 }; 315 316 enum ProcessorSubtypes { 317 INTEL_COREI7_NEHALEM = 1, 318 INTEL_COREI7_WESTMERE, 319 INTEL_COREI7_SANDYBRIDGE, 320 AMDFAM10H_BARCELONA, 321 AMDFAM10H_SHANGHAI, 322 AMDFAM10H_ISTANBUL, 323 AMDFAM15H_BDVER1, 324 AMDFAM15H_BDVER2, 325 AMDFAM15H_BDVER3, 326 AMDFAM15H_BDVER4, 327 AMDFAM17H_ZNVER1, 328 INTEL_COREI7_IVYBRIDGE, 329 INTEL_COREI7_HASWELL, 330 INTEL_COREI7_BROADWELL, 331 INTEL_COREI7_SKYLAKE, 332 INTEL_COREI7_SKYLAKE_AVX512, 333 // Entries below this are not in libgcc/compiler-rt. 334 INTEL_PENTIUM_MMX, 335 INTEL_CORE2_65, 336 INTEL_CORE2_45, 337 AMDPENTIUM_K6, 338 AMDPENTIUM_K62, 339 AMDPENTIUM_K63, 340 AMDPENTIUM_GEODE, 341 AMDATHLON_CLASSIC, 342 AMDATHLON_XP, 343 AMDATHLON_K8, 344 AMDATHLON_K8SSE3, 345 CPU_SUBTYPE_MAX 346 }; 347 348 enum ProcessorFeatures { 349 FEATURE_CMOV = 0, 350 FEATURE_MMX, 351 FEATURE_POPCNT, 352 FEATURE_SSE, 353 FEATURE_SSE2, 354 FEATURE_SSE3, 355 FEATURE_SSSE3, 356 FEATURE_SSE4_1, 357 FEATURE_SSE4_2, 358 FEATURE_AVX, 359 FEATURE_AVX2, 360 FEATURE_SSE4_A, 361 FEATURE_FMA4, 362 FEATURE_XOP, 363 FEATURE_FMA, 364 FEATURE_AVX512F, 365 FEATURE_BMI, 366 FEATURE_BMI2, 367 FEATURE_AES, 368 FEATURE_PCLMUL, 369 FEATURE_AVX512VL, 370 FEATURE_AVX512BW, 371 FEATURE_AVX512DQ, 372 FEATURE_AVX512CD, 373 FEATURE_AVX512ER, 374 FEATURE_AVX512PF, 375 FEATURE_AVX512VBMI, 376 FEATURE_AVX512IFMA, 377 FEATURE_AVX5124VNNIW, 378 FEATURE_AVX5124FMAPS, 379 FEATURE_AVX512VPOPCNTDQ, 380 // Only one bit free left in the first 32 features. 381 FEATURE_MOVBE = 32, 382 FEATURE_ADX, 383 FEATURE_EM64T, 384 FEATURE_CLFLUSHOPT, 385 FEATURE_SHA, 386 }; 387 388 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 389 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 390 // support. Consequently, for i386, the presence of CPUID is checked first 391 // via the corresponding eflags bit. 392 // Removal of cpuid.h header motivated by PR30384 393 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 394 // or test-suite, but are used in external projects e.g. libstdcxx 395 static bool isCpuIdSupported() { 396 #if defined(__GNUC__) || defined(__clang__) 397 #if defined(__i386__) 398 int __cpuid_supported; 399 __asm__(" pushfl\n" 400 " popl %%eax\n" 401 " movl %%eax,%%ecx\n" 402 " xorl $0x00200000,%%eax\n" 403 " pushl %%eax\n" 404 " popfl\n" 405 " pushfl\n" 406 " popl %%eax\n" 407 " movl $0,%0\n" 408 " cmpl %%eax,%%ecx\n" 409 " je 1f\n" 410 " movl $1,%0\n" 411 "1:" 412 : "=r"(__cpuid_supported) 413 : 414 : "eax", "ecx"); 415 if (!__cpuid_supported) 416 return false; 417 #endif 418 return true; 419 #endif 420 return true; 421 } 422 423 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 424 /// the specified arguments. If we can't run cpuid on the host, return true. 425 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 426 unsigned *rECX, unsigned *rEDX) { 427 #if defined(__GNUC__) || defined(__clang__) 428 #if defined(__x86_64__) 429 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 430 // FIXME: should we save this for Clang? 431 __asm__("movq\t%%rbx, %%rsi\n\t" 432 "cpuid\n\t" 433 "xchgq\t%%rbx, %%rsi\n\t" 434 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 435 : "a"(value)); 436 return false; 437 #elif defined(__i386__) 438 __asm__("movl\t%%ebx, %%esi\n\t" 439 "cpuid\n\t" 440 "xchgl\t%%ebx, %%esi\n\t" 441 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 442 : "a"(value)); 443 return false; 444 #else 445 return true; 446 #endif 447 #elif defined(_MSC_VER) 448 // The MSVC intrinsic is portable across x86 and x64. 449 int registers[4]; 450 __cpuid(registers, value); 451 *rEAX = registers[0]; 452 *rEBX = registers[1]; 453 *rECX = registers[2]; 454 *rEDX = registers[3]; 455 return false; 456 #else 457 return true; 458 #endif 459 } 460 461 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 462 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 463 /// return true. 464 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 465 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 466 unsigned *rEDX) { 467 #if defined(__GNUC__) || defined(__clang__) 468 #if defined(__x86_64__) 469 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 470 // FIXME: should we save this for Clang? 471 __asm__("movq\t%%rbx, %%rsi\n\t" 472 "cpuid\n\t" 473 "xchgq\t%%rbx, %%rsi\n\t" 474 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 475 : "a"(value), "c"(subleaf)); 476 return false; 477 #elif defined(__i386__) 478 __asm__("movl\t%%ebx, %%esi\n\t" 479 "cpuid\n\t" 480 "xchgl\t%%ebx, %%esi\n\t" 481 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 482 : "a"(value), "c"(subleaf)); 483 return false; 484 #else 485 return true; 486 #endif 487 #elif defined(_MSC_VER) 488 int registers[4]; 489 __cpuidex(registers, value, subleaf); 490 *rEAX = registers[0]; 491 *rEBX = registers[1]; 492 *rECX = registers[2]; 493 *rEDX = registers[3]; 494 return false; 495 #else 496 return true; 497 #endif 498 } 499 500 // Read control register 0 (XCR0). Used to detect features such as AVX. 501 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 502 #if defined(__GNUC__) || defined(__clang__) 503 // Check xgetbv; this uses a .byte sequence instead of the instruction 504 // directly because older assemblers do not include support for xgetbv and 505 // there is no easy way to conditionally compile based on the assembler used. 506 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 507 return false; 508 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 509 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 510 *rEAX = Result; 511 *rEDX = Result >> 32; 512 return false; 513 #else 514 return true; 515 #endif 516 } 517 518 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 519 unsigned *Model) { 520 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 521 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 522 if (*Family == 6 || *Family == 0xf) { 523 if (*Family == 0xf) 524 // Examine extended family ID if family ID is F. 525 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 526 // Examine extended model ID if family ID is 6 or F. 527 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 528 } 529 } 530 531 static void 532 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 533 unsigned Brand_id, unsigned Features, 534 unsigned Features2, unsigned *Type, 535 unsigned *Subtype) { 536 if (Brand_id != 0) 537 return; 538 switch (Family) { 539 case 3: 540 *Type = INTEL_i386; 541 break; 542 case 4: 543 switch (Model) { 544 case 0: // Intel486 DX processors 545 case 1: // Intel486 DX processors 546 case 2: // Intel486 SX processors 547 case 3: // Intel487 processors, IntelDX2 OverDrive processors, 548 // IntelDX2 processors 549 case 4: // Intel486 SL processor 550 case 5: // IntelSX2 processors 551 case 7: // Write-Back Enhanced IntelDX2 processors 552 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors 553 default: 554 *Type = INTEL_i486; 555 break; 556 } 557 break; 558 case 5: 559 switch (Model) { 560 case 1: // Pentium OverDrive processor for Pentium processor (60, 66), 561 // Pentium processors (60, 66) 562 case 2: // Pentium OverDrive processor for Pentium processor (75, 90, 563 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133, 564 // 150, 166, 200) 565 case 3: // Pentium OverDrive processors for Intel486 processor-based 566 // systems 567 *Type = INTEL_PENTIUM; 568 break; 569 case 4: // Pentium OverDrive processor with MMX technology for Pentium 570 // processor (75, 90, 100, 120, 133), Pentium processor with 571 // MMX technology (166, 200) 572 *Type = INTEL_PENTIUM; 573 *Subtype = INTEL_PENTIUM_MMX; 574 break; 575 default: 576 *Type = INTEL_PENTIUM; 577 break; 578 } 579 break; 580 case 6: 581 switch (Model) { 582 case 0x01: // Pentium Pro processor 583 *Type = INTEL_PENTIUM_PRO; 584 break; 585 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 586 // model 03 587 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 588 // model 05, and Intel Celeron processor, model 05 589 case 0x06: // Celeron processor, model 06 590 *Type = INTEL_PENTIUM_II; 591 break; 592 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 593 // processor, model 07 594 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 595 // model 08, and Celeron processor, model 08 596 case 0x0a: // Pentium III Xeon processor, model 0Ah 597 case 0x0b: // Pentium III processor, model 0Bh 598 *Type = INTEL_PENTIUM_III; 599 break; 600 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 601 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 602 // 0Dh. All processors are manufactured using the 90 nm process. 603 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 604 // Integrated Processor with Intel QuickAssist Technology 605 *Type = INTEL_PENTIUM_M; 606 break; 607 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 608 // 0Eh. All processors are manufactured using the 65 nm process. 609 *Type = INTEL_CORE_DUO; 610 break; // yonah 611 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 612 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 613 // mobile processor, Intel Core 2 Extreme processor, Intel 614 // Pentium Dual-Core processor, Intel Xeon processor, model 615 // 0Fh. All processors are manufactured using the 65 nm process. 616 case 0x16: // Intel Celeron processor model 16h. All processors are 617 // manufactured using the 65 nm process 618 *Type = INTEL_CORE2; // "core2" 619 *Subtype = INTEL_CORE2_65; 620 break; 621 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 622 // 17h. All processors are manufactured using the 45 nm process. 623 // 624 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 625 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 626 // the 45 nm process. 627 *Type = INTEL_CORE2; // "penryn" 628 *Subtype = INTEL_CORE2_45; 629 break; 630 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 631 // processors are manufactured using the 45 nm process. 632 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 633 // As found in a Summer 2010 model iMac. 634 case 0x1f: 635 case 0x2e: // Nehalem EX 636 *Type = INTEL_COREI7; // "nehalem" 637 *Subtype = INTEL_COREI7_NEHALEM; 638 break; 639 case 0x25: // Intel Core i7, laptop version. 640 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 641 // processors are manufactured using the 32 nm process. 642 case 0x2f: // Westmere EX 643 *Type = INTEL_COREI7; // "westmere" 644 *Subtype = INTEL_COREI7_WESTMERE; 645 break; 646 case 0x2a: // Intel Core i7 processor. All processors are manufactured 647 // using the 32 nm process. 648 case 0x2d: 649 *Type = INTEL_COREI7; //"sandybridge" 650 *Subtype = INTEL_COREI7_SANDYBRIDGE; 651 break; 652 case 0x3a: 653 case 0x3e: // Ivy Bridge EP 654 *Type = INTEL_COREI7; // "ivybridge" 655 *Subtype = INTEL_COREI7_IVYBRIDGE; 656 break; 657 658 // Haswell: 659 case 0x3c: 660 case 0x3f: 661 case 0x45: 662 case 0x46: 663 *Type = INTEL_COREI7; // "haswell" 664 *Subtype = INTEL_COREI7_HASWELL; 665 break; 666 667 // Broadwell: 668 case 0x3d: 669 case 0x47: 670 case 0x4f: 671 case 0x56: 672 *Type = INTEL_COREI7; // "broadwell" 673 *Subtype = INTEL_COREI7_BROADWELL; 674 break; 675 676 // Skylake: 677 case 0x4e: // Skylake mobile 678 case 0x5e: // Skylake desktop 679 case 0x8e: // Kaby Lake mobile 680 case 0x9e: // Kaby Lake desktop 681 *Type = INTEL_COREI7; // "skylake" 682 *Subtype = INTEL_COREI7_SKYLAKE; 683 break; 684 685 // Skylake Xeon: 686 case 0x55: 687 *Type = INTEL_COREI7; 688 *Subtype = INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 689 break; 690 691 case 0x1c: // Most 45 nm Intel Atom processors 692 case 0x26: // 45 nm Atom Lincroft 693 case 0x27: // 32 nm Atom Medfield 694 case 0x35: // 32 nm Atom Midview 695 case 0x36: // 32 nm Atom Midview 696 *Type = INTEL_BONNELL; 697 break; // "bonnell" 698 699 // Atom Silvermont codes from the Intel software optimization guide. 700 case 0x37: 701 case 0x4a: 702 case 0x4d: 703 case 0x5a: 704 case 0x5d: 705 case 0x4c: // really airmont 706 *Type = INTEL_SILVERMONT; 707 break; // "silvermont" 708 // Goldmont: 709 case 0x5c: 710 case 0x5f: 711 *Type = INTEL_GOLDMONT; 712 break; // "goldmont" 713 case 0x57: 714 *Type = INTEL_KNL; // knl 715 break; 716 717 default: // Unknown family 6 CPU, try to guess. 718 if (Features & (1 << FEATURE_AVX512F)) { 719 if (Features & (1 << FEATURE_AVX512VL)) { 720 *Type = INTEL_COREI7; 721 *Subtype = INTEL_COREI7_SKYLAKE_AVX512; 722 } else { 723 *Type = INTEL_KNL; // knl 724 } 725 break; 726 } 727 if (Features2 & (1 << (FEATURE_CLFLUSHOPT - 32))) { 728 if (Features2 & (1 << (FEATURE_SHA - 32))) { 729 *Type = INTEL_GOLDMONT; 730 } else { 731 *Type = INTEL_COREI7; 732 *Subtype = INTEL_COREI7_SKYLAKE; 733 } 734 break; 735 } 736 if (Features2 & (1 << (FEATURE_ADX - 32))) { 737 *Type = INTEL_COREI7; 738 *Subtype = INTEL_COREI7_BROADWELL; 739 break; 740 } 741 if (Features & (1 << FEATURE_AVX2)) { 742 *Type = INTEL_COREI7; 743 *Subtype = INTEL_COREI7_HASWELL; 744 break; 745 } 746 if (Features & (1 << FEATURE_AVX)) { 747 *Type = INTEL_COREI7; 748 *Subtype = INTEL_COREI7_SANDYBRIDGE; 749 break; 750 } 751 if (Features & (1 << FEATURE_SSE4_2)) { 752 if (Features2 & (1 << (FEATURE_MOVBE - 32))) { 753 *Type = INTEL_SILVERMONT; 754 } else { 755 *Type = INTEL_COREI7; 756 *Subtype = INTEL_COREI7_NEHALEM; 757 } 758 break; 759 } 760 if (Features & (1 << FEATURE_SSE4_1)) { 761 *Type = INTEL_CORE2; // "penryn" 762 *Subtype = INTEL_CORE2_45; 763 break; 764 } 765 if (Features & (1 << FEATURE_SSSE3)) { 766 if (Features2 & (1 << (FEATURE_MOVBE - 32))) { 767 *Type = INTEL_BONNELL; // "bonnell" 768 } else { 769 *Type = INTEL_CORE2; // "core2" 770 *Subtype = INTEL_CORE2_65; 771 } 772 break; 773 } 774 if (Features2 & (1 << (FEATURE_EM64T - 32))) { 775 *Type = INTEL_X86_64; 776 break; // x86-64 777 } 778 if (Features & (1 << FEATURE_SSE2)) { 779 *Type = INTEL_PENTIUM_M; 780 break; 781 } 782 if (Features & (1 << FEATURE_SSE)) { 783 *Type = INTEL_PENTIUM_III; 784 break; 785 } 786 if (Features & (1 << FEATURE_MMX)) { 787 *Type = INTEL_PENTIUM_II; 788 break; 789 } 790 *Type = INTEL_PENTIUM_PRO; 791 break; 792 } 793 break; 794 case 15: { 795 switch (Model) { 796 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are 797 // model 00h and manufactured using the 0.18 micron process. 798 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon 799 // processor MP, and Intel Celeron processor. All processors are 800 // model 01h and manufactured using the 0.18 micron process. 801 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M, 802 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron 803 // processor, and Mobile Intel Celeron processor. All processors 804 // are model 02h and manufactured using the 0.13 micron process. 805 *Type = ((Features2 & (1 << (FEATURE_EM64T - 32))) ? INTEL_X86_64 806 : INTEL_PENTIUM_IV); 807 break; 808 809 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D 810 // processor. All processors are model 03h and manufactured using 811 // the 90 nm process. 812 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition, 813 // Pentium D processor, Intel Xeon processor, Intel Xeon 814 // processor MP, Intel Celeron D processor. All processors are 815 // model 04h and manufactured using the 90 nm process. 816 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor 817 // Extreme Edition, Intel Xeon processor, Intel Xeon processor 818 // MP, Intel Celeron D processor. All processors are model 06h 819 // and manufactured using the 65 nm process. 820 *Type = ((Features2 & (1 << (FEATURE_EM64T - 32))) ? INTEL_NOCONA 821 : INTEL_PRESCOTT); 822 break; 823 824 default: 825 *Type = ((Features2 & (1 << (FEATURE_EM64T - 32))) ? INTEL_X86_64 826 : INTEL_PENTIUM_IV); 827 break; 828 } 829 break; 830 } 831 default: 832 break; /*"generic"*/ 833 } 834 } 835 836 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 837 unsigned Features, unsigned *Type, 838 unsigned *Subtype) { 839 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 840 // appears to be no way to generate the wide variety of AMD-specific targets 841 // from the information returned from CPUID. 842 switch (Family) { 843 case 4: 844 *Type = AMD_i486; 845 break; 846 case 5: 847 *Type = AMDPENTIUM; 848 switch (Model) { 849 case 6: 850 case 7: 851 *Subtype = AMDPENTIUM_K6; 852 break; // "k6" 853 case 8: 854 *Subtype = AMDPENTIUM_K62; 855 break; // "k6-2" 856 case 9: 857 case 13: 858 *Subtype = AMDPENTIUM_K63; 859 break; // "k6-3" 860 case 10: 861 *Subtype = AMDPENTIUM_GEODE; 862 break; // "geode" 863 } 864 break; 865 case 6: 866 *Type = AMDATHLON; 867 if (Features & (1 << FEATURE_SSE)) { 868 *Subtype = AMDATHLON_XP; 869 break; // "athlon-xp" 870 } 871 *Subtype = AMDATHLON_CLASSIC; 872 break; // "athlon" 873 case 15: 874 *Type = AMDATHLON; 875 if (Features & (1 << FEATURE_SSE3)) { 876 *Subtype = AMDATHLON_K8SSE3; 877 break; // "k8-sse3" 878 } 879 *Subtype = AMDATHLON_K8; 880 break; // "k8" 881 case 16: 882 *Type = AMDFAM10H; // "amdfam10" 883 switch (Model) { 884 case 2: 885 *Subtype = AMDFAM10H_BARCELONA; 886 break; 887 case 4: 888 *Subtype = AMDFAM10H_SHANGHAI; 889 break; 890 case 8: 891 *Subtype = AMDFAM10H_ISTANBUL; 892 break; 893 } 894 break; 895 case 20: 896 *Type = AMD_BTVER1; 897 break; // "btver1"; 898 case 21: 899 *Type = AMDFAM15H; 900 if (Model >= 0x60 && Model <= 0x7f) { 901 *Subtype = AMDFAM15H_BDVER4; 902 break; // "bdver4"; 60h-7Fh: Excavator 903 } 904 if (Model >= 0x30 && Model <= 0x3f) { 905 *Subtype = AMDFAM15H_BDVER3; 906 break; // "bdver3"; 30h-3Fh: Steamroller 907 } 908 if (Model >= 0x10 && Model <= 0x1f) { 909 *Subtype = AMDFAM15H_BDVER2; 910 break; // "bdver2"; 10h-1Fh: Piledriver 911 } 912 if (Model <= 0x0f) { 913 *Subtype = AMDFAM15H_BDVER1; 914 break; // "bdver1"; 00h-0Fh: Bulldozer 915 } 916 break; 917 case 22: 918 *Type = AMD_BTVER2; 919 break; // "btver2" 920 case 23: 921 *Type = AMDFAM17H; 922 *Subtype = AMDFAM17H_ZNVER1; 923 break; 924 default: 925 break; // "generic" 926 } 927 } 928 929 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 930 unsigned *FeaturesOut, 931 unsigned *Features2Out) { 932 unsigned Features = 0; 933 unsigned Features2 = 0; 934 unsigned EAX, EBX; 935 936 if ((EDX >> 15) & 1) 937 Features |= 1 << FEATURE_CMOV; 938 if ((EDX >> 23) & 1) 939 Features |= 1 << FEATURE_MMX; 940 if ((EDX >> 25) & 1) 941 Features |= 1 << FEATURE_SSE; 942 if ((EDX >> 26) & 1) 943 Features |= 1 << FEATURE_SSE2; 944 945 if ((ECX >> 0) & 1) 946 Features |= 1 << FEATURE_SSE3; 947 if ((ECX >> 1) & 1) 948 Features |= 1 << FEATURE_PCLMUL; 949 if ((ECX >> 9) & 1) 950 Features |= 1 << FEATURE_SSSE3; 951 if ((ECX >> 12) & 1) 952 Features |= 1 << FEATURE_FMA; 953 if ((ECX >> 19) & 1) 954 Features |= 1 << FEATURE_SSE4_1; 955 if ((ECX >> 20) & 1) 956 Features |= 1 << FEATURE_SSE4_2; 957 if ((ECX >> 23) & 1) 958 Features |= 1 << FEATURE_POPCNT; 959 if ((ECX >> 25) & 1) 960 Features |= 1 << FEATURE_AES; 961 962 if ((ECX >> 22) & 1) 963 Features2 |= 1 << (FEATURE_MOVBE - 32); 964 965 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 966 // indicates that the AVX registers will be saved and restored on context 967 // switch, then we have full AVX support. 968 const unsigned AVXBits = (1 << 27) | (1 << 28); 969 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 970 ((EAX & 0x6) == 0x6); 971 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 972 973 if (HasAVX) 974 Features |= 1 << FEATURE_AVX; 975 976 bool HasLeaf7 = 977 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 978 979 if (HasLeaf7 && ((EBX >> 3) & 1)) 980 Features |= 1 << FEATURE_BMI; 981 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 982 Features |= 1 << FEATURE_AVX2; 983 if (HasLeaf7 && ((EBX >> 9) & 1)) 984 Features |= 1 << FEATURE_BMI2; 985 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 986 Features |= 1 << FEATURE_AVX512F; 987 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 988 Features |= 1 << FEATURE_AVX512DQ; 989 if (HasLeaf7 && ((EBX >> 19) & 1)) 990 Features2 |= 1 << (FEATURE_ADX - 32); 991 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 992 Features |= 1 << FEATURE_AVX512IFMA; 993 if (HasLeaf7 && ((EBX >> 23) & 1)) 994 Features2 |= 1 << (FEATURE_CLFLUSHOPT - 32); 995 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 996 Features |= 1 << FEATURE_AVX512PF; 997 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 998 Features |= 1 << FEATURE_AVX512ER; 999 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 1000 Features |= 1 << FEATURE_AVX512CD; 1001 if (HasLeaf7 && ((EBX >> 29) & 1)) 1002 Features2 |= 1 << (FEATURE_SHA - 32); 1003 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 1004 Features |= 1 << FEATURE_AVX512BW; 1005 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 1006 Features |= 1 << FEATURE_AVX512VL; 1007 1008 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 1009 Features |= 1 << FEATURE_AVX512VBMI; 1010 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1011 Features |= 1 << FEATURE_AVX512VPOPCNTDQ; 1012 1013 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1014 Features |= 1 << FEATURE_AVX5124VNNIW; 1015 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1016 Features |= 1 << FEATURE_AVX5124FMAPS; 1017 1018 unsigned MaxExtLevel; 1019 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1020 1021 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1022 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1023 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1024 Features |= 1 << FEATURE_SSE4_A; 1025 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1026 Features |= 1 << FEATURE_XOP; 1027 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1028 Features |= 1 << FEATURE_FMA4; 1029 1030 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1031 Features2 |= 1 << (FEATURE_EM64T - 32); 1032 1033 *FeaturesOut = Features; 1034 *Features2Out = Features2; 1035 } 1036 1037 StringRef sys::getHostCPUName() { 1038 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1039 unsigned MaxLeaf, Vendor; 1040 1041 #if defined(__GNUC__) || defined(__clang__) 1042 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here 1043 // and simplify it to not invoke __cpuid (like cpu_model.c in 1044 // compiler-rt/lib/builtins/cpu_model.c? 1045 // Opting for the second option. 1046 if(!isCpuIdSupported()) 1047 return "generic"; 1048 #endif 1049 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) 1050 return "generic"; 1051 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1052 1053 unsigned Brand_id = EBX & 0xff; 1054 unsigned Family = 0, Model = 0; 1055 unsigned Features = 0, Features2 = 0; 1056 detectX86FamilyModel(EAX, &Family, &Model); 1057 getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2); 1058 1059 unsigned Type; 1060 unsigned Subtype; 1061 1062 if (Vendor == SIG_INTEL) { 1063 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, 1064 Features2, &Type, &Subtype); 1065 switch (Type) { 1066 case INTEL_i386: 1067 return "i386"; 1068 case INTEL_i486: 1069 return "i486"; 1070 case INTEL_PENTIUM: 1071 if (Subtype == INTEL_PENTIUM_MMX) 1072 return "pentium-mmx"; 1073 return "pentium"; 1074 case INTEL_PENTIUM_PRO: 1075 return "pentiumpro"; 1076 case INTEL_PENTIUM_II: 1077 return "pentium2"; 1078 case INTEL_PENTIUM_III: 1079 return "pentium3"; 1080 case INTEL_PENTIUM_IV: 1081 return "pentium4"; 1082 case INTEL_PENTIUM_M: 1083 return "pentium-m"; 1084 case INTEL_CORE_DUO: 1085 return "yonah"; 1086 case INTEL_CORE2: 1087 switch (Subtype) { 1088 case INTEL_CORE2_65: 1089 return "core2"; 1090 case INTEL_CORE2_45: 1091 return "penryn"; 1092 default: 1093 llvm_unreachable("Unexpected subtype!"); 1094 } 1095 case INTEL_COREI7: 1096 switch (Subtype) { 1097 case INTEL_COREI7_NEHALEM: 1098 return "nehalem"; 1099 case INTEL_COREI7_WESTMERE: 1100 return "westmere"; 1101 case INTEL_COREI7_SANDYBRIDGE: 1102 return "sandybridge"; 1103 case INTEL_COREI7_IVYBRIDGE: 1104 return "ivybridge"; 1105 case INTEL_COREI7_HASWELL: 1106 return "haswell"; 1107 case INTEL_COREI7_BROADWELL: 1108 return "broadwell"; 1109 case INTEL_COREI7_SKYLAKE: 1110 return "skylake"; 1111 case INTEL_COREI7_SKYLAKE_AVX512: 1112 return "skylake-avx512"; 1113 default: 1114 llvm_unreachable("Unexpected subtype!"); 1115 } 1116 case INTEL_BONNELL: 1117 return "bonnell"; 1118 case INTEL_SILVERMONT: 1119 return "silvermont"; 1120 case INTEL_GOLDMONT: 1121 return "goldmont"; 1122 case INTEL_KNL: 1123 return "knl"; 1124 case INTEL_X86_64: 1125 return "x86-64"; 1126 case INTEL_NOCONA: 1127 return "nocona"; 1128 case INTEL_PRESCOTT: 1129 return "prescott"; 1130 default: 1131 break; 1132 } 1133 } else if (Vendor == SIG_AMD) { 1134 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1135 switch (Type) { 1136 case AMD_i486: 1137 return "i486"; 1138 case AMDPENTIUM: 1139 switch (Subtype) { 1140 case AMDPENTIUM_K6: 1141 return "k6"; 1142 case AMDPENTIUM_K62: 1143 return "k6-2"; 1144 case AMDPENTIUM_K63: 1145 return "k6-3"; 1146 case AMDPENTIUM_GEODE: 1147 return "geode"; 1148 default: 1149 return "pentium"; 1150 } 1151 case AMDATHLON: 1152 switch (Subtype) { 1153 case AMDATHLON_CLASSIC: 1154 return "athlon"; 1155 case AMDATHLON_XP: 1156 return "athlon-xp"; 1157 case AMDATHLON_K8: 1158 return "k8"; 1159 case AMDATHLON_K8SSE3: 1160 return "k8-sse3"; 1161 default: 1162 llvm_unreachable("Unexpected subtype!"); 1163 } 1164 case AMDFAM10H: 1165 return "amdfam10"; 1166 case AMD_BTVER1: 1167 return "btver1"; 1168 case AMDFAM15H: 1169 switch (Subtype) { 1170 default: // There are gaps in the subtype detection. 1171 case AMDFAM15H_BDVER1: 1172 return "bdver1"; 1173 case AMDFAM15H_BDVER2: 1174 return "bdver2"; 1175 case AMDFAM15H_BDVER3: 1176 return "bdver3"; 1177 case AMDFAM15H_BDVER4: 1178 return "bdver4"; 1179 } 1180 case AMD_BTVER2: 1181 return "btver2"; 1182 case AMDFAM17H: 1183 return "znver1"; 1184 default: 1185 break; 1186 } 1187 } 1188 return "generic"; 1189 } 1190 1191 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1192 StringRef sys::getHostCPUName() { 1193 host_basic_info_data_t hostInfo; 1194 mach_msg_type_number_t infoCount; 1195 1196 infoCount = HOST_BASIC_INFO_COUNT; 1197 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo, 1198 &infoCount); 1199 1200 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1201 return "generic"; 1202 1203 switch (hostInfo.cpu_subtype) { 1204 case CPU_SUBTYPE_POWERPC_601: 1205 return "601"; 1206 case CPU_SUBTYPE_POWERPC_602: 1207 return "602"; 1208 case CPU_SUBTYPE_POWERPC_603: 1209 return "603"; 1210 case CPU_SUBTYPE_POWERPC_603e: 1211 return "603e"; 1212 case CPU_SUBTYPE_POWERPC_603ev: 1213 return "603ev"; 1214 case CPU_SUBTYPE_POWERPC_604: 1215 return "604"; 1216 case CPU_SUBTYPE_POWERPC_604e: 1217 return "604e"; 1218 case CPU_SUBTYPE_POWERPC_620: 1219 return "620"; 1220 case CPU_SUBTYPE_POWERPC_750: 1221 return "750"; 1222 case CPU_SUBTYPE_POWERPC_7400: 1223 return "7400"; 1224 case CPU_SUBTYPE_POWERPC_7450: 1225 return "7450"; 1226 case CPU_SUBTYPE_POWERPC_970: 1227 return "970"; 1228 default:; 1229 } 1230 1231 return "generic"; 1232 } 1233 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1234 StringRef sys::getHostCPUName() { 1235 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1236 const StringRef& Content = P ? P->getBuffer() : ""; 1237 return detail::getHostCPUNameForPowerPC(Content); 1238 } 1239 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1240 StringRef sys::getHostCPUName() { 1241 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1242 const StringRef& Content = P ? P->getBuffer() : ""; 1243 return detail::getHostCPUNameForARM(Content); 1244 } 1245 #elif defined(__linux__) && defined(__s390x__) 1246 StringRef sys::getHostCPUName() { 1247 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1248 const StringRef& Content = P ? P->getBuffer() : ""; 1249 return detail::getHostCPUNameForS390x(Content); 1250 } 1251 #else 1252 StringRef sys::getHostCPUName() { return "generic"; } 1253 #endif 1254 1255 #if defined(__linux__) && defined(__x86_64__) 1256 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1257 // using the number of unique physical/core id pairs. The following 1258 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1259 static int computeHostNumPhysicalCores() { 1260 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1261 // mmapped because it appears to have 0 size. 1262 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1263 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1264 if (std::error_code EC = Text.getError()) { 1265 llvm::errs() << "Can't read " 1266 << "/proc/cpuinfo: " << EC.message() << "\n"; 1267 return -1; 1268 } 1269 SmallVector<StringRef, 8> strs; 1270 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1271 /*KeepEmpty=*/false); 1272 int CurPhysicalId = -1; 1273 int CurCoreId = -1; 1274 SmallSet<std::pair<int, int>, 32> UniqueItems; 1275 for (auto &Line : strs) { 1276 Line = Line.trim(); 1277 if (!Line.startswith("physical id") && !Line.startswith("core id")) 1278 continue; 1279 std::pair<StringRef, StringRef> Data = Line.split(':'); 1280 auto Name = Data.first.trim(); 1281 auto Val = Data.second.trim(); 1282 if (Name == "physical id") { 1283 assert(CurPhysicalId == -1 && 1284 "Expected a core id before seeing another physical id"); 1285 Val.getAsInteger(10, CurPhysicalId); 1286 } 1287 if (Name == "core id") { 1288 assert(CurCoreId == -1 && 1289 "Expected a physical id before seeing another core id"); 1290 Val.getAsInteger(10, CurCoreId); 1291 } 1292 if (CurPhysicalId != -1 && CurCoreId != -1) { 1293 UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId)); 1294 CurPhysicalId = -1; 1295 CurCoreId = -1; 1296 } 1297 } 1298 return UniqueItems.size(); 1299 } 1300 #elif defined(__APPLE__) && defined(__x86_64__) 1301 #include <sys/param.h> 1302 #include <sys/sysctl.h> 1303 1304 // Gets the number of *physical cores* on the machine. 1305 static int computeHostNumPhysicalCores() { 1306 uint32_t count; 1307 size_t len = sizeof(count); 1308 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1309 if (count < 1) { 1310 int nm[2]; 1311 nm[0] = CTL_HW; 1312 nm[1] = HW_AVAILCPU; 1313 sysctl(nm, 2, &count, &len, NULL, 0); 1314 if (count < 1) 1315 return -1; 1316 } 1317 return count; 1318 } 1319 #else 1320 // On other systems, return -1 to indicate unknown. 1321 static int computeHostNumPhysicalCores() { return -1; } 1322 #endif 1323 1324 int sys::getHostNumPhysicalCores() { 1325 static int NumCores = computeHostNumPhysicalCores(); 1326 return NumCores; 1327 } 1328 1329 #if defined(__i386__) || defined(_M_IX86) || \ 1330 defined(__x86_64__) || defined(_M_X64) 1331 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1332 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1333 unsigned MaxLevel; 1334 union { 1335 unsigned u[3]; 1336 char c[12]; 1337 } text; 1338 1339 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1340 MaxLevel < 1) 1341 return false; 1342 1343 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1344 1345 Features["cmov"] = (EDX >> 15) & 1; 1346 Features["mmx"] = (EDX >> 23) & 1; 1347 Features["sse"] = (EDX >> 25) & 1; 1348 Features["sse2"] = (EDX >> 26) & 1; 1349 Features["sse3"] = (ECX >> 0) & 1; 1350 Features["ssse3"] = (ECX >> 9) & 1; 1351 Features["sse4.1"] = (ECX >> 19) & 1; 1352 Features["sse4.2"] = (ECX >> 20) & 1; 1353 1354 Features["pclmul"] = (ECX >> 1) & 1; 1355 Features["cx16"] = (ECX >> 13) & 1; 1356 Features["movbe"] = (ECX >> 22) & 1; 1357 Features["popcnt"] = (ECX >> 23) & 1; 1358 Features["aes"] = (ECX >> 25) & 1; 1359 Features["rdrnd"] = (ECX >> 30) & 1; 1360 1361 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1362 // indicates that the AVX registers will be saved and restored on context 1363 // switch, then we have full AVX support. 1364 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1365 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1366 Features["avx"] = HasAVXSave; 1367 Features["fma"] = HasAVXSave && (ECX >> 12) & 1; 1368 Features["f16c"] = HasAVXSave && (ECX >> 29) & 1; 1369 1370 // Only enable XSAVE if OS has enabled support for saving YMM state. 1371 Features["xsave"] = HasAVXSave && (ECX >> 26) & 1; 1372 1373 // AVX512 requires additional context to be saved by the OS. 1374 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1375 1376 unsigned MaxExtLevel; 1377 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1378 1379 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1380 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1381 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1382 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1383 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1384 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1385 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1386 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1387 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1388 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1389 1390 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1391 !getX86CpuIDAndInfoEx(0x80000008,0x0, &EAX, &EBX, &ECX, &EDX); 1392 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1393 1394 bool HasLeaf7 = 1395 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1396 1397 // AVX2 is only supported if we have the OS save support from AVX. 1398 Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1); 1399 1400 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1401 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1402 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1403 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1404 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1405 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1406 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1407 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1408 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1409 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1410 1411 // AVX512 is only supported if the OS supports the context save for it. 1412 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1413 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1414 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1415 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1416 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1417 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1418 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1419 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1420 1421 Features["prefetchwt1"] = HasLeaf7 && (ECX & 1); 1422 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1423 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1424 // Enable protection keys 1425 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1426 1427 bool HasLeafD = MaxLevel >= 0xd && 1428 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1429 1430 // Only enable XSAVE if OS has enabled support for saving YMM state. 1431 Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1); 1432 Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1); 1433 Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1); 1434 1435 return true; 1436 } 1437 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1438 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1439 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1440 if (!P) 1441 return false; 1442 1443 SmallVector<StringRef, 32> Lines; 1444 P->getBuffer().split(Lines, "\n"); 1445 1446 SmallVector<StringRef, 32> CPUFeatures; 1447 1448 // Look for the CPU features. 1449 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1450 if (Lines[I].startswith("Features")) { 1451 Lines[I].split(CPUFeatures, ' '); 1452 break; 1453 } 1454 1455 #if defined(__aarch64__) 1456 // Keep track of which crypto features we have seen 1457 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1458 uint32_t crypto = 0; 1459 #endif 1460 1461 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1462 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1463 #if defined(__aarch64__) 1464 .Case("asimd", "neon") 1465 .Case("fp", "fp-armv8") 1466 .Case("crc32", "crc") 1467 #else 1468 .Case("half", "fp16") 1469 .Case("neon", "neon") 1470 .Case("vfpv3", "vfp3") 1471 .Case("vfpv3d16", "d16") 1472 .Case("vfpv4", "vfp4") 1473 .Case("idiva", "hwdiv-arm") 1474 .Case("idivt", "hwdiv") 1475 #endif 1476 .Default(""); 1477 1478 #if defined(__aarch64__) 1479 // We need to check crypto separately since we need all of the crypto 1480 // extensions to enable the subtarget feature 1481 if (CPUFeatures[I] == "aes") 1482 crypto |= CAP_AES; 1483 else if (CPUFeatures[I] == "pmull") 1484 crypto |= CAP_PMULL; 1485 else if (CPUFeatures[I] == "sha1") 1486 crypto |= CAP_SHA1; 1487 else if (CPUFeatures[I] == "sha2") 1488 crypto |= CAP_SHA2; 1489 #endif 1490 1491 if (LLVMFeatureStr != "") 1492 Features[LLVMFeatureStr] = true; 1493 } 1494 1495 #if defined(__aarch64__) 1496 // If we have all crypto bits we can add the feature 1497 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1498 Features["crypto"] = true; 1499 #endif 1500 1501 return true; 1502 } 1503 #else 1504 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1505 #endif 1506 1507 std::string sys::getProcessTriple() { 1508 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1509 Triple PT(Triple::normalize(TargetTripleString)); 1510 1511 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1512 PT = PT.get64BitArchVariant(); 1513 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1514 PT = PT.get32BitArchVariant(); 1515 1516 return PT.str(); 1517 } 1518