1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the operating system Host concept. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/Host.h" 14 #include "llvm/Support/TargetParser.h" 15 #include "llvm/ADT/SmallSet.h" 16 #include "llvm/ADT/SmallVector.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/llvm-config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include <assert.h> 26 #include <string.h> 27 28 // Include the platform-specific parts of this class. 29 #ifdef LLVM_ON_UNIX 30 #include "Unix/Host.inc" 31 #endif 32 #ifdef _WIN32 33 #include "Windows/Host.inc" 34 #endif 35 #ifdef _MSC_VER 36 #include <intrin.h> 37 #endif 38 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 39 #include <mach/host_info.h> 40 #include <mach/mach.h> 41 #include <mach/mach_host.h> 42 #include <mach/machine.h> 43 #endif 44 45 #define DEBUG_TYPE "host-detection" 46 47 //===----------------------------------------------------------------------===// 48 // 49 // Implementations of the CPU detection routines 50 // 51 //===----------------------------------------------------------------------===// 52 53 using namespace llvm; 54 55 static std::unique_ptr<llvm::MemoryBuffer> 56 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 57 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 58 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 59 if (std::error_code EC = Text.getError()) { 60 llvm::errs() << "Can't read " 61 << "/proc/cpuinfo: " << EC.message() << "\n"; 62 return nullptr; 63 } 64 return std::move(*Text); 65 } 66 67 StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) { 68 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 69 // and so we must use an operating-system interface to determine the current 70 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 71 const char *generic = "generic"; 72 73 // The cpu line is second (after the 'processor: 0' line), so if this 74 // buffer is too small then something has changed (or is wrong). 75 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 76 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 77 78 StringRef::const_iterator CIP = CPUInfoStart; 79 80 StringRef::const_iterator CPUStart = 0; 81 size_t CPULen = 0; 82 83 // We need to find the first line which starts with cpu, spaces, and a colon. 84 // After the colon, there may be some additional spaces and then the cpu type. 85 while (CIP < CPUInfoEnd && CPUStart == 0) { 86 if (CIP < CPUInfoEnd && *CIP == '\n') 87 ++CIP; 88 89 if (CIP < CPUInfoEnd && *CIP == 'c') { 90 ++CIP; 91 if (CIP < CPUInfoEnd && *CIP == 'p') { 92 ++CIP; 93 if (CIP < CPUInfoEnd && *CIP == 'u') { 94 ++CIP; 95 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 96 ++CIP; 97 98 if (CIP < CPUInfoEnd && *CIP == ':') { 99 ++CIP; 100 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 101 ++CIP; 102 103 if (CIP < CPUInfoEnd) { 104 CPUStart = CIP; 105 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 106 *CIP != ',' && *CIP != '\n')) 107 ++CIP; 108 CPULen = CIP - CPUStart; 109 } 110 } 111 } 112 } 113 } 114 115 if (CPUStart == 0) 116 while (CIP < CPUInfoEnd && *CIP != '\n') 117 ++CIP; 118 } 119 120 if (CPUStart == 0) 121 return generic; 122 123 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 124 .Case("604e", "604e") 125 .Case("604", "604") 126 .Case("7400", "7400") 127 .Case("7410", "7400") 128 .Case("7447", "7400") 129 .Case("7455", "7450") 130 .Case("G4", "g4") 131 .Case("POWER4", "970") 132 .Case("PPC970FX", "970") 133 .Case("PPC970MP", "970") 134 .Case("G5", "g5") 135 .Case("POWER5", "g5") 136 .Case("A2", "a2") 137 .Case("POWER6", "pwr6") 138 .Case("POWER7", "pwr7") 139 .Case("POWER8", "pwr8") 140 .Case("POWER8E", "pwr8") 141 .Case("POWER8NVL", "pwr8") 142 .Case("POWER9", "pwr9") 143 .Default(generic); 144 } 145 146 StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { 147 // The cpuid register on arm is not accessible from user space. On Linux, 148 // it is exposed through the /proc/cpuinfo file. 149 150 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 151 // in all cases. 152 SmallVector<StringRef, 32> Lines; 153 ProcCpuinfoContent.split(Lines, "\n"); 154 155 // Look for the CPU implementer line. 156 StringRef Implementer; 157 StringRef Hardware; 158 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 159 if (Lines[I].startswith("CPU implementer")) 160 Implementer = Lines[I].substr(15).ltrim("\t :"); 161 if (Lines[I].startswith("Hardware")) 162 Hardware = Lines[I].substr(8).ltrim("\t :"); 163 } 164 165 if (Implementer == "0x41") { // ARM Ltd. 166 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 167 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 168 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 169 return "cortex-a53"; 170 171 172 // Look for the CPU part line. 173 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 174 if (Lines[I].startswith("CPU part")) 175 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 176 // values correspond to the "Part number" in the CP15/c0 register. The 177 // contents are specified in the various processor manuals. 178 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 179 .Case("0x926", "arm926ej-s") 180 .Case("0xb02", "mpcore") 181 .Case("0xb36", "arm1136j-s") 182 .Case("0xb56", "arm1156t2-s") 183 .Case("0xb76", "arm1176jz-s") 184 .Case("0xc08", "cortex-a8") 185 .Case("0xc09", "cortex-a9") 186 .Case("0xc0f", "cortex-a15") 187 .Case("0xc20", "cortex-m0") 188 .Case("0xc23", "cortex-m3") 189 .Case("0xc24", "cortex-m4") 190 .Case("0xd04", "cortex-a35") 191 .Case("0xd03", "cortex-a53") 192 .Case("0xd07", "cortex-a57") 193 .Case("0xd08", "cortex-a72") 194 .Case("0xd09", "cortex-a73") 195 .Case("0xd0a", "cortex-a75") 196 .Case("0xd0b", "cortex-a76") 197 .Default("generic"); 198 } 199 200 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium. 201 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 202 if (Lines[I].startswith("CPU part")) { 203 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 204 .Case("0x516", "thunderx2t99") 205 .Case("0x0516", "thunderx2t99") 206 .Case("0xaf", "thunderx2t99") 207 .Case("0x0af", "thunderx2t99") 208 .Case("0xa1", "thunderxt88") 209 .Case("0x0a1", "thunderxt88") 210 .Default("generic"); 211 } 212 } 213 } 214 215 if (Implementer == "0x48") // HiSilicon Technologies, Inc. 216 // Look for the CPU part line. 217 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 218 if (Lines[I].startswith("CPU part")) 219 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 220 // values correspond to the "Part number" in the CP15/c0 register. The 221 // contents are specified in the various processor manuals. 222 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 223 .Case("0xd01", "tsv110") 224 .Default("generic"); 225 226 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 227 // Look for the CPU part line. 228 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 229 if (Lines[I].startswith("CPU part")) 230 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 231 // values correspond to the "Part number" in the CP15/c0 register. The 232 // contents are specified in the various processor manuals. 233 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 234 .Case("0x06f", "krait") // APQ8064 235 .Case("0x201", "kryo") 236 .Case("0x205", "kryo") 237 .Case("0x211", "kryo") 238 .Case("0x800", "cortex-a73") 239 .Case("0x801", "cortex-a73") 240 .Case("0x802", "cortex-a73") 241 .Case("0x803", "cortex-a73") 242 .Case("0x804", "cortex-a73") 243 .Case("0x805", "cortex-a73") 244 .Case("0xc00", "falkor") 245 .Case("0xc01", "saphira") 246 .Default("generic"); 247 248 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. 249 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow 250 // any predictive pattern across variants and parts. 251 unsigned Variant = 0, Part = 0; 252 253 // Look for the CPU variant line, whose value is a 1 digit hexadecimal 254 // number, corresponding to the Variant bits in the CP15/C0 register. 255 for (auto I : Lines) 256 if (I.consume_front("CPU variant")) 257 I.ltrim("\t :").getAsInteger(0, Variant); 258 259 // Look for the CPU part line, whose value is a 3 digit hexadecimal 260 // number, corresponding to the PartNum bits in the CP15/C0 register. 261 for (auto I : Lines) 262 if (I.consume_front("CPU part")) 263 I.ltrim("\t :").getAsInteger(0, Part); 264 265 unsigned Exynos = (Variant << 12) | Part; 266 switch (Exynos) { 267 default: 268 // Default by falling through to Exynos M3. 269 LLVM_FALLTHROUGH; 270 case 0x1002: 271 return "exynos-m3"; 272 case 0x1003: 273 return "exynos-m4"; 274 } 275 } 276 277 return "generic"; 278 } 279 280 StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { 281 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 282 283 // The "processor 0:" line comes after a fair amount of other information, 284 // including a cache breakdown, but this should be plenty. 285 SmallVector<StringRef, 32> Lines; 286 ProcCpuinfoContent.split(Lines, "\n"); 287 288 // Look for the CPU features. 289 SmallVector<StringRef, 32> CPUFeatures; 290 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 291 if (Lines[I].startswith("features")) { 292 size_t Pos = Lines[I].find(":"); 293 if (Pos != StringRef::npos) { 294 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 295 break; 296 } 297 } 298 299 // We need to check for the presence of vector support independently of 300 // the machine type, since we may only use the vector register set when 301 // supported by the kernel (and hypervisor). 302 bool HaveVectorSupport = false; 303 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 304 if (CPUFeatures[I] == "vx") 305 HaveVectorSupport = true; 306 } 307 308 // Now check the processor machine type. 309 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 310 if (Lines[I].startswith("processor ")) { 311 size_t Pos = Lines[I].find("machine = "); 312 if (Pos != StringRef::npos) { 313 Pos += sizeof("machine = ") - 1; 314 unsigned int Id; 315 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 316 if (Id >= 8561 && HaveVectorSupport) 317 return "z15"; 318 if (Id >= 3906 && HaveVectorSupport) 319 return "z14"; 320 if (Id >= 2964 && HaveVectorSupport) 321 return "z13"; 322 if (Id >= 2827) 323 return "zEC12"; 324 if (Id >= 2817) 325 return "z196"; 326 } 327 } 328 break; 329 } 330 } 331 332 return "generic"; 333 } 334 335 StringRef sys::detail::getHostCPUNameForBPF() { 336 #if !defined(__linux__) || !defined(__x86_64__) 337 return "generic"; 338 #else 339 uint8_t v3_insns[40] __attribute__ ((aligned (8))) = 340 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 341 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 342 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 343 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 344 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 345 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 346 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 347 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 348 /* BPF_EXIT_INSN() */ 349 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 350 351 uint8_t v2_insns[40] __attribute__ ((aligned (8))) = 352 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 353 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 354 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 355 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 356 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 357 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 358 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 359 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 360 /* BPF_EXIT_INSN() */ 361 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 362 363 struct bpf_prog_load_attr { 364 uint32_t prog_type; 365 uint32_t insn_cnt; 366 uint64_t insns; 367 uint64_t license; 368 uint32_t log_level; 369 uint32_t log_size; 370 uint64_t log_buf; 371 uint32_t kern_version; 372 uint32_t prog_flags; 373 } attr = {}; 374 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 375 attr.insn_cnt = 5; 376 attr.insns = (uint64_t)v3_insns; 377 attr.license = (uint64_t)"DUMMY"; 378 379 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, 380 sizeof(attr)); 381 if (fd >= 0) { 382 close(fd); 383 return "v3"; 384 } 385 386 /* Clear the whole attr in case its content changed by syscall. */ 387 memset(&attr, 0, sizeof(attr)); 388 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 389 attr.insn_cnt = 5; 390 attr.insns = (uint64_t)v2_insns; 391 attr.license = (uint64_t)"DUMMY"; 392 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 393 if (fd >= 0) { 394 close(fd); 395 return "v2"; 396 } 397 return "v1"; 398 #endif 399 } 400 401 #if defined(__i386__) || defined(_M_IX86) || \ 402 defined(__x86_64__) || defined(_M_X64) 403 404 enum VendorSignatures { 405 SIG_INTEL = 0x756e6547 /* Genu */, 406 SIG_AMD = 0x68747541 /* Auth */ 407 }; 408 409 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 410 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 411 // support. Consequently, for i386, the presence of CPUID is checked first 412 // via the corresponding eflags bit. 413 // Removal of cpuid.h header motivated by PR30384 414 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 415 // or test-suite, but are used in external projects e.g. libstdcxx 416 static bool isCpuIdSupported() { 417 #if defined(__GNUC__) || defined(__clang__) 418 #if defined(__i386__) 419 int __cpuid_supported; 420 __asm__(" pushfl\n" 421 " popl %%eax\n" 422 " movl %%eax,%%ecx\n" 423 " xorl $0x00200000,%%eax\n" 424 " pushl %%eax\n" 425 " popfl\n" 426 " pushfl\n" 427 " popl %%eax\n" 428 " movl $0,%0\n" 429 " cmpl %%eax,%%ecx\n" 430 " je 1f\n" 431 " movl $1,%0\n" 432 "1:" 433 : "=r"(__cpuid_supported) 434 : 435 : "eax", "ecx"); 436 if (!__cpuid_supported) 437 return false; 438 #endif 439 return true; 440 #endif 441 return true; 442 } 443 444 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 445 /// the specified arguments. If we can't run cpuid on the host, return true. 446 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 447 unsigned *rECX, unsigned *rEDX) { 448 #if defined(__GNUC__) || defined(__clang__) 449 #if defined(__x86_64__) 450 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 451 // FIXME: should we save this for Clang? 452 __asm__("movq\t%%rbx, %%rsi\n\t" 453 "cpuid\n\t" 454 "xchgq\t%%rbx, %%rsi\n\t" 455 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 456 : "a"(value)); 457 return false; 458 #elif defined(__i386__) 459 __asm__("movl\t%%ebx, %%esi\n\t" 460 "cpuid\n\t" 461 "xchgl\t%%ebx, %%esi\n\t" 462 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 463 : "a"(value)); 464 return false; 465 #else 466 return true; 467 #endif 468 #elif defined(_MSC_VER) 469 // The MSVC intrinsic is portable across x86 and x64. 470 int registers[4]; 471 __cpuid(registers, value); 472 *rEAX = registers[0]; 473 *rEBX = registers[1]; 474 *rECX = registers[2]; 475 *rEDX = registers[3]; 476 return false; 477 #else 478 return true; 479 #endif 480 } 481 482 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 483 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 484 /// return true. 485 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 486 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 487 unsigned *rEDX) { 488 #if defined(__GNUC__) || defined(__clang__) 489 #if defined(__x86_64__) 490 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 491 // FIXME: should we save this for Clang? 492 __asm__("movq\t%%rbx, %%rsi\n\t" 493 "cpuid\n\t" 494 "xchgq\t%%rbx, %%rsi\n\t" 495 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 496 : "a"(value), "c"(subleaf)); 497 return false; 498 #elif defined(__i386__) 499 __asm__("movl\t%%ebx, %%esi\n\t" 500 "cpuid\n\t" 501 "xchgl\t%%ebx, %%esi\n\t" 502 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 503 : "a"(value), "c"(subleaf)); 504 return false; 505 #else 506 return true; 507 #endif 508 #elif defined(_MSC_VER) 509 int registers[4]; 510 __cpuidex(registers, value, subleaf); 511 *rEAX = registers[0]; 512 *rEBX = registers[1]; 513 *rECX = registers[2]; 514 *rEDX = registers[3]; 515 return false; 516 #else 517 return true; 518 #endif 519 } 520 521 // Read control register 0 (XCR0). Used to detect features such as AVX. 522 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 523 #if defined(__GNUC__) || defined(__clang__) 524 // Check xgetbv; this uses a .byte sequence instead of the instruction 525 // directly because older assemblers do not include support for xgetbv and 526 // there is no easy way to conditionally compile based on the assembler used. 527 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 528 return false; 529 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 530 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 531 *rEAX = Result; 532 *rEDX = Result >> 32; 533 return false; 534 #else 535 return true; 536 #endif 537 } 538 539 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 540 unsigned *Model) { 541 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 542 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 543 if (*Family == 6 || *Family == 0xf) { 544 if (*Family == 0xf) 545 // Examine extended family ID if family ID is F. 546 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 547 // Examine extended model ID if family ID is 6 or F. 548 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 549 } 550 } 551 552 static void 553 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 554 unsigned Brand_id, unsigned Features, 555 unsigned Features2, unsigned Features3, 556 unsigned *Type, unsigned *Subtype) { 557 if (Brand_id != 0) 558 return; 559 switch (Family) { 560 case 3: 561 *Type = X86::INTEL_i386; 562 break; 563 case 4: 564 *Type = X86::INTEL_i486; 565 break; 566 case 5: 567 if (Features & (1 << X86::FEATURE_MMX)) { 568 *Type = X86::INTEL_PENTIUM_MMX; 569 break; 570 } 571 *Type = X86::INTEL_PENTIUM; 572 break; 573 case 6: 574 switch (Model) { 575 case 0x01: // Pentium Pro processor 576 *Type = X86::INTEL_PENTIUM_PRO; 577 break; 578 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 579 // model 03 580 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 581 // model 05, and Intel Celeron processor, model 05 582 case 0x06: // Celeron processor, model 06 583 *Type = X86::INTEL_PENTIUM_II; 584 break; 585 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 586 // processor, model 07 587 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 588 // model 08, and Celeron processor, model 08 589 case 0x0a: // Pentium III Xeon processor, model 0Ah 590 case 0x0b: // Pentium III processor, model 0Bh 591 *Type = X86::INTEL_PENTIUM_III; 592 break; 593 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 594 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 595 // 0Dh. All processors are manufactured using the 90 nm process. 596 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 597 // Integrated Processor with Intel QuickAssist Technology 598 *Type = X86::INTEL_PENTIUM_M; 599 break; 600 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 601 // 0Eh. All processors are manufactured using the 65 nm process. 602 *Type = X86::INTEL_CORE_DUO; 603 break; // yonah 604 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 605 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 606 // mobile processor, Intel Core 2 Extreme processor, Intel 607 // Pentium Dual-Core processor, Intel Xeon processor, model 608 // 0Fh. All processors are manufactured using the 65 nm process. 609 case 0x16: // Intel Celeron processor model 16h. All processors are 610 // manufactured using the 65 nm process 611 *Type = X86::INTEL_CORE2; // "core2" 612 *Subtype = X86::INTEL_CORE2_65; 613 break; 614 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 615 // 17h. All processors are manufactured using the 45 nm process. 616 // 617 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 618 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 619 // the 45 nm process. 620 *Type = X86::INTEL_CORE2; // "penryn" 621 *Subtype = X86::INTEL_CORE2_45; 622 break; 623 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 624 // processors are manufactured using the 45 nm process. 625 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 626 // As found in a Summer 2010 model iMac. 627 case 0x1f: 628 case 0x2e: // Nehalem EX 629 *Type = X86::INTEL_COREI7; // "nehalem" 630 *Subtype = X86::INTEL_COREI7_NEHALEM; 631 break; 632 case 0x25: // Intel Core i7, laptop version. 633 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 634 // processors are manufactured using the 32 nm process. 635 case 0x2f: // Westmere EX 636 *Type = X86::INTEL_COREI7; // "westmere" 637 *Subtype = X86::INTEL_COREI7_WESTMERE; 638 break; 639 case 0x2a: // Intel Core i7 processor. All processors are manufactured 640 // using the 32 nm process. 641 case 0x2d: 642 *Type = X86::INTEL_COREI7; //"sandybridge" 643 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 644 break; 645 case 0x3a: 646 case 0x3e: // Ivy Bridge EP 647 *Type = X86::INTEL_COREI7; // "ivybridge" 648 *Subtype = X86::INTEL_COREI7_IVYBRIDGE; 649 break; 650 651 // Haswell: 652 case 0x3c: 653 case 0x3f: 654 case 0x45: 655 case 0x46: 656 *Type = X86::INTEL_COREI7; // "haswell" 657 *Subtype = X86::INTEL_COREI7_HASWELL; 658 break; 659 660 // Broadwell: 661 case 0x3d: 662 case 0x47: 663 case 0x4f: 664 case 0x56: 665 *Type = X86::INTEL_COREI7; // "broadwell" 666 *Subtype = X86::INTEL_COREI7_BROADWELL; 667 break; 668 669 // Skylake: 670 case 0x4e: // Skylake mobile 671 case 0x5e: // Skylake desktop 672 case 0x8e: // Kaby Lake mobile 673 case 0x9e: // Kaby Lake desktop 674 *Type = X86::INTEL_COREI7; // "skylake" 675 *Subtype = X86::INTEL_COREI7_SKYLAKE; 676 break; 677 678 // Skylake Xeon: 679 case 0x55: 680 *Type = X86::INTEL_COREI7; 681 if (Features2 & (1 << (X86::FEATURE_AVX512BF16 - 32))) 682 *Subtype = X86::INTEL_COREI7_COOPERLAKE; // "cooperlake" 683 else if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) 684 *Subtype = X86::INTEL_COREI7_CASCADELAKE; // "cascadelake" 685 else 686 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 687 break; 688 689 // Cannonlake: 690 case 0x66: 691 *Type = X86::INTEL_COREI7; 692 *Subtype = X86::INTEL_COREI7_CANNONLAKE; // "cannonlake" 693 break; 694 695 // Icelake: 696 case 0x7d: 697 case 0x7e: 698 *Type = X86::INTEL_COREI7; 699 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; // "icelake-client" 700 break; 701 702 // Icelake Xeon: 703 case 0x6a: 704 case 0x6c: 705 *Type = X86::INTEL_COREI7; 706 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; // "icelake-server" 707 break; 708 709 case 0x1c: // Most 45 nm Intel Atom processors 710 case 0x26: // 45 nm Atom Lincroft 711 case 0x27: // 32 nm Atom Medfield 712 case 0x35: // 32 nm Atom Midview 713 case 0x36: // 32 nm Atom Midview 714 *Type = X86::INTEL_BONNELL; 715 break; // "bonnell" 716 717 // Atom Silvermont codes from the Intel software optimization guide. 718 case 0x37: 719 case 0x4a: 720 case 0x4d: 721 case 0x5a: 722 case 0x5d: 723 case 0x4c: // really airmont 724 *Type = X86::INTEL_SILVERMONT; 725 break; // "silvermont" 726 // Goldmont: 727 case 0x5c: // Apollo Lake 728 case 0x5f: // Denverton 729 *Type = X86::INTEL_GOLDMONT; 730 break; // "goldmont" 731 case 0x7a: 732 *Type = X86::INTEL_GOLDMONT_PLUS; 733 break; 734 case 0x86: 735 *Type = X86::INTEL_TREMONT; 736 break; 737 738 case 0x57: 739 *Type = X86::INTEL_KNL; // knl 740 break; 741 742 case 0x85: 743 *Type = X86::INTEL_KNM; // knm 744 break; 745 746 default: // Unknown family 6 CPU, try to guess. 747 // TODO detect tigerlake host 748 if (Features3 & (1 << (X86::FEATURE_AVX512VP2INTERSECT - 64))) { 749 *Type = X86::INTEL_COREI7; 750 *Subtype = X86::INTEL_COREI7_TIGERLAKE; 751 break; 752 } 753 754 if (Features & (1 << X86::FEATURE_AVX512VBMI2)) { 755 *Type = X86::INTEL_COREI7; 756 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; 757 break; 758 } 759 760 if (Features & (1 << X86::FEATURE_AVX512VBMI)) { 761 *Type = X86::INTEL_COREI7; 762 *Subtype = X86::INTEL_COREI7_CANNONLAKE; 763 break; 764 } 765 766 if (Features2 & (1 << (X86::FEATURE_AVX512BF16 - 32))) { 767 *Type = X86::INTEL_COREI7; 768 *Subtype = X86::INTEL_COREI7_COOPERLAKE; 769 break; 770 } 771 772 if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) { 773 *Type = X86::INTEL_COREI7; 774 *Subtype = X86::INTEL_COREI7_CASCADELAKE; 775 break; 776 } 777 778 if (Features & (1 << X86::FEATURE_AVX512VL)) { 779 *Type = X86::INTEL_COREI7; 780 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; 781 break; 782 } 783 784 if (Features & (1 << X86::FEATURE_AVX512ER)) { 785 *Type = X86::INTEL_KNL; // knl 786 break; 787 } 788 789 if (Features3 & (1 << (X86::FEATURE_CLFLUSHOPT - 64))) { 790 if (Features3 & (1 << (X86::FEATURE_SHA - 64))) { 791 *Type = X86::INTEL_GOLDMONT; 792 } else { 793 *Type = X86::INTEL_COREI7; 794 *Subtype = X86::INTEL_COREI7_SKYLAKE; 795 } 796 break; 797 } 798 if (Features3 & (1 << (X86::FEATURE_ADX - 64))) { 799 *Type = X86::INTEL_COREI7; 800 *Subtype = X86::INTEL_COREI7_BROADWELL; 801 break; 802 } 803 if (Features & (1 << X86::FEATURE_AVX2)) { 804 *Type = X86::INTEL_COREI7; 805 *Subtype = X86::INTEL_COREI7_HASWELL; 806 break; 807 } 808 if (Features & (1 << X86::FEATURE_AVX)) { 809 *Type = X86::INTEL_COREI7; 810 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 811 break; 812 } 813 if (Features & (1 << X86::FEATURE_SSE4_2)) { 814 if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { 815 *Type = X86::INTEL_SILVERMONT; 816 } else { 817 *Type = X86::INTEL_COREI7; 818 *Subtype = X86::INTEL_COREI7_NEHALEM; 819 } 820 break; 821 } 822 if (Features & (1 << X86::FEATURE_SSE4_1)) { 823 *Type = X86::INTEL_CORE2; // "penryn" 824 *Subtype = X86::INTEL_CORE2_45; 825 break; 826 } 827 if (Features & (1 << X86::FEATURE_SSSE3)) { 828 if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { 829 *Type = X86::INTEL_BONNELL; // "bonnell" 830 } else { 831 *Type = X86::INTEL_CORE2; // "core2" 832 *Subtype = X86::INTEL_CORE2_65; 833 } 834 break; 835 } 836 if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { 837 *Type = X86::INTEL_CORE2; // "core2" 838 *Subtype = X86::INTEL_CORE2_65; 839 break; 840 } 841 if (Features & (1 << X86::FEATURE_SSE3)) { 842 *Type = X86::INTEL_CORE_DUO; 843 break; 844 } 845 if (Features & (1 << X86::FEATURE_SSE2)) { 846 *Type = X86::INTEL_PENTIUM_M; 847 break; 848 } 849 if (Features & (1 << X86::FEATURE_SSE)) { 850 *Type = X86::INTEL_PENTIUM_III; 851 break; 852 } 853 if (Features & (1 << X86::FEATURE_MMX)) { 854 *Type = X86::INTEL_PENTIUM_II; 855 break; 856 } 857 *Type = X86::INTEL_PENTIUM_PRO; 858 break; 859 } 860 break; 861 case 15: { 862 if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { 863 *Type = X86::INTEL_NOCONA; 864 break; 865 } 866 if (Features & (1 << X86::FEATURE_SSE3)) { 867 *Type = X86::INTEL_PRESCOTT; 868 break; 869 } 870 *Type = X86::INTEL_PENTIUM_IV; 871 break; 872 } 873 default: 874 break; /*"generic"*/ 875 } 876 } 877 878 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 879 unsigned Features, unsigned *Type, 880 unsigned *Subtype) { 881 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 882 // appears to be no way to generate the wide variety of AMD-specific targets 883 // from the information returned from CPUID. 884 switch (Family) { 885 case 4: 886 *Type = X86::AMD_i486; 887 break; 888 case 5: 889 *Type = X86::AMDPENTIUM; 890 switch (Model) { 891 case 6: 892 case 7: 893 *Subtype = X86::AMDPENTIUM_K6; 894 break; // "k6" 895 case 8: 896 *Subtype = X86::AMDPENTIUM_K62; 897 break; // "k6-2" 898 case 9: 899 case 13: 900 *Subtype = X86::AMDPENTIUM_K63; 901 break; // "k6-3" 902 case 10: 903 *Subtype = X86::AMDPENTIUM_GEODE; 904 break; // "geode" 905 } 906 break; 907 case 6: 908 if (Features & (1 << X86::FEATURE_SSE)) { 909 *Type = X86::AMD_ATHLON_XP; 910 break; // "athlon-xp" 911 } 912 *Type = X86::AMD_ATHLON; 913 break; // "athlon" 914 case 15: 915 if (Features & (1 << X86::FEATURE_SSE3)) { 916 *Type = X86::AMD_K8SSE3; 917 break; // "k8-sse3" 918 } 919 *Type = X86::AMD_K8; 920 break; // "k8" 921 case 16: 922 *Type = X86::AMDFAM10H; // "amdfam10" 923 switch (Model) { 924 case 2: 925 *Subtype = X86::AMDFAM10H_BARCELONA; 926 break; 927 case 4: 928 *Subtype = X86::AMDFAM10H_SHANGHAI; 929 break; 930 case 8: 931 *Subtype = X86::AMDFAM10H_ISTANBUL; 932 break; 933 } 934 break; 935 case 20: 936 *Type = X86::AMD_BTVER1; 937 break; // "btver1"; 938 case 21: 939 *Type = X86::AMDFAM15H; 940 if (Model >= 0x60 && Model <= 0x7f) { 941 *Subtype = X86::AMDFAM15H_BDVER4; 942 break; // "bdver4"; 60h-7Fh: Excavator 943 } 944 if (Model >= 0x30 && Model <= 0x3f) { 945 *Subtype = X86::AMDFAM15H_BDVER3; 946 break; // "bdver3"; 30h-3Fh: Steamroller 947 } 948 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) { 949 *Subtype = X86::AMDFAM15H_BDVER2; 950 break; // "bdver2"; 02h, 10h-1Fh: Piledriver 951 } 952 if (Model <= 0x0f) { 953 *Subtype = X86::AMDFAM15H_BDVER1; 954 break; // "bdver1"; 00h-0Fh: Bulldozer 955 } 956 break; 957 case 22: 958 *Type = X86::AMD_BTVER2; 959 break; // "btver2" 960 case 23: 961 *Type = X86::AMDFAM17H; 962 if (Model >= 0x30 && Model <= 0x3f) { 963 *Subtype = X86::AMDFAM17H_ZNVER2; 964 break; // "znver2"; 30h-3fh: Zen2 965 } 966 if (Model <= 0x0f) { 967 *Subtype = X86::AMDFAM17H_ZNVER1; 968 break; // "znver1"; 00h-0Fh: Zen1 969 } 970 break; 971 default: 972 break; // "generic" 973 } 974 } 975 976 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 977 unsigned *FeaturesOut, unsigned *Features2Out, 978 unsigned *Features3Out) { 979 unsigned Features = 0; 980 unsigned Features2 = 0; 981 unsigned Features3 = 0; 982 unsigned EAX, EBX; 983 984 auto setFeature = [&](unsigned F) { 985 if (F < 32) 986 Features |= 1U << (F & 0x1f); 987 else if (F < 64) 988 Features2 |= 1U << ((F - 32) & 0x1f); 989 else if (F < 96) 990 Features3 |= 1U << ((F - 64) & 0x1f); 991 else 992 llvm_unreachable("Unexpected FeatureBit"); 993 }; 994 995 if ((EDX >> 15) & 1) 996 setFeature(X86::FEATURE_CMOV); 997 if ((EDX >> 23) & 1) 998 setFeature(X86::FEATURE_MMX); 999 if ((EDX >> 25) & 1) 1000 setFeature(X86::FEATURE_SSE); 1001 if ((EDX >> 26) & 1) 1002 setFeature(X86::FEATURE_SSE2); 1003 1004 if ((ECX >> 0) & 1) 1005 setFeature(X86::FEATURE_SSE3); 1006 if ((ECX >> 1) & 1) 1007 setFeature(X86::FEATURE_PCLMUL); 1008 if ((ECX >> 9) & 1) 1009 setFeature(X86::FEATURE_SSSE3); 1010 if ((ECX >> 12) & 1) 1011 setFeature(X86::FEATURE_FMA); 1012 if ((ECX >> 19) & 1) 1013 setFeature(X86::FEATURE_SSE4_1); 1014 if ((ECX >> 20) & 1) 1015 setFeature(X86::FEATURE_SSE4_2); 1016 if ((ECX >> 23) & 1) 1017 setFeature(X86::FEATURE_POPCNT); 1018 if ((ECX >> 25) & 1) 1019 setFeature(X86::FEATURE_AES); 1020 1021 if ((ECX >> 22) & 1) 1022 setFeature(X86::FEATURE_MOVBE); 1023 1024 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1025 // indicates that the AVX registers will be saved and restored on context 1026 // switch, then we have full AVX support. 1027 const unsigned AVXBits = (1 << 27) | (1 << 28); 1028 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 1029 ((EAX & 0x6) == 0x6); 1030 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 1031 1032 if (HasAVX) 1033 setFeature(X86::FEATURE_AVX); 1034 1035 bool HasLeaf7 = 1036 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1037 1038 if (HasLeaf7 && ((EBX >> 3) & 1)) 1039 setFeature(X86::FEATURE_BMI); 1040 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 1041 setFeature(X86::FEATURE_AVX2); 1042 if (HasLeaf7 && ((EBX >> 8) & 1)) 1043 setFeature(X86::FEATURE_BMI2); 1044 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 1045 setFeature(X86::FEATURE_AVX512F); 1046 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 1047 setFeature(X86::FEATURE_AVX512DQ); 1048 if (HasLeaf7 && ((EBX >> 19) & 1)) 1049 setFeature(X86::FEATURE_ADX); 1050 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 1051 setFeature(X86::FEATURE_AVX512IFMA); 1052 if (HasLeaf7 && ((EBX >> 23) & 1)) 1053 setFeature(X86::FEATURE_CLFLUSHOPT); 1054 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 1055 setFeature(X86::FEATURE_AVX512PF); 1056 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 1057 setFeature(X86::FEATURE_AVX512ER); 1058 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 1059 setFeature(X86::FEATURE_AVX512CD); 1060 if (HasLeaf7 && ((EBX >> 29) & 1)) 1061 setFeature(X86::FEATURE_SHA); 1062 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 1063 setFeature(X86::FEATURE_AVX512BW); 1064 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 1065 setFeature(X86::FEATURE_AVX512VL); 1066 1067 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 1068 setFeature(X86::FEATURE_AVX512VBMI); 1069 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save) 1070 setFeature(X86::FEATURE_AVX512VBMI2); 1071 if (HasLeaf7 && ((ECX >> 8) & 1)) 1072 setFeature(X86::FEATURE_GFNI); 1073 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX) 1074 setFeature(X86::FEATURE_VPCLMULQDQ); 1075 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save) 1076 setFeature(X86::FEATURE_AVX512VNNI); 1077 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save) 1078 setFeature(X86::FEATURE_AVX512BITALG); 1079 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1080 setFeature(X86::FEATURE_AVX512VPOPCNTDQ); 1081 1082 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1083 setFeature(X86::FEATURE_AVX5124VNNIW); 1084 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1085 setFeature(X86::FEATURE_AVX5124FMAPS); 1086 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save) 1087 setFeature(X86::FEATURE_AVX512VP2INTERSECT); 1088 1089 bool HasLeaf7Subleaf1 = 1090 MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1091 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save) 1092 setFeature(X86::FEATURE_AVX512BF16); 1093 1094 unsigned MaxExtLevel; 1095 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1096 1097 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1098 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1099 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1100 setFeature(X86::FEATURE_SSE4_A); 1101 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1102 setFeature(X86::FEATURE_XOP); 1103 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1104 setFeature(X86::FEATURE_FMA4); 1105 1106 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1107 setFeature(X86::FEATURE_EM64T); 1108 1109 *FeaturesOut = Features; 1110 *Features2Out = Features2; 1111 *Features3Out = Features3; 1112 } 1113 1114 StringRef sys::getHostCPUName() { 1115 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1116 unsigned MaxLeaf, Vendor; 1117 1118 #if defined(__GNUC__) || defined(__clang__) 1119 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here 1120 // and simplify it to not invoke __cpuid (like cpu_model.c in 1121 // compiler-rt/lib/builtins/cpu_model.c? 1122 // Opting for the second option. 1123 if(!isCpuIdSupported()) 1124 return "generic"; 1125 #endif 1126 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) 1127 return "generic"; 1128 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1129 1130 unsigned Brand_id = EBX & 0xff; 1131 unsigned Family = 0, Model = 0; 1132 unsigned Features = 0, Features2 = 0, Features3 = 0; 1133 detectX86FamilyModel(EAX, &Family, &Model); 1134 getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2, &Features3); 1135 1136 unsigned Type = 0; 1137 unsigned Subtype = 0; 1138 1139 if (Vendor == SIG_INTEL) { 1140 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, 1141 Features2, Features3, &Type, &Subtype); 1142 } else if (Vendor == SIG_AMD) { 1143 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1144 } 1145 1146 // Check subtypes first since those are more specific. 1147 #define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \ 1148 if (Subtype == X86::ENUM) \ 1149 return ARCHNAME; 1150 #include "llvm/Support/X86TargetParser.def" 1151 1152 // Now check types. 1153 #define X86_CPU_TYPE(ARCHNAME, ENUM) \ 1154 if (Type == X86::ENUM) \ 1155 return ARCHNAME; 1156 #include "llvm/Support/X86TargetParser.def" 1157 1158 return "generic"; 1159 } 1160 1161 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1162 StringRef sys::getHostCPUName() { 1163 host_basic_info_data_t hostInfo; 1164 mach_msg_type_number_t infoCount; 1165 1166 infoCount = HOST_BASIC_INFO_COUNT; 1167 mach_port_t hostPort = mach_host_self(); 1168 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1169 &infoCount); 1170 mach_port_deallocate(mach_task_self(), hostPort); 1171 1172 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1173 return "generic"; 1174 1175 switch (hostInfo.cpu_subtype) { 1176 case CPU_SUBTYPE_POWERPC_601: 1177 return "601"; 1178 case CPU_SUBTYPE_POWERPC_602: 1179 return "602"; 1180 case CPU_SUBTYPE_POWERPC_603: 1181 return "603"; 1182 case CPU_SUBTYPE_POWERPC_603e: 1183 return "603e"; 1184 case CPU_SUBTYPE_POWERPC_603ev: 1185 return "603ev"; 1186 case CPU_SUBTYPE_POWERPC_604: 1187 return "604"; 1188 case CPU_SUBTYPE_POWERPC_604e: 1189 return "604e"; 1190 case CPU_SUBTYPE_POWERPC_620: 1191 return "620"; 1192 case CPU_SUBTYPE_POWERPC_750: 1193 return "750"; 1194 case CPU_SUBTYPE_POWERPC_7400: 1195 return "7400"; 1196 case CPU_SUBTYPE_POWERPC_7450: 1197 return "7450"; 1198 case CPU_SUBTYPE_POWERPC_970: 1199 return "970"; 1200 default:; 1201 } 1202 1203 return "generic"; 1204 } 1205 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1206 StringRef sys::getHostCPUName() { 1207 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1208 StringRef Content = P ? P->getBuffer() : ""; 1209 return detail::getHostCPUNameForPowerPC(Content); 1210 } 1211 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1212 StringRef sys::getHostCPUName() { 1213 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1214 StringRef Content = P ? P->getBuffer() : ""; 1215 return detail::getHostCPUNameForARM(Content); 1216 } 1217 #elif defined(__linux__) && defined(__s390x__) 1218 StringRef sys::getHostCPUName() { 1219 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1220 StringRef Content = P ? P->getBuffer() : ""; 1221 return detail::getHostCPUNameForS390x(Content); 1222 } 1223 #else 1224 StringRef sys::getHostCPUName() { return "generic"; } 1225 #endif 1226 1227 #if defined(__linux__) && defined(__x86_64__) 1228 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1229 // using the number of unique physical/core id pairs. The following 1230 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1231 static int computeHostNumPhysicalCores() { 1232 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1233 // mmapped because it appears to have 0 size. 1234 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1235 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1236 if (std::error_code EC = Text.getError()) { 1237 llvm::errs() << "Can't read " 1238 << "/proc/cpuinfo: " << EC.message() << "\n"; 1239 return -1; 1240 } 1241 SmallVector<StringRef, 8> strs; 1242 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1243 /*KeepEmpty=*/false); 1244 int CurPhysicalId = -1; 1245 int CurCoreId = -1; 1246 SmallSet<std::pair<int, int>, 32> UniqueItems; 1247 for (auto &Line : strs) { 1248 Line = Line.trim(); 1249 if (!Line.startswith("physical id") && !Line.startswith("core id")) 1250 continue; 1251 std::pair<StringRef, StringRef> Data = Line.split(':'); 1252 auto Name = Data.first.trim(); 1253 auto Val = Data.second.trim(); 1254 if (Name == "physical id") { 1255 assert(CurPhysicalId == -1 && 1256 "Expected a core id before seeing another physical id"); 1257 Val.getAsInteger(10, CurPhysicalId); 1258 } 1259 if (Name == "core id") { 1260 assert(CurCoreId == -1 && 1261 "Expected a physical id before seeing another core id"); 1262 Val.getAsInteger(10, CurCoreId); 1263 } 1264 if (CurPhysicalId != -1 && CurCoreId != -1) { 1265 UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId)); 1266 CurPhysicalId = -1; 1267 CurCoreId = -1; 1268 } 1269 } 1270 return UniqueItems.size(); 1271 } 1272 #elif defined(__APPLE__) && defined(__x86_64__) 1273 #include <sys/param.h> 1274 #include <sys/sysctl.h> 1275 1276 // Gets the number of *physical cores* on the machine. 1277 static int computeHostNumPhysicalCores() { 1278 uint32_t count; 1279 size_t len = sizeof(count); 1280 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1281 if (count < 1) { 1282 int nm[2]; 1283 nm[0] = CTL_HW; 1284 nm[1] = HW_AVAILCPU; 1285 sysctl(nm, 2, &count, &len, NULL, 0); 1286 if (count < 1) 1287 return -1; 1288 } 1289 return count; 1290 } 1291 #else 1292 // On other systems, return -1 to indicate unknown. 1293 static int computeHostNumPhysicalCores() { return -1; } 1294 #endif 1295 1296 int sys::getHostNumPhysicalCores() { 1297 static int NumCores = computeHostNumPhysicalCores(); 1298 return NumCores; 1299 } 1300 1301 #if defined(__i386__) || defined(_M_IX86) || \ 1302 defined(__x86_64__) || defined(_M_X64) 1303 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1304 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1305 unsigned MaxLevel; 1306 union { 1307 unsigned u[3]; 1308 char c[12]; 1309 } text; 1310 1311 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1312 MaxLevel < 1) 1313 return false; 1314 1315 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1316 1317 Features["cx8"] = (EDX >> 8) & 1; 1318 Features["cmov"] = (EDX >> 15) & 1; 1319 Features["mmx"] = (EDX >> 23) & 1; 1320 Features["fxsr"] = (EDX >> 24) & 1; 1321 Features["sse"] = (EDX >> 25) & 1; 1322 Features["sse2"] = (EDX >> 26) & 1; 1323 1324 Features["sse3"] = (ECX >> 0) & 1; 1325 Features["pclmul"] = (ECX >> 1) & 1; 1326 Features["ssse3"] = (ECX >> 9) & 1; 1327 Features["cx16"] = (ECX >> 13) & 1; 1328 Features["sse4.1"] = (ECX >> 19) & 1; 1329 Features["sse4.2"] = (ECX >> 20) & 1; 1330 Features["movbe"] = (ECX >> 22) & 1; 1331 Features["popcnt"] = (ECX >> 23) & 1; 1332 Features["aes"] = (ECX >> 25) & 1; 1333 Features["rdrnd"] = (ECX >> 30) & 1; 1334 1335 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1336 // indicates that the AVX registers will be saved and restored on context 1337 // switch, then we have full AVX support. 1338 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1339 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1340 // AVX512 requires additional context to be saved by the OS. 1341 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1342 1343 Features["avx"] = HasAVXSave; 1344 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave; 1345 // Only enable XSAVE if OS has enabled support for saving YMM state. 1346 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave; 1347 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave; 1348 1349 unsigned MaxExtLevel; 1350 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1351 1352 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1353 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1354 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1); 1355 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1356 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1357 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1358 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1359 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1360 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1361 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1362 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1363 1364 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1); 1365 1366 // Miscellaneous memory related features, detected by 1367 // using the 0x80000008 leaf of the CPUID instruction 1368 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1369 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX); 1370 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1371 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1); 1372 1373 bool HasLeaf7 = 1374 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1375 1376 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1377 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1378 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1379 // AVX2 is only supported if we have the OS save support from AVX. 1380 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave; 1381 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1382 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1383 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1384 // AVX512 is only supported if the OS supports the context save for it. 1385 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1386 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1387 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1388 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1389 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1390 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1391 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1392 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1393 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1394 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1395 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1396 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1397 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1398 1399 Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1); 1400 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1401 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1402 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1); 1403 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save; 1404 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1); 1405 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1); 1406 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave; 1407 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave; 1408 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save; 1409 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save; 1410 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1411 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1); 1412 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1); 1413 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1); 1414 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1); 1415 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1); 1416 1417 // There are two CPUID leafs which information associated with the pconfig 1418 // instruction: 1419 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th 1420 // bit of EDX), while the EAX=0x1b leaf returns information on the 1421 // availability of specific pconfig leafs. 1422 // The target feature here only refers to the the first of these two. 1423 // Users might need to check for the availability of specific pconfig 1424 // leaves using cpuid, since that information is ignored while 1425 // detecting features using the "-march=native" flag. 1426 // For more info, see X86 ISA docs. 1427 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1); 1428 bool HasLeaf7Subleaf1 = 1429 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1430 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save; 1431 1432 bool HasLeafD = MaxLevel >= 0xd && 1433 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1434 1435 // Only enable XSAVE if OS has enabled support for saving YMM state. 1436 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave; 1437 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave; 1438 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave; 1439 1440 bool HasLeaf14 = MaxLevel >= 0x14 && 1441 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX); 1442 1443 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1); 1444 1445 return true; 1446 } 1447 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1448 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1449 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1450 if (!P) 1451 return false; 1452 1453 SmallVector<StringRef, 32> Lines; 1454 P->getBuffer().split(Lines, "\n"); 1455 1456 SmallVector<StringRef, 32> CPUFeatures; 1457 1458 // Look for the CPU features. 1459 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1460 if (Lines[I].startswith("Features")) { 1461 Lines[I].split(CPUFeatures, ' '); 1462 break; 1463 } 1464 1465 #if defined(__aarch64__) 1466 // Keep track of which crypto features we have seen 1467 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1468 uint32_t crypto = 0; 1469 #endif 1470 1471 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1472 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1473 #if defined(__aarch64__) 1474 .Case("asimd", "neon") 1475 .Case("fp", "fp-armv8") 1476 .Case("crc32", "crc") 1477 #else 1478 .Case("half", "fp16") 1479 .Case("neon", "neon") 1480 .Case("vfpv3", "vfp3") 1481 .Case("vfpv3d16", "d16") 1482 .Case("vfpv4", "vfp4") 1483 .Case("idiva", "hwdiv-arm") 1484 .Case("idivt", "hwdiv") 1485 #endif 1486 .Default(""); 1487 1488 #if defined(__aarch64__) 1489 // We need to check crypto separately since we need all of the crypto 1490 // extensions to enable the subtarget feature 1491 if (CPUFeatures[I] == "aes") 1492 crypto |= CAP_AES; 1493 else if (CPUFeatures[I] == "pmull") 1494 crypto |= CAP_PMULL; 1495 else if (CPUFeatures[I] == "sha1") 1496 crypto |= CAP_SHA1; 1497 else if (CPUFeatures[I] == "sha2") 1498 crypto |= CAP_SHA2; 1499 #endif 1500 1501 if (LLVMFeatureStr != "") 1502 Features[LLVMFeatureStr] = true; 1503 } 1504 1505 #if defined(__aarch64__) 1506 // If we have all crypto bits we can add the feature 1507 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1508 Features["crypto"] = true; 1509 #endif 1510 1511 return true; 1512 } 1513 #elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64)) 1514 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1515 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE)) 1516 Features["neon"] = true; 1517 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE)) 1518 Features["crc"] = true; 1519 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) 1520 Features["crypto"] = true; 1521 1522 return true; 1523 } 1524 #else 1525 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1526 #endif 1527 1528 std::string sys::getProcessTriple() { 1529 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1530 Triple PT(Triple::normalize(TargetTripleString)); 1531 1532 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1533 PT = PT.get64BitArchVariant(); 1534 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1535 PT = PT.get32BitArchVariant(); 1536 1537 return PT.str(); 1538 } 1539