1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the operating system Host concept. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/Host.h" 14 #include "llvm/ADT/SmallSet.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringMap.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/llvm-config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/X86TargetParser.h" 25 #include "llvm/Support/raw_ostream.h" 26 #include <assert.h> 27 #include <string.h> 28 29 // Include the platform-specific parts of this class. 30 #ifdef LLVM_ON_UNIX 31 #include "Unix/Host.inc" 32 #include <sched.h> 33 #endif 34 #ifdef _WIN32 35 #include "Windows/Host.inc" 36 #endif 37 #ifdef _MSC_VER 38 #include <intrin.h> 39 #endif 40 #if defined(__APPLE__) && (!defined(__x86_64__)) 41 #include <mach/host_info.h> 42 #include <mach/mach.h> 43 #include <mach/mach_host.h> 44 #include <mach/machine.h> 45 #endif 46 47 #define DEBUG_TYPE "host-detection" 48 49 //===----------------------------------------------------------------------===// 50 // 51 // Implementations of the CPU detection routines 52 // 53 //===----------------------------------------------------------------------===// 54 55 using namespace llvm; 56 57 static std::unique_ptr<llvm::MemoryBuffer> 58 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 59 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 60 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 61 if (std::error_code EC = Text.getError()) { 62 llvm::errs() << "Can't read " 63 << "/proc/cpuinfo: " << EC.message() << "\n"; 64 return nullptr; 65 } 66 return std::move(*Text); 67 } 68 69 StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) { 70 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 71 // and so we must use an operating-system interface to determine the current 72 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 73 const char *generic = "generic"; 74 75 // The cpu line is second (after the 'processor: 0' line), so if this 76 // buffer is too small then something has changed (or is wrong). 77 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 78 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 79 80 StringRef::const_iterator CIP = CPUInfoStart; 81 82 StringRef::const_iterator CPUStart = 0; 83 size_t CPULen = 0; 84 85 // We need to find the first line which starts with cpu, spaces, and a colon. 86 // After the colon, there may be some additional spaces and then the cpu type. 87 while (CIP < CPUInfoEnd && CPUStart == 0) { 88 if (CIP < CPUInfoEnd && *CIP == '\n') 89 ++CIP; 90 91 if (CIP < CPUInfoEnd && *CIP == 'c') { 92 ++CIP; 93 if (CIP < CPUInfoEnd && *CIP == 'p') { 94 ++CIP; 95 if (CIP < CPUInfoEnd && *CIP == 'u') { 96 ++CIP; 97 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 98 ++CIP; 99 100 if (CIP < CPUInfoEnd && *CIP == ':') { 101 ++CIP; 102 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 103 ++CIP; 104 105 if (CIP < CPUInfoEnd) { 106 CPUStart = CIP; 107 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 108 *CIP != ',' && *CIP != '\n')) 109 ++CIP; 110 CPULen = CIP - CPUStart; 111 } 112 } 113 } 114 } 115 } 116 117 if (CPUStart == 0) 118 while (CIP < CPUInfoEnd && *CIP != '\n') 119 ++CIP; 120 } 121 122 if (CPUStart == 0) 123 return generic; 124 125 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 126 .Case("604e", "604e") 127 .Case("604", "604") 128 .Case("7400", "7400") 129 .Case("7410", "7400") 130 .Case("7447", "7400") 131 .Case("7455", "7450") 132 .Case("G4", "g4") 133 .Case("POWER4", "970") 134 .Case("PPC970FX", "970") 135 .Case("PPC970MP", "970") 136 .Case("G5", "g5") 137 .Case("POWER5", "g5") 138 .Case("A2", "a2") 139 .Case("POWER6", "pwr6") 140 .Case("POWER7", "pwr7") 141 .Case("POWER8", "pwr8") 142 .Case("POWER8E", "pwr8") 143 .Case("POWER8NVL", "pwr8") 144 .Case("POWER9", "pwr9") 145 .Case("POWER10", "pwr10") 146 // FIXME: If we get a simulator or machine with the capabilities of 147 // mcpu=future, we should revisit this and add the name reported by the 148 // simulator/machine. 149 .Default(generic); 150 } 151 152 StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { 153 // The cpuid register on arm is not accessible from user space. On Linux, 154 // it is exposed through the /proc/cpuinfo file. 155 156 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 157 // in all cases. 158 SmallVector<StringRef, 32> Lines; 159 ProcCpuinfoContent.split(Lines, "\n"); 160 161 // Look for the CPU implementer line. 162 StringRef Implementer; 163 StringRef Hardware; 164 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 165 if (Lines[I].startswith("CPU implementer")) 166 Implementer = Lines[I].substr(15).ltrim("\t :"); 167 if (Lines[I].startswith("Hardware")) 168 Hardware = Lines[I].substr(8).ltrim("\t :"); 169 } 170 171 if (Implementer == "0x41") { // ARM Ltd. 172 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 173 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 174 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 175 return "cortex-a53"; 176 177 178 // Look for the CPU part line. 179 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 180 if (Lines[I].startswith("CPU part")) 181 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 182 // values correspond to the "Part number" in the CP15/c0 register. The 183 // contents are specified in the various processor manuals. 184 // This corresponds to the Main ID Register in Technical Reference Manuals. 185 // and is used in programs like sys-utils 186 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 187 .Case("0x926", "arm926ej-s") 188 .Case("0xb02", "mpcore") 189 .Case("0xb36", "arm1136j-s") 190 .Case("0xb56", "arm1156t2-s") 191 .Case("0xb76", "arm1176jz-s") 192 .Case("0xc08", "cortex-a8") 193 .Case("0xc09", "cortex-a9") 194 .Case("0xc0f", "cortex-a15") 195 .Case("0xc20", "cortex-m0") 196 .Case("0xc23", "cortex-m3") 197 .Case("0xc24", "cortex-m4") 198 .Case("0xd22", "cortex-m55") 199 .Case("0xd02", "cortex-a34") 200 .Case("0xd04", "cortex-a35") 201 .Case("0xd03", "cortex-a53") 202 .Case("0xd07", "cortex-a57") 203 .Case("0xd08", "cortex-a72") 204 .Case("0xd09", "cortex-a73") 205 .Case("0xd0a", "cortex-a75") 206 .Case("0xd0b", "cortex-a76") 207 .Case("0xd0d", "cortex-a77") 208 .Case("0xd0c", "neoverse-n1") 209 .Default("generic"); 210 } 211 212 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium. 213 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 214 if (Lines[I].startswith("CPU part")) { 215 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 216 .Case("0x516", "thunderx2t99") 217 .Case("0x0516", "thunderx2t99") 218 .Case("0xaf", "thunderx2t99") 219 .Case("0x0af", "thunderx2t99") 220 .Case("0xa1", "thunderxt88") 221 .Case("0x0a1", "thunderxt88") 222 .Default("generic"); 223 } 224 } 225 } 226 227 if (Implementer == "0x46") { // Fujitsu Ltd. 228 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 229 if (Lines[I].startswith("CPU part")) { 230 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 231 .Case("0x001", "a64fx") 232 .Default("generic"); 233 } 234 } 235 } 236 237 if (Implementer == "0x4e") { // NVIDIA Corporation 238 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 239 if (Lines[I].startswith("CPU part")) { 240 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 241 .Case("0x004", "carmel") 242 .Default("generic"); 243 } 244 } 245 } 246 247 if (Implementer == "0x48") // HiSilicon Technologies, Inc. 248 // Look for the CPU part line. 249 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 250 if (Lines[I].startswith("CPU part")) 251 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 252 // values correspond to the "Part number" in the CP15/c0 register. The 253 // contents are specified in the various processor manuals. 254 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 255 .Case("0xd01", "tsv110") 256 .Default("generic"); 257 258 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 259 // Look for the CPU part line. 260 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 261 if (Lines[I].startswith("CPU part")) 262 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 263 // values correspond to the "Part number" in the CP15/c0 register. The 264 // contents are specified in the various processor manuals. 265 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 266 .Case("0x06f", "krait") // APQ8064 267 .Case("0x201", "kryo") 268 .Case("0x205", "kryo") 269 .Case("0x211", "kryo") 270 .Case("0x800", "cortex-a73") 271 .Case("0x801", "cortex-a73") 272 .Case("0x802", "cortex-a73") 273 .Case("0x803", "cortex-a73") 274 .Case("0x804", "cortex-a73") 275 .Case("0x805", "cortex-a73") 276 .Case("0xc00", "falkor") 277 .Case("0xc01", "saphira") 278 .Default("generic"); 279 280 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. 281 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow 282 // any predictive pattern across variants and parts. 283 unsigned Variant = 0, Part = 0; 284 285 // Look for the CPU variant line, whose value is a 1 digit hexadecimal 286 // number, corresponding to the Variant bits in the CP15/C0 register. 287 for (auto I : Lines) 288 if (I.consume_front("CPU variant")) 289 I.ltrim("\t :").getAsInteger(0, Variant); 290 291 // Look for the CPU part line, whose value is a 3 digit hexadecimal 292 // number, corresponding to the PartNum bits in the CP15/C0 register. 293 for (auto I : Lines) 294 if (I.consume_front("CPU part")) 295 I.ltrim("\t :").getAsInteger(0, Part); 296 297 unsigned Exynos = (Variant << 12) | Part; 298 switch (Exynos) { 299 default: 300 // Default by falling through to Exynos M3. 301 LLVM_FALLTHROUGH; 302 case 0x1002: 303 return "exynos-m3"; 304 case 0x1003: 305 return "exynos-m4"; 306 } 307 } 308 309 return "generic"; 310 } 311 312 StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { 313 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 314 315 // The "processor 0:" line comes after a fair amount of other information, 316 // including a cache breakdown, but this should be plenty. 317 SmallVector<StringRef, 32> Lines; 318 ProcCpuinfoContent.split(Lines, "\n"); 319 320 // Look for the CPU features. 321 SmallVector<StringRef, 32> CPUFeatures; 322 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 323 if (Lines[I].startswith("features")) { 324 size_t Pos = Lines[I].find(":"); 325 if (Pos != StringRef::npos) { 326 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 327 break; 328 } 329 } 330 331 // We need to check for the presence of vector support independently of 332 // the machine type, since we may only use the vector register set when 333 // supported by the kernel (and hypervisor). 334 bool HaveVectorSupport = false; 335 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 336 if (CPUFeatures[I] == "vx") 337 HaveVectorSupport = true; 338 } 339 340 // Now check the processor machine type. 341 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 342 if (Lines[I].startswith("processor ")) { 343 size_t Pos = Lines[I].find("machine = "); 344 if (Pos != StringRef::npos) { 345 Pos += sizeof("machine = ") - 1; 346 unsigned int Id; 347 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 348 if (Id >= 8561 && HaveVectorSupport) 349 return "z15"; 350 if (Id >= 3906 && HaveVectorSupport) 351 return "z14"; 352 if (Id >= 2964 && HaveVectorSupport) 353 return "z13"; 354 if (Id >= 2827) 355 return "zEC12"; 356 if (Id >= 2817) 357 return "z196"; 358 } 359 } 360 break; 361 } 362 } 363 364 return "generic"; 365 } 366 367 StringRef sys::detail::getHostCPUNameForBPF() { 368 #if !defined(__linux__) || !defined(__x86_64__) 369 return "generic"; 370 #else 371 uint8_t v3_insns[40] __attribute__ ((aligned (8))) = 372 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 373 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 374 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 375 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 376 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 377 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 378 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 379 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 380 /* BPF_EXIT_INSN() */ 381 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 382 383 uint8_t v2_insns[40] __attribute__ ((aligned (8))) = 384 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 385 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 386 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 387 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 388 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 389 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 390 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 391 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 392 /* BPF_EXIT_INSN() */ 393 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 394 395 struct bpf_prog_load_attr { 396 uint32_t prog_type; 397 uint32_t insn_cnt; 398 uint64_t insns; 399 uint64_t license; 400 uint32_t log_level; 401 uint32_t log_size; 402 uint64_t log_buf; 403 uint32_t kern_version; 404 uint32_t prog_flags; 405 } attr = {}; 406 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 407 attr.insn_cnt = 5; 408 attr.insns = (uint64_t)v3_insns; 409 attr.license = (uint64_t)"DUMMY"; 410 411 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, 412 sizeof(attr)); 413 if (fd >= 0) { 414 close(fd); 415 return "v3"; 416 } 417 418 /* Clear the whole attr in case its content changed by syscall. */ 419 memset(&attr, 0, sizeof(attr)); 420 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 421 attr.insn_cnt = 5; 422 attr.insns = (uint64_t)v2_insns; 423 attr.license = (uint64_t)"DUMMY"; 424 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 425 if (fd >= 0) { 426 close(fd); 427 return "v2"; 428 } 429 return "v1"; 430 #endif 431 } 432 433 #if defined(__i386__) || defined(_M_IX86) || \ 434 defined(__x86_64__) || defined(_M_X64) 435 436 enum VendorSignatures { 437 SIG_INTEL = 0x756e6547 /* Genu */, 438 SIG_AMD = 0x68747541 /* Auth */ 439 }; 440 441 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 442 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 443 // support. Consequently, for i386, the presence of CPUID is checked first 444 // via the corresponding eflags bit. 445 // Removal of cpuid.h header motivated by PR30384 446 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 447 // or test-suite, but are used in external projects e.g. libstdcxx 448 static bool isCpuIdSupported() { 449 #if defined(__GNUC__) || defined(__clang__) 450 #if defined(__i386__) 451 int __cpuid_supported; 452 __asm__(" pushfl\n" 453 " popl %%eax\n" 454 " movl %%eax,%%ecx\n" 455 " xorl $0x00200000,%%eax\n" 456 " pushl %%eax\n" 457 " popfl\n" 458 " pushfl\n" 459 " popl %%eax\n" 460 " movl $0,%0\n" 461 " cmpl %%eax,%%ecx\n" 462 " je 1f\n" 463 " movl $1,%0\n" 464 "1:" 465 : "=r"(__cpuid_supported) 466 : 467 : "eax", "ecx"); 468 if (!__cpuid_supported) 469 return false; 470 #endif 471 return true; 472 #endif 473 return true; 474 } 475 476 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 477 /// the specified arguments. If we can't run cpuid on the host, return true. 478 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 479 unsigned *rECX, unsigned *rEDX) { 480 #if defined(__GNUC__) || defined(__clang__) 481 #if defined(__x86_64__) 482 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 483 // FIXME: should we save this for Clang? 484 __asm__("movq\t%%rbx, %%rsi\n\t" 485 "cpuid\n\t" 486 "xchgq\t%%rbx, %%rsi\n\t" 487 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 488 : "a"(value)); 489 return false; 490 #elif defined(__i386__) 491 __asm__("movl\t%%ebx, %%esi\n\t" 492 "cpuid\n\t" 493 "xchgl\t%%ebx, %%esi\n\t" 494 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 495 : "a"(value)); 496 return false; 497 #else 498 return true; 499 #endif 500 #elif defined(_MSC_VER) 501 // The MSVC intrinsic is portable across x86 and x64. 502 int registers[4]; 503 __cpuid(registers, value); 504 *rEAX = registers[0]; 505 *rEBX = registers[1]; 506 *rECX = registers[2]; 507 *rEDX = registers[3]; 508 return false; 509 #else 510 return true; 511 #endif 512 } 513 514 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 515 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 516 /// return true. 517 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 518 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 519 unsigned *rEDX) { 520 #if defined(__GNUC__) || defined(__clang__) 521 #if defined(__x86_64__) 522 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 523 // FIXME: should we save this for Clang? 524 __asm__("movq\t%%rbx, %%rsi\n\t" 525 "cpuid\n\t" 526 "xchgq\t%%rbx, %%rsi\n\t" 527 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 528 : "a"(value), "c"(subleaf)); 529 return false; 530 #elif defined(__i386__) 531 __asm__("movl\t%%ebx, %%esi\n\t" 532 "cpuid\n\t" 533 "xchgl\t%%ebx, %%esi\n\t" 534 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 535 : "a"(value), "c"(subleaf)); 536 return false; 537 #else 538 return true; 539 #endif 540 #elif defined(_MSC_VER) 541 int registers[4]; 542 __cpuidex(registers, value, subleaf); 543 *rEAX = registers[0]; 544 *rEBX = registers[1]; 545 *rECX = registers[2]; 546 *rEDX = registers[3]; 547 return false; 548 #else 549 return true; 550 #endif 551 } 552 553 // Read control register 0 (XCR0). Used to detect features such as AVX. 554 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 555 #if defined(__GNUC__) || defined(__clang__) 556 // Check xgetbv; this uses a .byte sequence instead of the instruction 557 // directly because older assemblers do not include support for xgetbv and 558 // there is no easy way to conditionally compile based on the assembler used. 559 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 560 return false; 561 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 562 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 563 *rEAX = Result; 564 *rEDX = Result >> 32; 565 return false; 566 #else 567 return true; 568 #endif 569 } 570 571 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 572 unsigned *Model) { 573 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 574 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 575 if (*Family == 6 || *Family == 0xf) { 576 if (*Family == 0xf) 577 // Examine extended family ID if family ID is F. 578 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 579 // Examine extended model ID if family ID is 6 or F. 580 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 581 } 582 } 583 584 static void 585 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 586 const unsigned *Features, 587 unsigned *Type, unsigned *Subtype) { 588 auto testFeature = [&](unsigned F) { 589 return (Features[F / 32] & (1U << (F % 32))) != 0; 590 }; 591 592 switch (Family) { 593 case 3: 594 *Type = X86::INTEL_i386; 595 break; 596 case 4: 597 *Type = X86::INTEL_i486; 598 break; 599 case 5: 600 if (testFeature(X86::FEATURE_MMX)) { 601 *Type = X86::INTEL_PENTIUM_MMX; 602 break; 603 } 604 *Type = X86::INTEL_PENTIUM; 605 break; 606 case 6: 607 switch (Model) { 608 case 0x01: // Pentium Pro processor 609 *Type = X86::INTEL_PENTIUM_PRO; 610 break; 611 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 612 // model 03 613 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 614 // model 05, and Intel Celeron processor, model 05 615 case 0x06: // Celeron processor, model 06 616 *Type = X86::INTEL_PENTIUM_II; 617 break; 618 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 619 // processor, model 07 620 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 621 // model 08, and Celeron processor, model 08 622 case 0x0a: // Pentium III Xeon processor, model 0Ah 623 case 0x0b: // Pentium III processor, model 0Bh 624 *Type = X86::INTEL_PENTIUM_III; 625 break; 626 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 627 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 628 // 0Dh. All processors are manufactured using the 90 nm process. 629 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 630 // Integrated Processor with Intel QuickAssist Technology 631 *Type = X86::INTEL_PENTIUM_M; 632 break; 633 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 634 // 0Eh. All processors are manufactured using the 65 nm process. 635 *Type = X86::INTEL_CORE_DUO; 636 break; // yonah 637 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 638 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 639 // mobile processor, Intel Core 2 Extreme processor, Intel 640 // Pentium Dual-Core processor, Intel Xeon processor, model 641 // 0Fh. All processors are manufactured using the 65 nm process. 642 case 0x16: // Intel Celeron processor model 16h. All processors are 643 // manufactured using the 65 nm process 644 *Type = X86::INTEL_CORE2; // "core2" 645 *Subtype = X86::INTEL_CORE2_65; 646 break; 647 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 648 // 17h. All processors are manufactured using the 45 nm process. 649 // 650 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 651 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 652 // the 45 nm process. 653 *Type = X86::INTEL_CORE2; // "penryn" 654 *Subtype = X86::INTEL_CORE2_45; 655 break; 656 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 657 // processors are manufactured using the 45 nm process. 658 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 659 // As found in a Summer 2010 model iMac. 660 case 0x1f: 661 case 0x2e: // Nehalem EX 662 *Type = X86::INTEL_COREI7; // "nehalem" 663 *Subtype = X86::INTEL_COREI7_NEHALEM; 664 break; 665 case 0x25: // Intel Core i7, laptop version. 666 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 667 // processors are manufactured using the 32 nm process. 668 case 0x2f: // Westmere EX 669 *Type = X86::INTEL_COREI7; // "westmere" 670 *Subtype = X86::INTEL_COREI7_WESTMERE; 671 break; 672 case 0x2a: // Intel Core i7 processor. All processors are manufactured 673 // using the 32 nm process. 674 case 0x2d: 675 *Type = X86::INTEL_COREI7; //"sandybridge" 676 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 677 break; 678 case 0x3a: 679 case 0x3e: // Ivy Bridge EP 680 *Type = X86::INTEL_COREI7; // "ivybridge" 681 *Subtype = X86::INTEL_COREI7_IVYBRIDGE; 682 break; 683 684 // Haswell: 685 case 0x3c: 686 case 0x3f: 687 case 0x45: 688 case 0x46: 689 *Type = X86::INTEL_COREI7; // "haswell" 690 *Subtype = X86::INTEL_COREI7_HASWELL; 691 break; 692 693 // Broadwell: 694 case 0x3d: 695 case 0x47: 696 case 0x4f: 697 case 0x56: 698 *Type = X86::INTEL_COREI7; // "broadwell" 699 *Subtype = X86::INTEL_COREI7_BROADWELL; 700 break; 701 702 // Skylake: 703 case 0x4e: // Skylake mobile 704 case 0x5e: // Skylake desktop 705 case 0x8e: // Kaby Lake mobile 706 case 0x9e: // Kaby Lake desktop 707 case 0xa5: // Comet Lake-H/S 708 case 0xa6: // Comet Lake-U 709 *Type = X86::INTEL_COREI7; // "skylake" 710 *Subtype = X86::INTEL_COREI7_SKYLAKE; 711 break; 712 713 // Skylake Xeon: 714 case 0x55: 715 *Type = X86::INTEL_COREI7; 716 if (testFeature(X86::FEATURE_AVX512BF16)) 717 *Subtype = X86::INTEL_COREI7_COOPERLAKE; // "cooperlake" 718 else if (testFeature(X86::FEATURE_AVX512VNNI)) 719 *Subtype = X86::INTEL_COREI7_CASCADELAKE; // "cascadelake" 720 else 721 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 722 break; 723 724 // Cannonlake: 725 case 0x66: 726 *Type = X86::INTEL_COREI7; 727 *Subtype = X86::INTEL_COREI7_CANNONLAKE; // "cannonlake" 728 break; 729 730 // Icelake: 731 case 0x7d: 732 case 0x7e: 733 *Type = X86::INTEL_COREI7; 734 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; // "icelake-client" 735 break; 736 737 // Icelake Xeon: 738 case 0x6a: 739 case 0x6c: 740 *Type = X86::INTEL_COREI7; 741 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; // "icelake-server" 742 break; 743 744 case 0x1c: // Most 45 nm Intel Atom processors 745 case 0x26: // 45 nm Atom Lincroft 746 case 0x27: // 32 nm Atom Medfield 747 case 0x35: // 32 nm Atom Midview 748 case 0x36: // 32 nm Atom Midview 749 *Type = X86::INTEL_BONNELL; 750 break; // "bonnell" 751 752 // Atom Silvermont codes from the Intel software optimization guide. 753 case 0x37: 754 case 0x4a: 755 case 0x4d: 756 case 0x5a: 757 case 0x5d: 758 case 0x4c: // really airmont 759 *Type = X86::INTEL_SILVERMONT; 760 break; // "silvermont" 761 // Goldmont: 762 case 0x5c: // Apollo Lake 763 case 0x5f: // Denverton 764 *Type = X86::INTEL_GOLDMONT; 765 break; // "goldmont" 766 case 0x7a: 767 *Type = X86::INTEL_GOLDMONT_PLUS; 768 break; 769 case 0x86: 770 *Type = X86::INTEL_TREMONT; 771 break; 772 773 case 0x57: 774 *Type = X86::INTEL_KNL; // knl 775 break; 776 777 case 0x85: 778 *Type = X86::INTEL_KNM; // knm 779 break; 780 781 default: // Unknown family 6 CPU, try to guess. 782 // TODO detect tigerlake host from model 783 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) { 784 *Type = X86::INTEL_COREI7; 785 *Subtype = X86::INTEL_COREI7_TIGERLAKE; 786 break; 787 } 788 789 if (testFeature(X86::FEATURE_AVX512VBMI2)) { 790 *Type = X86::INTEL_COREI7; 791 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; 792 break; 793 } 794 795 if (testFeature(X86::FEATURE_AVX512VBMI)) { 796 *Type = X86::INTEL_COREI7; 797 *Subtype = X86::INTEL_COREI7_CANNONLAKE; 798 break; 799 } 800 801 if (testFeature(X86::FEATURE_AVX512BF16)) { 802 *Type = X86::INTEL_COREI7; 803 *Subtype = X86::INTEL_COREI7_COOPERLAKE; 804 break; 805 } 806 807 if (testFeature(X86::FEATURE_AVX512VNNI)) { 808 *Type = X86::INTEL_COREI7; 809 *Subtype = X86::INTEL_COREI7_CASCADELAKE; 810 break; 811 } 812 813 if (testFeature(X86::FEATURE_AVX512VL)) { 814 *Type = X86::INTEL_COREI7; 815 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; 816 break; 817 } 818 819 if (testFeature(X86::FEATURE_AVX512ER)) { 820 *Type = X86::INTEL_KNL; // knl 821 break; 822 } 823 824 if (testFeature(X86::FEATURE_CLFLUSHOPT)) { 825 if (testFeature(X86::FEATURE_SHA)) { 826 *Type = X86::INTEL_GOLDMONT; 827 } else { 828 *Type = X86::INTEL_COREI7; 829 *Subtype = X86::INTEL_COREI7_SKYLAKE; 830 } 831 break; 832 } 833 if (testFeature(X86::FEATURE_ADX)) { 834 *Type = X86::INTEL_COREI7; 835 *Subtype = X86::INTEL_COREI7_BROADWELL; 836 break; 837 } 838 if (testFeature(X86::FEATURE_AVX2)) { 839 *Type = X86::INTEL_COREI7; 840 *Subtype = X86::INTEL_COREI7_HASWELL; 841 break; 842 } 843 if (testFeature(X86::FEATURE_AVX)) { 844 *Type = X86::INTEL_COREI7; 845 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 846 break; 847 } 848 if (testFeature(X86::FEATURE_SSE4_2)) { 849 if (testFeature(X86::FEATURE_MOVBE)) { 850 *Type = X86::INTEL_SILVERMONT; 851 } else { 852 *Type = X86::INTEL_COREI7; 853 *Subtype = X86::INTEL_COREI7_NEHALEM; 854 } 855 break; 856 } 857 if (testFeature(X86::FEATURE_SSE4_1)) { 858 *Type = X86::INTEL_CORE2; // "penryn" 859 *Subtype = X86::INTEL_CORE2_45; 860 break; 861 } 862 if (testFeature(X86::FEATURE_SSSE3)) { 863 if (testFeature(X86::FEATURE_MOVBE)) { 864 *Type = X86::INTEL_BONNELL; // "bonnell" 865 } else { 866 *Type = X86::INTEL_CORE2; // "core2" 867 *Subtype = X86::INTEL_CORE2_65; 868 } 869 break; 870 } 871 if (testFeature(X86::FEATURE_64BIT)) { 872 *Type = X86::INTEL_CORE2; // "core2" 873 *Subtype = X86::INTEL_CORE2_65; 874 break; 875 } 876 if (testFeature(X86::FEATURE_SSE3)) { 877 *Type = X86::INTEL_CORE_DUO; 878 break; 879 } 880 if (testFeature(X86::FEATURE_SSE2)) { 881 *Type = X86::INTEL_PENTIUM_M; 882 break; 883 } 884 if (testFeature(X86::FEATURE_SSE)) { 885 *Type = X86::INTEL_PENTIUM_III; 886 break; 887 } 888 if (testFeature(X86::FEATURE_MMX)) { 889 *Type = X86::INTEL_PENTIUM_II; 890 break; 891 } 892 *Type = X86::INTEL_PENTIUM_PRO; 893 break; 894 } 895 break; 896 case 15: { 897 if (testFeature(X86::FEATURE_64BIT)) { 898 *Type = X86::INTEL_NOCONA; 899 break; 900 } 901 if (testFeature(X86::FEATURE_SSE3)) { 902 *Type = X86::INTEL_PRESCOTT; 903 break; 904 } 905 *Type = X86::INTEL_PENTIUM_IV; 906 break; 907 } 908 default: 909 break; /*"generic"*/ 910 } 911 } 912 913 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 914 const unsigned *Features, 915 unsigned *Type, unsigned *Subtype) { 916 auto testFeature = [&](unsigned F) { 917 return (Features[F / 32] & (1U << (F % 32))) != 0; 918 }; 919 920 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 921 // appears to be no way to generate the wide variety of AMD-specific targets 922 // from the information returned from CPUID. 923 switch (Family) { 924 case 4: 925 *Type = X86::AMD_i486; 926 break; 927 case 5: 928 *Type = X86::AMDPENTIUM; 929 switch (Model) { 930 case 6: 931 case 7: 932 *Subtype = X86::AMDPENTIUM_K6; 933 break; // "k6" 934 case 8: 935 *Subtype = X86::AMDPENTIUM_K62; 936 break; // "k6-2" 937 case 9: 938 case 13: 939 *Subtype = X86::AMDPENTIUM_K63; 940 break; // "k6-3" 941 case 10: 942 *Subtype = X86::AMDPENTIUM_GEODE; 943 break; // "geode" 944 } 945 break; 946 case 6: 947 if (testFeature(X86::FEATURE_SSE)) { 948 *Type = X86::AMD_ATHLON_XP; 949 break; // "athlon-xp" 950 } 951 *Type = X86::AMD_ATHLON; 952 break; // "athlon" 953 case 15: 954 if (testFeature(X86::FEATURE_SSE3)) { 955 *Type = X86::AMD_K8SSE3; 956 break; // "k8-sse3" 957 } 958 *Type = X86::AMD_K8; 959 break; // "k8" 960 case 16: 961 *Type = X86::AMDFAM10H; // "amdfam10" 962 switch (Model) { 963 case 2: 964 *Subtype = X86::AMDFAM10H_BARCELONA; 965 break; 966 case 4: 967 *Subtype = X86::AMDFAM10H_SHANGHAI; 968 break; 969 case 8: 970 *Subtype = X86::AMDFAM10H_ISTANBUL; 971 break; 972 } 973 break; 974 case 20: 975 *Type = X86::AMD_BTVER1; 976 break; // "btver1"; 977 case 21: 978 *Type = X86::AMDFAM15H; 979 if (Model >= 0x60 && Model <= 0x7f) { 980 *Subtype = X86::AMDFAM15H_BDVER4; 981 break; // "bdver4"; 60h-7Fh: Excavator 982 } 983 if (Model >= 0x30 && Model <= 0x3f) { 984 *Subtype = X86::AMDFAM15H_BDVER3; 985 break; // "bdver3"; 30h-3Fh: Steamroller 986 } 987 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) { 988 *Subtype = X86::AMDFAM15H_BDVER2; 989 break; // "bdver2"; 02h, 10h-1Fh: Piledriver 990 } 991 if (Model <= 0x0f) { 992 *Subtype = X86::AMDFAM15H_BDVER1; 993 break; // "bdver1"; 00h-0Fh: Bulldozer 994 } 995 break; 996 case 22: 997 *Type = X86::AMD_BTVER2; 998 break; // "btver2" 999 case 23: 1000 *Type = X86::AMDFAM17H; 1001 if ((Model >= 0x30 && Model <= 0x3f) || Model == 0x71) { 1002 *Subtype = X86::AMDFAM17H_ZNVER2; 1003 break; // "znver2"; 30h-3fh, 71h: Zen2 1004 } 1005 if (Model <= 0x0f) { 1006 *Subtype = X86::AMDFAM17H_ZNVER1; 1007 break; // "znver1"; 00h-0Fh: Zen1 1008 } 1009 break; 1010 default: 1011 break; // "generic" 1012 } 1013 } 1014 1015 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 1016 unsigned *Features) { 1017 unsigned EAX, EBX; 1018 1019 auto setFeature = [&](unsigned F) { 1020 Features[F / 32] |= 1U << (F % 32); 1021 }; 1022 1023 if ((EDX >> 15) & 1) 1024 setFeature(X86::FEATURE_CMOV); 1025 if ((EDX >> 23) & 1) 1026 setFeature(X86::FEATURE_MMX); 1027 if ((EDX >> 25) & 1) 1028 setFeature(X86::FEATURE_SSE); 1029 if ((EDX >> 26) & 1) 1030 setFeature(X86::FEATURE_SSE2); 1031 1032 if ((ECX >> 0) & 1) 1033 setFeature(X86::FEATURE_SSE3); 1034 if ((ECX >> 1) & 1) 1035 setFeature(X86::FEATURE_PCLMUL); 1036 if ((ECX >> 9) & 1) 1037 setFeature(X86::FEATURE_SSSE3); 1038 if ((ECX >> 12) & 1) 1039 setFeature(X86::FEATURE_FMA); 1040 if ((ECX >> 19) & 1) 1041 setFeature(X86::FEATURE_SSE4_1); 1042 if ((ECX >> 20) & 1) 1043 setFeature(X86::FEATURE_SSE4_2); 1044 if ((ECX >> 23) & 1) 1045 setFeature(X86::FEATURE_POPCNT); 1046 if ((ECX >> 25) & 1) 1047 setFeature(X86::FEATURE_AES); 1048 1049 if ((ECX >> 22) & 1) 1050 setFeature(X86::FEATURE_MOVBE); 1051 1052 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1053 // indicates that the AVX registers will be saved and restored on context 1054 // switch, then we have full AVX support. 1055 const unsigned AVXBits = (1 << 27) | (1 << 28); 1056 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 1057 ((EAX & 0x6) == 0x6); 1058 #if defined(__APPLE__) 1059 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1060 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1061 // set right now. 1062 bool HasAVX512Save = true; 1063 #else 1064 // AVX512 requires additional context to be saved by the OS. 1065 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 1066 #endif 1067 1068 if (HasAVX) 1069 setFeature(X86::FEATURE_AVX); 1070 1071 bool HasLeaf7 = 1072 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1073 1074 if (HasLeaf7 && ((EBX >> 3) & 1)) 1075 setFeature(X86::FEATURE_BMI); 1076 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 1077 setFeature(X86::FEATURE_AVX2); 1078 if (HasLeaf7 && ((EBX >> 8) & 1)) 1079 setFeature(X86::FEATURE_BMI2); 1080 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 1081 setFeature(X86::FEATURE_AVX512F); 1082 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 1083 setFeature(X86::FEATURE_AVX512DQ); 1084 if (HasLeaf7 && ((EBX >> 19) & 1)) 1085 setFeature(X86::FEATURE_ADX); 1086 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 1087 setFeature(X86::FEATURE_AVX512IFMA); 1088 if (HasLeaf7 && ((EBX >> 23) & 1)) 1089 setFeature(X86::FEATURE_CLFLUSHOPT); 1090 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 1091 setFeature(X86::FEATURE_AVX512PF); 1092 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 1093 setFeature(X86::FEATURE_AVX512ER); 1094 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 1095 setFeature(X86::FEATURE_AVX512CD); 1096 if (HasLeaf7 && ((EBX >> 29) & 1)) 1097 setFeature(X86::FEATURE_SHA); 1098 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 1099 setFeature(X86::FEATURE_AVX512BW); 1100 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 1101 setFeature(X86::FEATURE_AVX512VL); 1102 1103 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 1104 setFeature(X86::FEATURE_AVX512VBMI); 1105 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save) 1106 setFeature(X86::FEATURE_AVX512VBMI2); 1107 if (HasLeaf7 && ((ECX >> 8) & 1)) 1108 setFeature(X86::FEATURE_GFNI); 1109 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX) 1110 setFeature(X86::FEATURE_VPCLMULQDQ); 1111 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save) 1112 setFeature(X86::FEATURE_AVX512VNNI); 1113 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save) 1114 setFeature(X86::FEATURE_AVX512BITALG); 1115 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1116 setFeature(X86::FEATURE_AVX512VPOPCNTDQ); 1117 1118 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1119 setFeature(X86::FEATURE_AVX5124VNNIW); 1120 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1121 setFeature(X86::FEATURE_AVX5124FMAPS); 1122 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save) 1123 setFeature(X86::FEATURE_AVX512VP2INTERSECT); 1124 1125 bool HasLeaf7Subleaf1 = 1126 MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1127 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save) 1128 setFeature(X86::FEATURE_AVX512BF16); 1129 1130 unsigned MaxExtLevel; 1131 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1132 1133 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1134 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1135 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1136 setFeature(X86::FEATURE_SSE4_A); 1137 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1138 setFeature(X86::FEATURE_XOP); 1139 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1140 setFeature(X86::FEATURE_FMA4); 1141 1142 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1143 setFeature(X86::FEATURE_64BIT); 1144 } 1145 1146 StringRef sys::getHostCPUName() { 1147 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1148 unsigned MaxLeaf, Vendor; 1149 1150 if (!isCpuIdSupported()) 1151 return "generic"; 1152 1153 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) 1154 return "generic"; 1155 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1156 1157 unsigned Family = 0, Model = 0; 1158 unsigned Features[(X86::CPU_FEATURE_MAX + 31) / 32] = {0}; 1159 detectX86FamilyModel(EAX, &Family, &Model); 1160 getAvailableFeatures(ECX, EDX, MaxLeaf, Features); 1161 1162 unsigned Type = 0; 1163 unsigned Subtype = 0; 1164 1165 if (Vendor == SIG_INTEL) { 1166 getIntelProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1167 } else if (Vendor == SIG_AMD) { 1168 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1169 } 1170 1171 // Check subtypes first since those are more specific. 1172 #define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \ 1173 if (Subtype == X86::ENUM) \ 1174 return ARCHNAME; 1175 #include "llvm/Support/X86TargetParser.def" 1176 1177 // Now check types. 1178 #define X86_CPU_TYPE(ARCHNAME, ENUM) \ 1179 if (Type == X86::ENUM) \ 1180 return ARCHNAME; 1181 #include "llvm/Support/X86TargetParser.def" 1182 1183 return "generic"; 1184 } 1185 1186 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1187 StringRef sys::getHostCPUName() { 1188 host_basic_info_data_t hostInfo; 1189 mach_msg_type_number_t infoCount; 1190 1191 infoCount = HOST_BASIC_INFO_COUNT; 1192 mach_port_t hostPort = mach_host_self(); 1193 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1194 &infoCount); 1195 mach_port_deallocate(mach_task_self(), hostPort); 1196 1197 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1198 return "generic"; 1199 1200 switch (hostInfo.cpu_subtype) { 1201 case CPU_SUBTYPE_POWERPC_601: 1202 return "601"; 1203 case CPU_SUBTYPE_POWERPC_602: 1204 return "602"; 1205 case CPU_SUBTYPE_POWERPC_603: 1206 return "603"; 1207 case CPU_SUBTYPE_POWERPC_603e: 1208 return "603e"; 1209 case CPU_SUBTYPE_POWERPC_603ev: 1210 return "603ev"; 1211 case CPU_SUBTYPE_POWERPC_604: 1212 return "604"; 1213 case CPU_SUBTYPE_POWERPC_604e: 1214 return "604e"; 1215 case CPU_SUBTYPE_POWERPC_620: 1216 return "620"; 1217 case CPU_SUBTYPE_POWERPC_750: 1218 return "750"; 1219 case CPU_SUBTYPE_POWERPC_7400: 1220 return "7400"; 1221 case CPU_SUBTYPE_POWERPC_7450: 1222 return "7450"; 1223 case CPU_SUBTYPE_POWERPC_970: 1224 return "970"; 1225 default:; 1226 } 1227 1228 return "generic"; 1229 } 1230 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1231 StringRef sys::getHostCPUName() { 1232 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1233 StringRef Content = P ? P->getBuffer() : ""; 1234 return detail::getHostCPUNameForPowerPC(Content); 1235 } 1236 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1237 StringRef sys::getHostCPUName() { 1238 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1239 StringRef Content = P ? P->getBuffer() : ""; 1240 return detail::getHostCPUNameForARM(Content); 1241 } 1242 #elif defined(__linux__) && defined(__s390x__) 1243 StringRef sys::getHostCPUName() { 1244 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1245 StringRef Content = P ? P->getBuffer() : ""; 1246 return detail::getHostCPUNameForS390x(Content); 1247 } 1248 #elif defined(__APPLE__) && defined(__aarch64__) 1249 StringRef sys::getHostCPUName() { 1250 return "cyclone"; 1251 } 1252 #elif defined(__APPLE__) && defined(__arm__) 1253 StringRef sys::getHostCPUName() { 1254 host_basic_info_data_t hostInfo; 1255 mach_msg_type_number_t infoCount; 1256 1257 infoCount = HOST_BASIC_INFO_COUNT; 1258 mach_port_t hostPort = mach_host_self(); 1259 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1260 &infoCount); 1261 mach_port_deallocate(mach_task_self(), hostPort); 1262 1263 if (hostInfo.cpu_type != CPU_TYPE_ARM) { 1264 assert(false && "CPUType not equal to ARM should not be possible on ARM"); 1265 return "generic"; 1266 } 1267 switch (hostInfo.cpu_subtype) { 1268 case CPU_SUBTYPE_ARM_V7S: 1269 return "swift"; 1270 default:; 1271 } 1272 1273 return "generic"; 1274 } 1275 #else 1276 StringRef sys::getHostCPUName() { return "generic"; } 1277 #endif 1278 1279 #if defined(__linux__) && (defined(__i386__) || defined(__x86_64__)) 1280 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1281 // using the number of unique physical/core id pairs. The following 1282 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1283 int computeHostNumPhysicalCores() { 1284 // Enabled represents the number of physical id/core id pairs with at least 1285 // one processor id enabled by the CPU affinity mask. 1286 cpu_set_t Affinity, Enabled; 1287 if (sched_getaffinity(0, sizeof(Affinity), &Affinity) != 0) 1288 return -1; 1289 CPU_ZERO(&Enabled); 1290 1291 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1292 // mmapped because it appears to have 0 size. 1293 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1294 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1295 if (std::error_code EC = Text.getError()) { 1296 llvm::errs() << "Can't read " 1297 << "/proc/cpuinfo: " << EC.message() << "\n"; 1298 return -1; 1299 } 1300 SmallVector<StringRef, 8> strs; 1301 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1302 /*KeepEmpty=*/false); 1303 int CurProcessor = -1; 1304 int CurPhysicalId = -1; 1305 int CurSiblings = -1; 1306 int CurCoreId = -1; 1307 for (StringRef Line : strs) { 1308 std::pair<StringRef, StringRef> Data = Line.split(':'); 1309 auto Name = Data.first.trim(); 1310 auto Val = Data.second.trim(); 1311 // These fields are available if the kernel is configured with CONFIG_SMP. 1312 if (Name == "processor") 1313 Val.getAsInteger(10, CurProcessor); 1314 else if (Name == "physical id") 1315 Val.getAsInteger(10, CurPhysicalId); 1316 else if (Name == "siblings") 1317 Val.getAsInteger(10, CurSiblings); 1318 else if (Name == "core id") { 1319 Val.getAsInteger(10, CurCoreId); 1320 // The processor id corresponds to an index into cpu_set_t. 1321 if (CPU_ISSET(CurProcessor, &Affinity)) 1322 CPU_SET(CurPhysicalId * CurSiblings + CurCoreId, &Enabled); 1323 } 1324 } 1325 return CPU_COUNT(&Enabled); 1326 } 1327 #elif defined(__APPLE__) && defined(__x86_64__) 1328 #include <sys/param.h> 1329 #include <sys/sysctl.h> 1330 1331 // Gets the number of *physical cores* on the machine. 1332 int computeHostNumPhysicalCores() { 1333 uint32_t count; 1334 size_t len = sizeof(count); 1335 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1336 if (count < 1) { 1337 int nm[2]; 1338 nm[0] = CTL_HW; 1339 nm[1] = HW_AVAILCPU; 1340 sysctl(nm, 2, &count, &len, NULL, 0); 1341 if (count < 1) 1342 return -1; 1343 } 1344 return count; 1345 } 1346 #elif defined(_WIN32) && LLVM_ENABLE_THREADS != 0 1347 // Defined in llvm/lib/Support/Windows/Threading.inc 1348 int computeHostNumPhysicalCores(); 1349 #else 1350 // On other systems, return -1 to indicate unknown. 1351 static int computeHostNumPhysicalCores() { return -1; } 1352 #endif 1353 1354 int sys::getHostNumPhysicalCores() { 1355 static int NumCores = computeHostNumPhysicalCores(); 1356 return NumCores; 1357 } 1358 1359 #if defined(__i386__) || defined(_M_IX86) || \ 1360 defined(__x86_64__) || defined(_M_X64) 1361 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1362 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1363 unsigned MaxLevel; 1364 1365 if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1) 1366 return false; 1367 1368 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1369 1370 Features["cx8"] = (EDX >> 8) & 1; 1371 Features["cmov"] = (EDX >> 15) & 1; 1372 Features["mmx"] = (EDX >> 23) & 1; 1373 Features["fxsr"] = (EDX >> 24) & 1; 1374 Features["sse"] = (EDX >> 25) & 1; 1375 Features["sse2"] = (EDX >> 26) & 1; 1376 1377 Features["sse3"] = (ECX >> 0) & 1; 1378 Features["pclmul"] = (ECX >> 1) & 1; 1379 Features["ssse3"] = (ECX >> 9) & 1; 1380 Features["cx16"] = (ECX >> 13) & 1; 1381 Features["sse4.1"] = (ECX >> 19) & 1; 1382 Features["sse4.2"] = (ECX >> 20) & 1; 1383 Features["movbe"] = (ECX >> 22) & 1; 1384 Features["popcnt"] = (ECX >> 23) & 1; 1385 Features["aes"] = (ECX >> 25) & 1; 1386 Features["rdrnd"] = (ECX >> 30) & 1; 1387 1388 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1389 // indicates that the AVX registers will be saved and restored on context 1390 // switch, then we have full AVX support. 1391 bool HasXSave = ((ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX); 1392 bool HasAVXSave = HasXSave && ((ECX >> 28) & 1) && ((EAX & 0x6) == 0x6); 1393 #if defined(__APPLE__) 1394 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1395 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1396 // set right now. 1397 bool HasAVX512Save = true; 1398 #else 1399 // AVX512 requires additional context to be saved by the OS. 1400 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1401 #endif 1402 // AMX requires additional context to be saved by the OS. 1403 const unsigned AMXBits = (1 << 17) | (1 << 18); 1404 bool HasAMXSave = HasXSave && ((EAX & AMXBits) == AMXBits); 1405 1406 Features["avx"] = HasAVXSave; 1407 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave; 1408 // Only enable XSAVE if OS has enabled support for saving YMM state. 1409 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave; 1410 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave; 1411 1412 unsigned MaxExtLevel; 1413 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1414 1415 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1416 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1417 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1); 1418 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1419 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1420 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1421 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1422 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1423 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1424 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1425 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1426 1427 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1); 1428 1429 // Miscellaneous memory related features, detected by 1430 // using the 0x80000008 leaf of the CPUID instruction 1431 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1432 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX); 1433 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1434 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1); 1435 1436 bool HasLeaf7 = 1437 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1438 1439 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1440 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1441 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1442 // AVX2 is only supported if we have the OS save support from AVX. 1443 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave; 1444 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1445 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1446 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1447 // AVX512 is only supported if the OS supports the context save for it. 1448 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1449 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1450 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1451 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1452 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1453 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1454 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1455 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1456 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1457 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1458 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1459 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1460 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1461 1462 Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1); 1463 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1464 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1465 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1); 1466 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save; 1467 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1); 1468 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1); 1469 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave; 1470 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave; 1471 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save; 1472 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save; 1473 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1474 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1); 1475 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1); 1476 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1); 1477 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1); 1478 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1); 1479 1480 Features["avx512vp2intersect"] = 1481 HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save; 1482 Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1); 1483 Features["tsxldtrk"] = HasLeaf7 && ((EDX >> 16) & 1); 1484 // There are two CPUID leafs which information associated with the pconfig 1485 // instruction: 1486 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th 1487 // bit of EDX), while the EAX=0x1b leaf returns information on the 1488 // availability of specific pconfig leafs. 1489 // The target feature here only refers to the the first of these two. 1490 // Users might need to check for the availability of specific pconfig 1491 // leaves using cpuid, since that information is ignored while 1492 // detecting features using the "-march=native" flag. 1493 // For more info, see X86 ISA docs. 1494 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1); 1495 Features["amx-bf16"] = HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave; 1496 Features["amx-tile"] = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave; 1497 Features["amx-int8"] = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave; 1498 bool HasLeaf7Subleaf1 = 1499 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1500 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save; 1501 1502 bool HasLeafD = MaxLevel >= 0xd && 1503 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1504 1505 // Only enable XSAVE if OS has enabled support for saving YMM state. 1506 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave; 1507 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave; 1508 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave; 1509 1510 bool HasLeaf14 = MaxLevel >= 0x14 && 1511 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX); 1512 1513 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1); 1514 1515 return true; 1516 } 1517 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1518 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1519 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1520 if (!P) 1521 return false; 1522 1523 SmallVector<StringRef, 32> Lines; 1524 P->getBuffer().split(Lines, "\n"); 1525 1526 SmallVector<StringRef, 32> CPUFeatures; 1527 1528 // Look for the CPU features. 1529 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1530 if (Lines[I].startswith("Features")) { 1531 Lines[I].split(CPUFeatures, ' '); 1532 break; 1533 } 1534 1535 #if defined(__aarch64__) 1536 // Keep track of which crypto features we have seen 1537 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1538 uint32_t crypto = 0; 1539 #endif 1540 1541 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1542 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1543 #if defined(__aarch64__) 1544 .Case("asimd", "neon") 1545 .Case("fp", "fp-armv8") 1546 .Case("crc32", "crc") 1547 #else 1548 .Case("half", "fp16") 1549 .Case("neon", "neon") 1550 .Case("vfpv3", "vfp3") 1551 .Case("vfpv3d16", "d16") 1552 .Case("vfpv4", "vfp4") 1553 .Case("idiva", "hwdiv-arm") 1554 .Case("idivt", "hwdiv") 1555 #endif 1556 .Default(""); 1557 1558 #if defined(__aarch64__) 1559 // We need to check crypto separately since we need all of the crypto 1560 // extensions to enable the subtarget feature 1561 if (CPUFeatures[I] == "aes") 1562 crypto |= CAP_AES; 1563 else if (CPUFeatures[I] == "pmull") 1564 crypto |= CAP_PMULL; 1565 else if (CPUFeatures[I] == "sha1") 1566 crypto |= CAP_SHA1; 1567 else if (CPUFeatures[I] == "sha2") 1568 crypto |= CAP_SHA2; 1569 #endif 1570 1571 if (LLVMFeatureStr != "") 1572 Features[LLVMFeatureStr] = true; 1573 } 1574 1575 #if defined(__aarch64__) 1576 // If we have all crypto bits we can add the feature 1577 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1578 Features["crypto"] = true; 1579 #endif 1580 1581 return true; 1582 } 1583 #elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64)) 1584 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1585 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE)) 1586 Features["neon"] = true; 1587 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE)) 1588 Features["crc"] = true; 1589 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) 1590 Features["crypto"] = true; 1591 1592 return true; 1593 } 1594 #else 1595 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1596 #endif 1597 1598 std::string sys::getProcessTriple() { 1599 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1600 Triple PT(Triple::normalize(TargetTripleString)); 1601 1602 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1603 PT = PT.get64BitArchVariant(); 1604 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1605 PT = PT.get32BitArchVariant(); 1606 1607 return PT.str(); 1608 } 1609