1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the operating system Host concept. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Support/Host.h" 15 #include "llvm/ADT/SmallSet.h" 16 #include "llvm/ADT/SmallVector.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include <assert.h> 26 #include <string.h> 27 28 // Include the platform-specific parts of this class. 29 #ifdef LLVM_ON_UNIX 30 #include "Unix/Host.inc" 31 #endif 32 #ifdef LLVM_ON_WIN32 33 #include "Windows/Host.inc" 34 #endif 35 #ifdef _MSC_VER 36 #include <intrin.h> 37 #endif 38 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 39 #include <mach/host_info.h> 40 #include <mach/mach.h> 41 #include <mach/mach_host.h> 42 #include <mach/machine.h> 43 #endif 44 45 #define DEBUG_TYPE "host-detection" 46 47 //===----------------------------------------------------------------------===// 48 // 49 // Implementations of the CPU detection routines 50 // 51 //===----------------------------------------------------------------------===// 52 53 using namespace llvm; 54 55 static std::unique_ptr<llvm::MemoryBuffer> 56 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 57 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 58 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 59 if (std::error_code EC = Text.getError()) { 60 llvm::errs() << "Can't read " 61 << "/proc/cpuinfo: " << EC.message() << "\n"; 62 return nullptr; 63 } 64 return std::move(*Text); 65 } 66 67 StringRef sys::detail::getHostCPUNameForPowerPC( 68 const StringRef &ProcCpuinfoContent) { 69 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 70 // and so we must use an operating-system interface to determine the current 71 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 72 const char *generic = "generic"; 73 74 // The cpu line is second (after the 'processor: 0' line), so if this 75 // buffer is too small then something has changed (or is wrong). 76 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 77 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 78 79 StringRef::const_iterator CIP = CPUInfoStart; 80 81 StringRef::const_iterator CPUStart = 0; 82 size_t CPULen = 0; 83 84 // We need to find the first line which starts with cpu, spaces, and a colon. 85 // After the colon, there may be some additional spaces and then the cpu type. 86 while (CIP < CPUInfoEnd && CPUStart == 0) { 87 if (CIP < CPUInfoEnd && *CIP == '\n') 88 ++CIP; 89 90 if (CIP < CPUInfoEnd && *CIP == 'c') { 91 ++CIP; 92 if (CIP < CPUInfoEnd && *CIP == 'p') { 93 ++CIP; 94 if (CIP < CPUInfoEnd && *CIP == 'u') { 95 ++CIP; 96 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 97 ++CIP; 98 99 if (CIP < CPUInfoEnd && *CIP == ':') { 100 ++CIP; 101 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 102 ++CIP; 103 104 if (CIP < CPUInfoEnd) { 105 CPUStart = CIP; 106 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 107 *CIP != ',' && *CIP != '\n')) 108 ++CIP; 109 CPULen = CIP - CPUStart; 110 } 111 } 112 } 113 } 114 } 115 116 if (CPUStart == 0) 117 while (CIP < CPUInfoEnd && *CIP != '\n') 118 ++CIP; 119 } 120 121 if (CPUStart == 0) 122 return generic; 123 124 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 125 .Case("604e", "604e") 126 .Case("604", "604") 127 .Case("7400", "7400") 128 .Case("7410", "7400") 129 .Case("7447", "7400") 130 .Case("7455", "7450") 131 .Case("G4", "g4") 132 .Case("POWER4", "970") 133 .Case("PPC970FX", "970") 134 .Case("PPC970MP", "970") 135 .Case("G5", "g5") 136 .Case("POWER5", "g5") 137 .Case("A2", "a2") 138 .Case("POWER6", "pwr6") 139 .Case("POWER7", "pwr7") 140 .Case("POWER8", "pwr8") 141 .Case("POWER8E", "pwr8") 142 .Case("POWER8NVL", "pwr8") 143 .Case("POWER9", "pwr9") 144 .Default(generic); 145 } 146 147 StringRef sys::detail::getHostCPUNameForARM( 148 const StringRef &ProcCpuinfoContent) { 149 // The cpuid register on arm is not accessible from user space. On Linux, 150 // it is exposed through the /proc/cpuinfo file. 151 152 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 153 // in all cases. 154 SmallVector<StringRef, 32> Lines; 155 ProcCpuinfoContent.split(Lines, "\n"); 156 157 // Look for the CPU implementer line. 158 StringRef Implementer; 159 StringRef Hardware; 160 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 161 if (Lines[I].startswith("CPU implementer")) 162 Implementer = Lines[I].substr(15).ltrim("\t :"); 163 if (Lines[I].startswith("Hardware")) 164 Hardware = Lines[I].substr(8).ltrim("\t :"); 165 } 166 167 if (Implementer == "0x41") { // ARM Ltd. 168 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 169 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 170 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 171 return "cortex-a53"; 172 173 174 // Look for the CPU part line. 175 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 176 if (Lines[I].startswith("CPU part")) 177 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 178 // values correspond to the "Part number" in the CP15/c0 register. The 179 // contents are specified in the various processor manuals. 180 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 181 .Case("0x926", "arm926ej-s") 182 .Case("0xb02", "mpcore") 183 .Case("0xb36", "arm1136j-s") 184 .Case("0xb56", "arm1156t2-s") 185 .Case("0xb76", "arm1176jz-s") 186 .Case("0xc08", "cortex-a8") 187 .Case("0xc09", "cortex-a9") 188 .Case("0xc0f", "cortex-a15") 189 .Case("0xc20", "cortex-m0") 190 .Case("0xc23", "cortex-m3") 191 .Case("0xc24", "cortex-m4") 192 .Case("0xd04", "cortex-a35") 193 .Case("0xd03", "cortex-a53") 194 .Case("0xd07", "cortex-a57") 195 .Case("0xd08", "cortex-a72") 196 .Case("0xd09", "cortex-a73") 197 .Default("generic"); 198 } 199 200 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 201 // Look for the CPU part line. 202 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 203 if (Lines[I].startswith("CPU part")) 204 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 205 // values correspond to the "Part number" in the CP15/c0 register. The 206 // contents are specified in the various processor manuals. 207 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 208 .Case("0x06f", "krait") // APQ8064 209 .Case("0x201", "kryo") 210 .Case("0x205", "kryo") 211 .Case("0x211", "kryo") 212 .Case("0x800", "cortex-a73") 213 .Case("0x801", "cortex-a73") 214 .Case("0xc00", "falkor") 215 .Case("0xc01", "saphira") 216 .Default("generic"); 217 218 return "generic"; 219 } 220 221 StringRef sys::detail::getHostCPUNameForS390x( 222 const StringRef &ProcCpuinfoContent) { 223 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 224 225 // The "processor 0:" line comes after a fair amount of other information, 226 // including a cache breakdown, but this should be plenty. 227 SmallVector<StringRef, 32> Lines; 228 ProcCpuinfoContent.split(Lines, "\n"); 229 230 // Look for the CPU features. 231 SmallVector<StringRef, 32> CPUFeatures; 232 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 233 if (Lines[I].startswith("features")) { 234 size_t Pos = Lines[I].find(":"); 235 if (Pos != StringRef::npos) { 236 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 237 break; 238 } 239 } 240 241 // We need to check for the presence of vector support independently of 242 // the machine type, since we may only use the vector register set when 243 // supported by the kernel (and hypervisor). 244 bool HaveVectorSupport = false; 245 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 246 if (CPUFeatures[I] == "vx") 247 HaveVectorSupport = true; 248 } 249 250 // Now check the processor machine type. 251 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 252 if (Lines[I].startswith("processor ")) { 253 size_t Pos = Lines[I].find("machine = "); 254 if (Pos != StringRef::npos) { 255 Pos += sizeof("machine = ") - 1; 256 unsigned int Id; 257 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 258 if (Id >= 3906 && HaveVectorSupport) 259 return "z14"; 260 if (Id >= 2964 && HaveVectorSupport) 261 return "z13"; 262 if (Id >= 2827) 263 return "zEC12"; 264 if (Id >= 2817) 265 return "z196"; 266 } 267 } 268 break; 269 } 270 } 271 272 return "generic"; 273 } 274 275 StringRef sys::detail::getHostCPUNameForBPF() { 276 #if !defined(__linux__) || !defined(__x86_64__) 277 return "generic"; 278 #else 279 uint8_t insns[40] __attribute__ ((aligned (8))) = 280 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 281 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 282 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 283 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 284 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 285 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 286 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 287 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 288 /* BPF_EXIT_INSN() */ 289 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 290 291 struct bpf_prog_load_attr { 292 uint32_t prog_type; 293 uint32_t insn_cnt; 294 uint64_t insns; 295 uint64_t license; 296 uint32_t log_level; 297 uint32_t log_size; 298 uint64_t log_buf; 299 uint32_t kern_version; 300 uint32_t prog_flags; 301 } attr = {}; 302 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 303 attr.insn_cnt = 5; 304 attr.insns = (uint64_t)insns; 305 attr.license = (uint64_t)"DUMMY"; 306 307 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 308 if (fd >= 0) { 309 close(fd); 310 return "v2"; 311 } 312 return "v1"; 313 #endif 314 } 315 316 #if defined(__i386__) || defined(_M_IX86) || \ 317 defined(__x86_64__) || defined(_M_X64) 318 319 enum VendorSignatures { 320 SIG_INTEL = 0x756e6547 /* Genu */, 321 SIG_AMD = 0x68747541 /* Auth */ 322 }; 323 324 enum ProcessorVendors { 325 VENDOR_INTEL = 1, 326 VENDOR_AMD, 327 VENDOR_OTHER, 328 VENDOR_MAX 329 }; 330 331 enum ProcessorTypes { 332 INTEL_BONNELL = 1, 333 INTEL_CORE2, 334 INTEL_COREI7, 335 AMDFAM10H, 336 AMDFAM15H, 337 INTEL_SILVERMONT, 338 INTEL_KNL, 339 AMD_BTVER1, 340 AMD_BTVER2, 341 AMDFAM17H, 342 INTEL_KNM, 343 // Entries below this are not in libgcc/compiler-rt. 344 INTEL_i386, 345 INTEL_i486, 346 INTEL_PENTIUM, 347 INTEL_PENTIUM_MMX, 348 INTEL_PENTIUM_PRO, 349 INTEL_PENTIUM_II, 350 INTEL_PENTIUM_III, 351 INTEL_PENTIUM_IV, 352 INTEL_PENTIUM_M, 353 INTEL_CORE_DUO, 354 INTEL_X86_64, 355 INTEL_NOCONA, 356 INTEL_PRESCOTT, 357 AMD_i486, 358 AMDPENTIUM, 359 AMDATHLON, 360 INTEL_GOLDMONT, 361 CPU_TYPE_MAX 362 }; 363 364 enum ProcessorSubtypes { 365 INTEL_COREI7_NEHALEM = 1, 366 INTEL_COREI7_WESTMERE, 367 INTEL_COREI7_SANDYBRIDGE, 368 AMDFAM10H_BARCELONA, 369 AMDFAM10H_SHANGHAI, 370 AMDFAM10H_ISTANBUL, 371 AMDFAM15H_BDVER1, 372 AMDFAM15H_BDVER2, 373 AMDFAM15H_BDVER3, 374 AMDFAM15H_BDVER4, 375 AMDFAM17H_ZNVER1, 376 INTEL_COREI7_IVYBRIDGE, 377 INTEL_COREI7_HASWELL, 378 INTEL_COREI7_BROADWELL, 379 INTEL_COREI7_SKYLAKE, 380 INTEL_COREI7_SKYLAKE_AVX512, 381 // Entries below this are not in libgcc/compiler-rt. 382 INTEL_CORE2_65, 383 INTEL_CORE2_45, 384 AMDPENTIUM_K6, 385 AMDPENTIUM_K62, 386 AMDPENTIUM_K63, 387 AMDPENTIUM_GEODE, 388 AMDATHLON_CLASSIC, 389 AMDATHLON_XP, 390 AMDATHLON_K8, 391 AMDATHLON_K8SSE3, 392 CPU_SUBTYPE_MAX 393 }; 394 395 enum ProcessorFeatures { 396 FEATURE_CMOV = 0, 397 FEATURE_MMX, 398 FEATURE_POPCNT, 399 FEATURE_SSE, 400 FEATURE_SSE2, 401 FEATURE_SSE3, 402 FEATURE_SSSE3, 403 FEATURE_SSE4_1, 404 FEATURE_SSE4_2, 405 FEATURE_AVX, 406 FEATURE_AVX2, 407 FEATURE_SSE4_A, 408 FEATURE_FMA4, 409 FEATURE_XOP, 410 FEATURE_FMA, 411 FEATURE_AVX512F, 412 FEATURE_BMI, 413 FEATURE_BMI2, 414 FEATURE_AES, 415 FEATURE_PCLMUL, 416 FEATURE_AVX512VL, 417 FEATURE_AVX512BW, 418 FEATURE_AVX512DQ, 419 FEATURE_AVX512CD, 420 FEATURE_AVX512ER, 421 FEATURE_AVX512PF, 422 FEATURE_AVX512VBMI, 423 FEATURE_AVX512IFMA, 424 FEATURE_AVX5124VNNIW, 425 FEATURE_AVX5124FMAPS, 426 FEATURE_AVX512VPOPCNTDQ, 427 // Only one bit free left in the first 32 features. 428 FEATURE_MOVBE = 32, 429 FEATURE_ADX, 430 FEATURE_EM64T, 431 FEATURE_CLFLUSHOPT, 432 FEATURE_SHA, 433 }; 434 435 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 436 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 437 // support. Consequently, for i386, the presence of CPUID is checked first 438 // via the corresponding eflags bit. 439 // Removal of cpuid.h header motivated by PR30384 440 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 441 // or test-suite, but are used in external projects e.g. libstdcxx 442 static bool isCpuIdSupported() { 443 #if defined(__GNUC__) || defined(__clang__) 444 #if defined(__i386__) 445 int __cpuid_supported; 446 __asm__(" pushfl\n" 447 " popl %%eax\n" 448 " movl %%eax,%%ecx\n" 449 " xorl $0x00200000,%%eax\n" 450 " pushl %%eax\n" 451 " popfl\n" 452 " pushfl\n" 453 " popl %%eax\n" 454 " movl $0,%0\n" 455 " cmpl %%eax,%%ecx\n" 456 " je 1f\n" 457 " movl $1,%0\n" 458 "1:" 459 : "=r"(__cpuid_supported) 460 : 461 : "eax", "ecx"); 462 if (!__cpuid_supported) 463 return false; 464 #endif 465 return true; 466 #endif 467 return true; 468 } 469 470 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 471 /// the specified arguments. If we can't run cpuid on the host, return true. 472 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 473 unsigned *rECX, unsigned *rEDX) { 474 #if defined(__GNUC__) || defined(__clang__) 475 #if defined(__x86_64__) 476 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 477 // FIXME: should we save this for Clang? 478 __asm__("movq\t%%rbx, %%rsi\n\t" 479 "cpuid\n\t" 480 "xchgq\t%%rbx, %%rsi\n\t" 481 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 482 : "a"(value)); 483 return false; 484 #elif defined(__i386__) 485 __asm__("movl\t%%ebx, %%esi\n\t" 486 "cpuid\n\t" 487 "xchgl\t%%ebx, %%esi\n\t" 488 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 489 : "a"(value)); 490 return false; 491 #else 492 return true; 493 #endif 494 #elif defined(_MSC_VER) 495 // The MSVC intrinsic is portable across x86 and x64. 496 int registers[4]; 497 __cpuid(registers, value); 498 *rEAX = registers[0]; 499 *rEBX = registers[1]; 500 *rECX = registers[2]; 501 *rEDX = registers[3]; 502 return false; 503 #else 504 return true; 505 #endif 506 } 507 508 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 509 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 510 /// return true. 511 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 512 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 513 unsigned *rEDX) { 514 #if defined(__GNUC__) || defined(__clang__) 515 #if defined(__x86_64__) 516 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 517 // FIXME: should we save this for Clang? 518 __asm__("movq\t%%rbx, %%rsi\n\t" 519 "cpuid\n\t" 520 "xchgq\t%%rbx, %%rsi\n\t" 521 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 522 : "a"(value), "c"(subleaf)); 523 return false; 524 #elif defined(__i386__) 525 __asm__("movl\t%%ebx, %%esi\n\t" 526 "cpuid\n\t" 527 "xchgl\t%%ebx, %%esi\n\t" 528 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 529 : "a"(value), "c"(subleaf)); 530 return false; 531 #else 532 return true; 533 #endif 534 #elif defined(_MSC_VER) 535 int registers[4]; 536 __cpuidex(registers, value, subleaf); 537 *rEAX = registers[0]; 538 *rEBX = registers[1]; 539 *rECX = registers[2]; 540 *rEDX = registers[3]; 541 return false; 542 #else 543 return true; 544 #endif 545 } 546 547 // Read control register 0 (XCR0). Used to detect features such as AVX. 548 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 549 #if defined(__GNUC__) || defined(__clang__) 550 // Check xgetbv; this uses a .byte sequence instead of the instruction 551 // directly because older assemblers do not include support for xgetbv and 552 // there is no easy way to conditionally compile based on the assembler used. 553 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 554 return false; 555 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 556 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 557 *rEAX = Result; 558 *rEDX = Result >> 32; 559 return false; 560 #else 561 return true; 562 #endif 563 } 564 565 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 566 unsigned *Model) { 567 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 568 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 569 if (*Family == 6 || *Family == 0xf) { 570 if (*Family == 0xf) 571 // Examine extended family ID if family ID is F. 572 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 573 // Examine extended model ID if family ID is 6 or F. 574 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 575 } 576 } 577 578 static void 579 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 580 unsigned Brand_id, unsigned Features, 581 unsigned Features2, unsigned *Type, 582 unsigned *Subtype) { 583 if (Brand_id != 0) 584 return; 585 switch (Family) { 586 case 3: 587 *Type = INTEL_i386; 588 break; 589 case 4: 590 *Type = INTEL_i486; 591 break; 592 case 5: 593 if (Features & (1 << FEATURE_MMX)) { 594 *Type = INTEL_PENTIUM_MMX; 595 break; 596 } 597 *Type = INTEL_PENTIUM; 598 break; 599 case 6: 600 switch (Model) { 601 case 0x01: // Pentium Pro processor 602 *Type = INTEL_PENTIUM_PRO; 603 break; 604 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 605 // model 03 606 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 607 // model 05, and Intel Celeron processor, model 05 608 case 0x06: // Celeron processor, model 06 609 *Type = INTEL_PENTIUM_II; 610 break; 611 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 612 // processor, model 07 613 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 614 // model 08, and Celeron processor, model 08 615 case 0x0a: // Pentium III Xeon processor, model 0Ah 616 case 0x0b: // Pentium III processor, model 0Bh 617 *Type = INTEL_PENTIUM_III; 618 break; 619 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 620 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 621 // 0Dh. All processors are manufactured using the 90 nm process. 622 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 623 // Integrated Processor with Intel QuickAssist Technology 624 *Type = INTEL_PENTIUM_M; 625 break; 626 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 627 // 0Eh. All processors are manufactured using the 65 nm process. 628 *Type = INTEL_CORE_DUO; 629 break; // yonah 630 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 631 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 632 // mobile processor, Intel Core 2 Extreme processor, Intel 633 // Pentium Dual-Core processor, Intel Xeon processor, model 634 // 0Fh. All processors are manufactured using the 65 nm process. 635 case 0x16: // Intel Celeron processor model 16h. All processors are 636 // manufactured using the 65 nm process 637 *Type = INTEL_CORE2; // "core2" 638 *Subtype = INTEL_CORE2_65; 639 break; 640 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 641 // 17h. All processors are manufactured using the 45 nm process. 642 // 643 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 644 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 645 // the 45 nm process. 646 *Type = INTEL_CORE2; // "penryn" 647 *Subtype = INTEL_CORE2_45; 648 break; 649 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 650 // processors are manufactured using the 45 nm process. 651 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 652 // As found in a Summer 2010 model iMac. 653 case 0x1f: 654 case 0x2e: // Nehalem EX 655 *Type = INTEL_COREI7; // "nehalem" 656 *Subtype = INTEL_COREI7_NEHALEM; 657 break; 658 case 0x25: // Intel Core i7, laptop version. 659 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 660 // processors are manufactured using the 32 nm process. 661 case 0x2f: // Westmere EX 662 *Type = INTEL_COREI7; // "westmere" 663 *Subtype = INTEL_COREI7_WESTMERE; 664 break; 665 case 0x2a: // Intel Core i7 processor. All processors are manufactured 666 // using the 32 nm process. 667 case 0x2d: 668 *Type = INTEL_COREI7; //"sandybridge" 669 *Subtype = INTEL_COREI7_SANDYBRIDGE; 670 break; 671 case 0x3a: 672 case 0x3e: // Ivy Bridge EP 673 *Type = INTEL_COREI7; // "ivybridge" 674 *Subtype = INTEL_COREI7_IVYBRIDGE; 675 break; 676 677 // Haswell: 678 case 0x3c: 679 case 0x3f: 680 case 0x45: 681 case 0x46: 682 *Type = INTEL_COREI7; // "haswell" 683 *Subtype = INTEL_COREI7_HASWELL; 684 break; 685 686 // Broadwell: 687 case 0x3d: 688 case 0x47: 689 case 0x4f: 690 case 0x56: 691 *Type = INTEL_COREI7; // "broadwell" 692 *Subtype = INTEL_COREI7_BROADWELL; 693 break; 694 695 // Skylake: 696 case 0x4e: // Skylake mobile 697 case 0x5e: // Skylake desktop 698 case 0x8e: // Kaby Lake mobile 699 case 0x9e: // Kaby Lake desktop 700 *Type = INTEL_COREI7; // "skylake" 701 *Subtype = INTEL_COREI7_SKYLAKE; 702 break; 703 704 // Skylake Xeon: 705 case 0x55: 706 *Type = INTEL_COREI7; 707 *Subtype = INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 708 break; 709 710 case 0x1c: // Most 45 nm Intel Atom processors 711 case 0x26: // 45 nm Atom Lincroft 712 case 0x27: // 32 nm Atom Medfield 713 case 0x35: // 32 nm Atom Midview 714 case 0x36: // 32 nm Atom Midview 715 *Type = INTEL_BONNELL; 716 break; // "bonnell" 717 718 // Atom Silvermont codes from the Intel software optimization guide. 719 case 0x37: 720 case 0x4a: 721 case 0x4d: 722 case 0x5a: 723 case 0x5d: 724 case 0x4c: // really airmont 725 *Type = INTEL_SILVERMONT; 726 break; // "silvermont" 727 // Goldmont: 728 case 0x5c: 729 case 0x5f: 730 *Type = INTEL_GOLDMONT; 731 break; // "goldmont" 732 case 0x57: 733 *Type = INTEL_KNL; // knl 734 break; 735 case 0x85: 736 *Type = INTEL_KNM; // knm 737 break; 738 739 default: // Unknown family 6 CPU, try to guess. 740 if (Features & (1 << FEATURE_AVX512F)) { 741 if (Features & (1 << FEATURE_AVX512VL)) { 742 *Type = INTEL_COREI7; 743 *Subtype = INTEL_COREI7_SKYLAKE_AVX512; 744 } else { 745 *Type = INTEL_KNL; // knl 746 } 747 break; 748 } 749 if (Features2 & (1 << (FEATURE_CLFLUSHOPT - 32))) { 750 if (Features2 & (1 << (FEATURE_SHA - 32))) { 751 *Type = INTEL_GOLDMONT; 752 } else { 753 *Type = INTEL_COREI7; 754 *Subtype = INTEL_COREI7_SKYLAKE; 755 } 756 break; 757 } 758 if (Features2 & (1 << (FEATURE_ADX - 32))) { 759 *Type = INTEL_COREI7; 760 *Subtype = INTEL_COREI7_BROADWELL; 761 break; 762 } 763 if (Features & (1 << FEATURE_AVX2)) { 764 *Type = INTEL_COREI7; 765 *Subtype = INTEL_COREI7_HASWELL; 766 break; 767 } 768 if (Features & (1 << FEATURE_AVX)) { 769 *Type = INTEL_COREI7; 770 *Subtype = INTEL_COREI7_SANDYBRIDGE; 771 break; 772 } 773 if (Features & (1 << FEATURE_SSE4_2)) { 774 if (Features2 & (1 << (FEATURE_MOVBE - 32))) { 775 *Type = INTEL_SILVERMONT; 776 } else { 777 *Type = INTEL_COREI7; 778 *Subtype = INTEL_COREI7_NEHALEM; 779 } 780 break; 781 } 782 if (Features & (1 << FEATURE_SSE4_1)) { 783 *Type = INTEL_CORE2; // "penryn" 784 *Subtype = INTEL_CORE2_45; 785 break; 786 } 787 if (Features & (1 << FEATURE_SSSE3)) { 788 if (Features2 & (1 << (FEATURE_MOVBE - 32))) { 789 *Type = INTEL_BONNELL; // "bonnell" 790 } else { 791 *Type = INTEL_CORE2; // "core2" 792 *Subtype = INTEL_CORE2_65; 793 } 794 break; 795 } 796 if (Features2 & (1 << (FEATURE_EM64T - 32))) { 797 *Type = INTEL_X86_64; 798 break; // x86-64 799 } 800 if (Features & (1 << FEATURE_SSE2)) { 801 *Type = INTEL_PENTIUM_M; 802 break; 803 } 804 if (Features & (1 << FEATURE_SSE)) { 805 *Type = INTEL_PENTIUM_III; 806 break; 807 } 808 if (Features & (1 << FEATURE_MMX)) { 809 *Type = INTEL_PENTIUM_II; 810 break; 811 } 812 *Type = INTEL_PENTIUM_PRO; 813 break; 814 } 815 break; 816 case 15: { 817 switch (Model) { 818 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are 819 // model 00h and manufactured using the 0.18 micron process. 820 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon 821 // processor MP, and Intel Celeron processor. All processors are 822 // model 01h and manufactured using the 0.18 micron process. 823 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M, 824 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron 825 // processor, and Mobile Intel Celeron processor. All processors 826 // are model 02h and manufactured using the 0.13 micron process. 827 *Type = ((Features2 & (1 << (FEATURE_EM64T - 32))) ? INTEL_X86_64 828 : INTEL_PENTIUM_IV); 829 break; 830 831 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D 832 // processor. All processors are model 03h and manufactured using 833 // the 90 nm process. 834 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition, 835 // Pentium D processor, Intel Xeon processor, Intel Xeon 836 // processor MP, Intel Celeron D processor. All processors are 837 // model 04h and manufactured using the 90 nm process. 838 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor 839 // Extreme Edition, Intel Xeon processor, Intel Xeon processor 840 // MP, Intel Celeron D processor. All processors are model 06h 841 // and manufactured using the 65 nm process. 842 *Type = ((Features2 & (1 << (FEATURE_EM64T - 32))) ? INTEL_NOCONA 843 : INTEL_PRESCOTT); 844 break; 845 846 default: 847 *Type = ((Features2 & (1 << (FEATURE_EM64T - 32))) ? INTEL_X86_64 848 : INTEL_PENTIUM_IV); 849 break; 850 } 851 break; 852 } 853 default: 854 break; /*"generic"*/ 855 } 856 } 857 858 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 859 unsigned Features, unsigned *Type, 860 unsigned *Subtype) { 861 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 862 // appears to be no way to generate the wide variety of AMD-specific targets 863 // from the information returned from CPUID. 864 switch (Family) { 865 case 4: 866 *Type = AMD_i486; 867 break; 868 case 5: 869 *Type = AMDPENTIUM; 870 switch (Model) { 871 case 6: 872 case 7: 873 *Subtype = AMDPENTIUM_K6; 874 break; // "k6" 875 case 8: 876 *Subtype = AMDPENTIUM_K62; 877 break; // "k6-2" 878 case 9: 879 case 13: 880 *Subtype = AMDPENTIUM_K63; 881 break; // "k6-3" 882 case 10: 883 *Subtype = AMDPENTIUM_GEODE; 884 break; // "geode" 885 } 886 break; 887 case 6: 888 *Type = AMDATHLON; 889 if (Features & (1 << FEATURE_SSE)) { 890 *Subtype = AMDATHLON_XP; 891 break; // "athlon-xp" 892 } 893 *Subtype = AMDATHLON_CLASSIC; 894 break; // "athlon" 895 case 15: 896 *Type = AMDATHLON; 897 if (Features & (1 << FEATURE_SSE3)) { 898 *Subtype = AMDATHLON_K8SSE3; 899 break; // "k8-sse3" 900 } 901 *Subtype = AMDATHLON_K8; 902 break; // "k8" 903 case 16: 904 *Type = AMDFAM10H; // "amdfam10" 905 switch (Model) { 906 case 2: 907 *Subtype = AMDFAM10H_BARCELONA; 908 break; 909 case 4: 910 *Subtype = AMDFAM10H_SHANGHAI; 911 break; 912 case 8: 913 *Subtype = AMDFAM10H_ISTANBUL; 914 break; 915 } 916 break; 917 case 20: 918 *Type = AMD_BTVER1; 919 break; // "btver1"; 920 case 21: 921 *Type = AMDFAM15H; 922 if (Model >= 0x60 && Model <= 0x7f) { 923 *Subtype = AMDFAM15H_BDVER4; 924 break; // "bdver4"; 60h-7Fh: Excavator 925 } 926 if (Model >= 0x30 && Model <= 0x3f) { 927 *Subtype = AMDFAM15H_BDVER3; 928 break; // "bdver3"; 30h-3Fh: Steamroller 929 } 930 if (Model >= 0x10 && Model <= 0x1f) { 931 *Subtype = AMDFAM15H_BDVER2; 932 break; // "bdver2"; 10h-1Fh: Piledriver 933 } 934 if (Model <= 0x0f) { 935 *Subtype = AMDFAM15H_BDVER1; 936 break; // "bdver1"; 00h-0Fh: Bulldozer 937 } 938 break; 939 case 22: 940 *Type = AMD_BTVER2; 941 break; // "btver2" 942 case 23: 943 *Type = AMDFAM17H; 944 *Subtype = AMDFAM17H_ZNVER1; 945 break; 946 default: 947 break; // "generic" 948 } 949 } 950 951 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 952 unsigned *FeaturesOut, 953 unsigned *Features2Out) { 954 unsigned Features = 0; 955 unsigned Features2 = 0; 956 unsigned EAX, EBX; 957 958 if ((EDX >> 15) & 1) 959 Features |= 1 << FEATURE_CMOV; 960 if ((EDX >> 23) & 1) 961 Features |= 1 << FEATURE_MMX; 962 if ((EDX >> 25) & 1) 963 Features |= 1 << FEATURE_SSE; 964 if ((EDX >> 26) & 1) 965 Features |= 1 << FEATURE_SSE2; 966 967 if ((ECX >> 0) & 1) 968 Features |= 1 << FEATURE_SSE3; 969 if ((ECX >> 1) & 1) 970 Features |= 1 << FEATURE_PCLMUL; 971 if ((ECX >> 9) & 1) 972 Features |= 1 << FEATURE_SSSE3; 973 if ((ECX >> 12) & 1) 974 Features |= 1 << FEATURE_FMA; 975 if ((ECX >> 19) & 1) 976 Features |= 1 << FEATURE_SSE4_1; 977 if ((ECX >> 20) & 1) 978 Features |= 1 << FEATURE_SSE4_2; 979 if ((ECX >> 23) & 1) 980 Features |= 1 << FEATURE_POPCNT; 981 if ((ECX >> 25) & 1) 982 Features |= 1 << FEATURE_AES; 983 984 if ((ECX >> 22) & 1) 985 Features2 |= 1 << (FEATURE_MOVBE - 32); 986 987 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 988 // indicates that the AVX registers will be saved and restored on context 989 // switch, then we have full AVX support. 990 const unsigned AVXBits = (1 << 27) | (1 << 28); 991 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 992 ((EAX & 0x6) == 0x6); 993 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 994 995 if (HasAVX) 996 Features |= 1 << FEATURE_AVX; 997 998 bool HasLeaf7 = 999 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1000 1001 if (HasLeaf7 && ((EBX >> 3) & 1)) 1002 Features |= 1 << FEATURE_BMI; 1003 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 1004 Features |= 1 << FEATURE_AVX2; 1005 if (HasLeaf7 && ((EBX >> 9) & 1)) 1006 Features |= 1 << FEATURE_BMI2; 1007 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 1008 Features |= 1 << FEATURE_AVX512F; 1009 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 1010 Features |= 1 << FEATURE_AVX512DQ; 1011 if (HasLeaf7 && ((EBX >> 19) & 1)) 1012 Features2 |= 1 << (FEATURE_ADX - 32); 1013 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 1014 Features |= 1 << FEATURE_AVX512IFMA; 1015 if (HasLeaf7 && ((EBX >> 23) & 1)) 1016 Features2 |= 1 << (FEATURE_CLFLUSHOPT - 32); 1017 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 1018 Features |= 1 << FEATURE_AVX512PF; 1019 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 1020 Features |= 1 << FEATURE_AVX512ER; 1021 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 1022 Features |= 1 << FEATURE_AVX512CD; 1023 if (HasLeaf7 && ((EBX >> 29) & 1)) 1024 Features2 |= 1 << (FEATURE_SHA - 32); 1025 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 1026 Features |= 1 << FEATURE_AVX512BW; 1027 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 1028 Features |= 1 << FEATURE_AVX512VL; 1029 1030 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 1031 Features |= 1 << FEATURE_AVX512VBMI; 1032 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1033 Features |= 1 << FEATURE_AVX512VPOPCNTDQ; 1034 1035 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1036 Features |= 1 << FEATURE_AVX5124VNNIW; 1037 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1038 Features |= 1 << FEATURE_AVX5124FMAPS; 1039 1040 unsigned MaxExtLevel; 1041 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1042 1043 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1044 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1045 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1046 Features |= 1 << FEATURE_SSE4_A; 1047 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1048 Features |= 1 << FEATURE_XOP; 1049 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1050 Features |= 1 << FEATURE_FMA4; 1051 1052 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1053 Features2 |= 1 << (FEATURE_EM64T - 32); 1054 1055 *FeaturesOut = Features; 1056 *Features2Out = Features2; 1057 } 1058 1059 StringRef sys::getHostCPUName() { 1060 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1061 unsigned MaxLeaf, Vendor; 1062 1063 #if defined(__GNUC__) || defined(__clang__) 1064 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here 1065 // and simplify it to not invoke __cpuid (like cpu_model.c in 1066 // compiler-rt/lib/builtins/cpu_model.c? 1067 // Opting for the second option. 1068 if(!isCpuIdSupported()) 1069 return "generic"; 1070 #endif 1071 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) 1072 return "generic"; 1073 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1074 1075 unsigned Brand_id = EBX & 0xff; 1076 unsigned Family = 0, Model = 0; 1077 unsigned Features = 0, Features2 = 0; 1078 detectX86FamilyModel(EAX, &Family, &Model); 1079 getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2); 1080 1081 unsigned Type; 1082 unsigned Subtype; 1083 1084 if (Vendor == SIG_INTEL) { 1085 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, 1086 Features2, &Type, &Subtype); 1087 switch (Type) { 1088 case INTEL_i386: 1089 return "i386"; 1090 case INTEL_i486: 1091 return "i486"; 1092 case INTEL_PENTIUM: 1093 return "pentium"; 1094 case INTEL_PENTIUM_MMX: 1095 return "pentium-mmx"; 1096 case INTEL_PENTIUM_PRO: 1097 return "pentiumpro"; 1098 case INTEL_PENTIUM_II: 1099 return "pentium2"; 1100 case INTEL_PENTIUM_III: 1101 return "pentium3"; 1102 case INTEL_PENTIUM_IV: 1103 return "pentium4"; 1104 case INTEL_PENTIUM_M: 1105 return "pentium-m"; 1106 case INTEL_CORE_DUO: 1107 return "yonah"; 1108 case INTEL_CORE2: 1109 switch (Subtype) { 1110 case INTEL_CORE2_65: 1111 return "core2"; 1112 case INTEL_CORE2_45: 1113 return "penryn"; 1114 default: 1115 llvm_unreachable("Unexpected subtype!"); 1116 } 1117 case INTEL_COREI7: 1118 switch (Subtype) { 1119 case INTEL_COREI7_NEHALEM: 1120 return "nehalem"; 1121 case INTEL_COREI7_WESTMERE: 1122 return "westmere"; 1123 case INTEL_COREI7_SANDYBRIDGE: 1124 return "sandybridge"; 1125 case INTEL_COREI7_IVYBRIDGE: 1126 return "ivybridge"; 1127 case INTEL_COREI7_HASWELL: 1128 return "haswell"; 1129 case INTEL_COREI7_BROADWELL: 1130 return "broadwell"; 1131 case INTEL_COREI7_SKYLAKE: 1132 return "skylake"; 1133 case INTEL_COREI7_SKYLAKE_AVX512: 1134 return "skylake-avx512"; 1135 default: 1136 llvm_unreachable("Unexpected subtype!"); 1137 } 1138 case INTEL_BONNELL: 1139 return "bonnell"; 1140 case INTEL_SILVERMONT: 1141 return "silvermont"; 1142 case INTEL_GOLDMONT: 1143 return "goldmont"; 1144 case INTEL_KNL: 1145 return "knl"; 1146 case INTEL_KNM: 1147 return "knm"; 1148 case INTEL_X86_64: 1149 return "x86-64"; 1150 case INTEL_NOCONA: 1151 return "nocona"; 1152 case INTEL_PRESCOTT: 1153 return "prescott"; 1154 default: 1155 break; 1156 } 1157 } else if (Vendor == SIG_AMD) { 1158 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1159 switch (Type) { 1160 case AMD_i486: 1161 return "i486"; 1162 case AMDPENTIUM: 1163 switch (Subtype) { 1164 case AMDPENTIUM_K6: 1165 return "k6"; 1166 case AMDPENTIUM_K62: 1167 return "k6-2"; 1168 case AMDPENTIUM_K63: 1169 return "k6-3"; 1170 case AMDPENTIUM_GEODE: 1171 return "geode"; 1172 default: 1173 return "pentium"; 1174 } 1175 case AMDATHLON: 1176 switch (Subtype) { 1177 case AMDATHLON_CLASSIC: 1178 return "athlon"; 1179 case AMDATHLON_XP: 1180 return "athlon-xp"; 1181 case AMDATHLON_K8: 1182 return "k8"; 1183 case AMDATHLON_K8SSE3: 1184 return "k8-sse3"; 1185 default: 1186 llvm_unreachable("Unexpected subtype!"); 1187 } 1188 case AMDFAM10H: 1189 return "amdfam10"; 1190 case AMD_BTVER1: 1191 return "btver1"; 1192 case AMDFAM15H: 1193 switch (Subtype) { 1194 default: // There are gaps in the subtype detection. 1195 case AMDFAM15H_BDVER1: 1196 return "bdver1"; 1197 case AMDFAM15H_BDVER2: 1198 return "bdver2"; 1199 case AMDFAM15H_BDVER3: 1200 return "bdver3"; 1201 case AMDFAM15H_BDVER4: 1202 return "bdver4"; 1203 } 1204 case AMD_BTVER2: 1205 return "btver2"; 1206 case AMDFAM17H: 1207 return "znver1"; 1208 default: 1209 break; 1210 } 1211 } 1212 return "generic"; 1213 } 1214 1215 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1216 StringRef sys::getHostCPUName() { 1217 host_basic_info_data_t hostInfo; 1218 mach_msg_type_number_t infoCount; 1219 1220 infoCount = HOST_BASIC_INFO_COUNT; 1221 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo, 1222 &infoCount); 1223 1224 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1225 return "generic"; 1226 1227 switch (hostInfo.cpu_subtype) { 1228 case CPU_SUBTYPE_POWERPC_601: 1229 return "601"; 1230 case CPU_SUBTYPE_POWERPC_602: 1231 return "602"; 1232 case CPU_SUBTYPE_POWERPC_603: 1233 return "603"; 1234 case CPU_SUBTYPE_POWERPC_603e: 1235 return "603e"; 1236 case CPU_SUBTYPE_POWERPC_603ev: 1237 return "603ev"; 1238 case CPU_SUBTYPE_POWERPC_604: 1239 return "604"; 1240 case CPU_SUBTYPE_POWERPC_604e: 1241 return "604e"; 1242 case CPU_SUBTYPE_POWERPC_620: 1243 return "620"; 1244 case CPU_SUBTYPE_POWERPC_750: 1245 return "750"; 1246 case CPU_SUBTYPE_POWERPC_7400: 1247 return "7400"; 1248 case CPU_SUBTYPE_POWERPC_7450: 1249 return "7450"; 1250 case CPU_SUBTYPE_POWERPC_970: 1251 return "970"; 1252 default:; 1253 } 1254 1255 return "generic"; 1256 } 1257 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1258 StringRef sys::getHostCPUName() { 1259 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1260 const StringRef& Content = P ? P->getBuffer() : ""; 1261 return detail::getHostCPUNameForPowerPC(Content); 1262 } 1263 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1264 StringRef sys::getHostCPUName() { 1265 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1266 const StringRef& Content = P ? P->getBuffer() : ""; 1267 return detail::getHostCPUNameForARM(Content); 1268 } 1269 #elif defined(__linux__) && defined(__s390x__) 1270 StringRef sys::getHostCPUName() { 1271 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1272 const StringRef& Content = P ? P->getBuffer() : ""; 1273 return detail::getHostCPUNameForS390x(Content); 1274 } 1275 #else 1276 StringRef sys::getHostCPUName() { return "generic"; } 1277 #endif 1278 1279 #if defined(__linux__) && defined(__x86_64__) 1280 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1281 // using the number of unique physical/core id pairs. The following 1282 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1283 static int computeHostNumPhysicalCores() { 1284 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1285 // mmapped because it appears to have 0 size. 1286 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1287 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1288 if (std::error_code EC = Text.getError()) { 1289 llvm::errs() << "Can't read " 1290 << "/proc/cpuinfo: " << EC.message() << "\n"; 1291 return -1; 1292 } 1293 SmallVector<StringRef, 8> strs; 1294 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1295 /*KeepEmpty=*/false); 1296 int CurPhysicalId = -1; 1297 int CurCoreId = -1; 1298 SmallSet<std::pair<int, int>, 32> UniqueItems; 1299 for (auto &Line : strs) { 1300 Line = Line.trim(); 1301 if (!Line.startswith("physical id") && !Line.startswith("core id")) 1302 continue; 1303 std::pair<StringRef, StringRef> Data = Line.split(':'); 1304 auto Name = Data.first.trim(); 1305 auto Val = Data.second.trim(); 1306 if (Name == "physical id") { 1307 assert(CurPhysicalId == -1 && 1308 "Expected a core id before seeing another physical id"); 1309 Val.getAsInteger(10, CurPhysicalId); 1310 } 1311 if (Name == "core id") { 1312 assert(CurCoreId == -1 && 1313 "Expected a physical id before seeing another core id"); 1314 Val.getAsInteger(10, CurCoreId); 1315 } 1316 if (CurPhysicalId != -1 && CurCoreId != -1) { 1317 UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId)); 1318 CurPhysicalId = -1; 1319 CurCoreId = -1; 1320 } 1321 } 1322 return UniqueItems.size(); 1323 } 1324 #elif defined(__APPLE__) && defined(__x86_64__) 1325 #include <sys/param.h> 1326 #include <sys/sysctl.h> 1327 1328 // Gets the number of *physical cores* on the machine. 1329 static int computeHostNumPhysicalCores() { 1330 uint32_t count; 1331 size_t len = sizeof(count); 1332 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1333 if (count < 1) { 1334 int nm[2]; 1335 nm[0] = CTL_HW; 1336 nm[1] = HW_AVAILCPU; 1337 sysctl(nm, 2, &count, &len, NULL, 0); 1338 if (count < 1) 1339 return -1; 1340 } 1341 return count; 1342 } 1343 #else 1344 // On other systems, return -1 to indicate unknown. 1345 static int computeHostNumPhysicalCores() { return -1; } 1346 #endif 1347 1348 int sys::getHostNumPhysicalCores() { 1349 static int NumCores = computeHostNumPhysicalCores(); 1350 return NumCores; 1351 } 1352 1353 #if defined(__i386__) || defined(_M_IX86) || \ 1354 defined(__x86_64__) || defined(_M_X64) 1355 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1356 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1357 unsigned MaxLevel; 1358 union { 1359 unsigned u[3]; 1360 char c[12]; 1361 } text; 1362 1363 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1364 MaxLevel < 1) 1365 return false; 1366 1367 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1368 1369 Features["cmov"] = (EDX >> 15) & 1; 1370 Features["mmx"] = (EDX >> 23) & 1; 1371 Features["sse"] = (EDX >> 25) & 1; 1372 Features["sse2"] = (EDX >> 26) & 1; 1373 Features["sse3"] = (ECX >> 0) & 1; 1374 Features["ssse3"] = (ECX >> 9) & 1; 1375 Features["sse4.1"] = (ECX >> 19) & 1; 1376 Features["sse4.2"] = (ECX >> 20) & 1; 1377 1378 Features["pclmul"] = (ECX >> 1) & 1; 1379 Features["cx16"] = (ECX >> 13) & 1; 1380 Features["movbe"] = (ECX >> 22) & 1; 1381 Features["popcnt"] = (ECX >> 23) & 1; 1382 Features["aes"] = (ECX >> 25) & 1; 1383 Features["rdrnd"] = (ECX >> 30) & 1; 1384 1385 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1386 // indicates that the AVX registers will be saved and restored on context 1387 // switch, then we have full AVX support. 1388 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1389 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1390 Features["avx"] = HasAVXSave; 1391 Features["fma"] = HasAVXSave && (ECX >> 12) & 1; 1392 Features["f16c"] = HasAVXSave && (ECX >> 29) & 1; 1393 1394 // Only enable XSAVE if OS has enabled support for saving YMM state. 1395 Features["xsave"] = HasAVXSave && (ECX >> 26) & 1; 1396 1397 // AVX512 requires additional context to be saved by the OS. 1398 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1399 1400 unsigned MaxExtLevel; 1401 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1402 1403 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1404 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1405 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1406 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1407 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1408 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1409 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1410 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1411 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1412 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1413 1414 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1415 !getX86CpuIDAndInfoEx(0x80000008,0x0, &EAX, &EBX, &ECX, &EDX); 1416 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1417 1418 bool HasLeaf7 = 1419 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1420 1421 // AVX2 is only supported if we have the OS save support from AVX. 1422 Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1); 1423 1424 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1425 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1426 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1427 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1428 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1429 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1430 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1431 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1432 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1433 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1434 1435 // AVX512 is only supported if the OS supports the context save for it. 1436 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1437 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1438 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1439 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1440 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1441 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1442 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1443 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1444 1445 Features["prefetchwt1"] = HasLeaf7 && (ECX & 1); 1446 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1447 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1448 // Enable protection keys 1449 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1450 1451 bool HasLeafD = MaxLevel >= 0xd && 1452 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1453 1454 // Only enable XSAVE if OS has enabled support for saving YMM state. 1455 Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1); 1456 Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1); 1457 Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1); 1458 1459 return true; 1460 } 1461 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1462 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1463 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1464 if (!P) 1465 return false; 1466 1467 SmallVector<StringRef, 32> Lines; 1468 P->getBuffer().split(Lines, "\n"); 1469 1470 SmallVector<StringRef, 32> CPUFeatures; 1471 1472 // Look for the CPU features. 1473 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1474 if (Lines[I].startswith("Features")) { 1475 Lines[I].split(CPUFeatures, ' '); 1476 break; 1477 } 1478 1479 #if defined(__aarch64__) 1480 // Keep track of which crypto features we have seen 1481 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1482 uint32_t crypto = 0; 1483 #endif 1484 1485 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1486 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1487 #if defined(__aarch64__) 1488 .Case("asimd", "neon") 1489 .Case("fp", "fp-armv8") 1490 .Case("crc32", "crc") 1491 #else 1492 .Case("half", "fp16") 1493 .Case("neon", "neon") 1494 .Case("vfpv3", "vfp3") 1495 .Case("vfpv3d16", "d16") 1496 .Case("vfpv4", "vfp4") 1497 .Case("idiva", "hwdiv-arm") 1498 .Case("idivt", "hwdiv") 1499 #endif 1500 .Default(""); 1501 1502 #if defined(__aarch64__) 1503 // We need to check crypto separately since we need all of the crypto 1504 // extensions to enable the subtarget feature 1505 if (CPUFeatures[I] == "aes") 1506 crypto |= CAP_AES; 1507 else if (CPUFeatures[I] == "pmull") 1508 crypto |= CAP_PMULL; 1509 else if (CPUFeatures[I] == "sha1") 1510 crypto |= CAP_SHA1; 1511 else if (CPUFeatures[I] == "sha2") 1512 crypto |= CAP_SHA2; 1513 #endif 1514 1515 if (LLVMFeatureStr != "") 1516 Features[LLVMFeatureStr] = true; 1517 } 1518 1519 #if defined(__aarch64__) 1520 // If we have all crypto bits we can add the feature 1521 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1522 Features["crypto"] = true; 1523 #endif 1524 1525 return true; 1526 } 1527 #else 1528 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1529 #endif 1530 1531 std::string sys::getProcessTriple() { 1532 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1533 Triple PT(Triple::normalize(TargetTripleString)); 1534 1535 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1536 PT = PT.get64BitArchVariant(); 1537 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1538 PT = PT.get32BitArchVariant(); 1539 1540 return PT.str(); 1541 } 1542